1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/types.h>
11 #include <linux/uuid.h>
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25 #define NVME_RDMA_IP_PORT 4420
27 #define NVME_NSID_ALL 0xffffffff
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
45 NVMF_TRTYPE_RDMA = 1, /* RDMA */
46 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
47 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
48 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
54 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
55 NVMF_TREQ_REQUIRED = 1, /* Required */
56 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
57 #define NVME_TREQ_SECURE_CHANNEL_MASK \
58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
60 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
82 /* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
89 #define NVME_AQ_DEPTH 32
90 #define NVME_NR_AEN_COMMANDS 1
91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
95 * NVM-Express 1.2 specification, section 4.1.2.
97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
100 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
101 NVME_REG_VS = 0x0008, /* Version */
102 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
103 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
104 NVME_REG_CC = 0x0014, /* Controller Configuration */
105 NVME_REG_CSTS = 0x001c, /* Controller Status */
106 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
107 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
108 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
109 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
110 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
111 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
112 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
113 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
114 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
117 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
118 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
119 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
120 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
123 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
126 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
129 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
130 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
131 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
132 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
133 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
134 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
136 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
137 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
140 NVME_CMBSZ_SQS = 1 << 0,
141 NVME_CMBSZ_CQS = 1 << 1,
142 NVME_CMBSZ_LISTS = 1 << 2,
143 NVME_CMBSZ_RDS = 1 << 3,
144 NVME_CMBSZ_WDS = 1 << 4,
146 NVME_CMBSZ_SZ_SHIFT = 12,
147 NVME_CMBSZ_SZ_MASK = 0xfffff,
149 NVME_CMBSZ_SZU_SHIFT = 8,
150 NVME_CMBSZ_SZU_MASK = 0xf,
154 * Submission and Completion Queue Entry Sizes for the NVM command set.
155 * (In bytes and specified as a power of two (2^n)).
157 #define NVME_ADM_SQES 6
158 #define NVME_NVM_IOSQES 6
159 #define NVME_NVM_IOCQES 4
162 NVME_CC_ENABLE = 1 << 0,
163 NVME_CC_CSS_NVM = 0 << 4,
164 NVME_CC_EN_SHIFT = 0,
165 NVME_CC_CSS_SHIFT = 4,
166 NVME_CC_MPS_SHIFT = 7,
167 NVME_CC_AMS_SHIFT = 11,
168 NVME_CC_SHN_SHIFT = 14,
169 NVME_CC_IOSQES_SHIFT = 16,
170 NVME_CC_IOCQES_SHIFT = 20,
171 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
172 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
173 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
174 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
175 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
176 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
177 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
178 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
179 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
180 NVME_CSTS_RDY = 1 << 0,
181 NVME_CSTS_CFS = 1 << 1,
182 NVME_CSTS_NSSRO = 1 << 4,
183 NVME_CSTS_PP = 1 << 5,
184 NVME_CSTS_SHST_NORMAL = 0 << 2,
185 NVME_CSTS_SHST_OCCUR = 1 << 2,
186 NVME_CSTS_SHST_CMPLT = 2 << 2,
187 NVME_CSTS_SHST_MASK = 3 << 2,
190 struct nvme_id_power_state {
191 __le16 max_power; /* centiwatts */
194 __le32 entry_lat; /* microseconds */
195 __le32 exit_lat; /* microseconds */
204 __u8 active_work_scale;
209 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
210 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
213 enum nvme_ctrl_attr {
214 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
215 NVME_CTRL_ATTR_TBKAS = (1 << 6),
218 struct nvme_id_ctrl {
297 struct nvme_id_power_state psd[32];
302 NVME_CTRL_ONCS_COMPARE = 1 << 0,
303 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
304 NVME_CTRL_ONCS_DSM = 1 << 2,
305 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
306 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
307 NVME_CTRL_VWC_PRESENT = 1 << 0,
308 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
309 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
310 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
311 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
312 NVME_CTRL_CTRATT_128_ID = 1 << 0,
313 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
314 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
315 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
316 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
317 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
318 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
319 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
363 struct nvme_lbaf lbaf[16];
369 NVME_ID_CNS_NS = 0x00,
370 NVME_ID_CNS_CTRL = 0x01,
371 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
372 NVME_ID_CNS_NS_DESC_LIST = 0x03,
373 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
374 NVME_ID_CNS_NS_PRESENT = 0x11,
375 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
376 NVME_ID_CNS_CTRL_LIST = 0x13,
377 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
378 NVME_ID_CNS_NS_GRANULARITY = 0x16,
379 NVME_ID_CNS_UUID_LIST = 0x17,
383 NVME_DIR_IDENTIFY = 0x00,
384 NVME_DIR_STREAMS = 0x01,
385 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
386 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
387 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
388 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
389 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
390 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
391 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
392 NVME_DIR_ENDIR = 0x01,
396 NVME_NS_FEAT_THIN = 1 << 0,
397 NVME_NS_FLBAS_LBA_MASK = 0xf,
398 NVME_NS_FLBAS_META_EXT = 0x10,
399 NVME_LBAF_RP_BEST = 0,
400 NVME_LBAF_RP_BETTER = 1,
401 NVME_LBAF_RP_GOOD = 2,
402 NVME_LBAF_RP_DEGRADED = 3,
403 NVME_NS_DPC_PI_LAST = 1 << 4,
404 NVME_NS_DPC_PI_FIRST = 1 << 3,
405 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
406 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
407 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
408 NVME_NS_DPS_PI_FIRST = 1 << 3,
409 NVME_NS_DPS_PI_MASK = 0x7,
410 NVME_NS_DPS_PI_TYPE1 = 1,
411 NVME_NS_DPS_PI_TYPE2 = 2,
412 NVME_NS_DPS_PI_TYPE3 = 3,
415 struct nvme_ns_id_desc {
421 #define NVME_NIDT_EUI64_LEN 8
422 #define NVME_NIDT_NGUID_LEN 16
423 #define NVME_NIDT_UUID_LEN 16
426 NVME_NIDT_EUI64 = 0x01,
427 NVME_NIDT_NGUID = 0x02,
428 NVME_NIDT_UUID = 0x03,
431 struct nvme_smart_log {
432 __u8 critical_warning;
437 __u8 endu_grp_crit_warn_sumry;
439 __u8 data_units_read[16];
440 __u8 data_units_written[16];
442 __u8 host_writes[16];
443 __u8 ctrl_busy_time[16];
444 __u8 power_cycles[16];
445 __u8 power_on_hours[16];
446 __u8 unsafe_shutdowns[16];
447 __u8 media_errors[16];
448 __u8 num_err_log_entries[16];
449 __le32 warning_temp_time;
450 __le32 critical_comp_time;
451 __le16 temp_sensor[8];
452 __le32 thm_temp1_trans_count;
453 __le32 thm_temp2_trans_count;
454 __le32 thm_temp1_total_time;
455 __le32 thm_temp2_total_time;
459 struct nvme_fw_slot_info_log {
467 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
468 NVME_CMD_EFFECTS_LBCC = 1 << 1,
469 NVME_CMD_EFFECTS_NCC = 1 << 2,
470 NVME_CMD_EFFECTS_NIC = 1 << 3,
471 NVME_CMD_EFFECTS_CCC = 1 << 4,
472 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
473 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
476 struct nvme_effects_log {
482 enum nvme_ana_state {
483 NVME_ANA_OPTIMIZED = 0x01,
484 NVME_ANA_NONOPTIMIZED = 0x02,
485 NVME_ANA_INACCESSIBLE = 0x03,
486 NVME_ANA_PERSISTENT_LOSS = 0x04,
487 NVME_ANA_CHANGE = 0x0f,
490 struct nvme_ana_group_desc {
499 /* flag for the log specific field of the ANA log */
500 #define NVME_ANA_LOG_RGO (1 << 0)
502 struct nvme_ana_rsp_hdr {
509 NVME_SMART_CRIT_SPARE = 1 << 0,
510 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
511 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
512 NVME_SMART_CRIT_MEDIA = 1 << 3,
513 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
525 NVME_AER_NOTICE_NS_CHANGED = 0x00,
526 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
527 NVME_AER_NOTICE_ANA = 0x03,
528 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
532 NVME_AEN_BIT_NS_ATTR = 8,
533 NVME_AEN_BIT_FW_ACT = 9,
534 NVME_AEN_BIT_ANA_CHANGE = 11,
535 NVME_AEN_BIT_DISC_CHANGE = 31,
539 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
540 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
541 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
542 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
545 struct nvme_lba_range_type {
556 NVME_LBART_TYPE_FS = 0x01,
557 NVME_LBART_TYPE_RAID = 0x02,
558 NVME_LBART_TYPE_CACHE = 0x03,
559 NVME_LBART_TYPE_SWAP = 0x04,
561 NVME_LBART_ATTRIB_TEMP = 1 << 0,
562 NVME_LBART_ATTRIB_HIDE = 1 << 1,
565 struct nvme_reservation_status {
581 enum nvme_async_event_type {
582 NVME_AER_TYPE_ERROR = 0,
583 NVME_AER_TYPE_SMART = 1,
584 NVME_AER_TYPE_NOTICE = 2,
590 nvme_cmd_flush = 0x00,
591 nvme_cmd_write = 0x01,
592 nvme_cmd_read = 0x02,
593 nvme_cmd_write_uncor = 0x04,
594 nvme_cmd_compare = 0x05,
595 nvme_cmd_write_zeroes = 0x08,
597 nvme_cmd_verify = 0x0c,
598 nvme_cmd_resv_register = 0x0d,
599 nvme_cmd_resv_report = 0x0e,
600 nvme_cmd_resv_acquire = 0x11,
601 nvme_cmd_resv_release = 0x15,
604 #define nvme_opcode_name(opcode) { opcode, #opcode }
605 #define show_nvm_opcode_name(val) \
606 __print_symbolic(val, \
607 nvme_opcode_name(nvme_cmd_flush), \
608 nvme_opcode_name(nvme_cmd_write), \
609 nvme_opcode_name(nvme_cmd_read), \
610 nvme_opcode_name(nvme_cmd_write_uncor), \
611 nvme_opcode_name(nvme_cmd_compare), \
612 nvme_opcode_name(nvme_cmd_write_zeroes), \
613 nvme_opcode_name(nvme_cmd_dsm), \
614 nvme_opcode_name(nvme_cmd_resv_register), \
615 nvme_opcode_name(nvme_cmd_resv_report), \
616 nvme_opcode_name(nvme_cmd_resv_acquire), \
617 nvme_opcode_name(nvme_cmd_resv_release))
621 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
623 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
624 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
625 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
626 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
630 NVME_SGL_FMT_ADDRESS = 0x00,
631 NVME_SGL_FMT_OFFSET = 0x01,
632 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
633 NVME_SGL_FMT_INVALIDATE = 0x0f,
637 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
639 * For struct nvme_sgl_desc:
640 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
641 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
642 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
644 * For struct nvme_keyed_sgl_desc:
645 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
647 * Transport-specific SGL types:
648 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
651 NVME_SGL_FMT_DATA_DESC = 0x00,
652 NVME_SGL_FMT_SEG_DESC = 0x02,
653 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
654 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
655 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
658 struct nvme_sgl_desc {
665 struct nvme_keyed_sgl_desc {
672 union nvme_data_ptr {
677 struct nvme_sgl_desc sgl;
678 struct nvme_keyed_sgl_desc ksgl;
682 * Lowest two bits of our flags field (FUSE field in the spec):
684 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
685 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
687 * Highest two bits in our flags field (PSDT field in the spec):
689 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
690 * If used, MPTR contains addr of single physical buffer (byte aligned).
691 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
692 * If used, MPTR contains an address of an SGL segment containing
693 * exactly 1 SGL descriptor (qword aligned).
696 NVME_CMD_FUSE_FIRST = (1 << 0),
697 NVME_CMD_FUSE_SECOND = (1 << 1),
699 NVME_CMD_SGL_METABUF = (1 << 6),
700 NVME_CMD_SGL_METASEG = (1 << 7),
701 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
704 struct nvme_common_command {
711 union nvme_data_ptr dptr;
720 struct nvme_rw_command {
727 union nvme_data_ptr dptr;
738 NVME_RW_LR = 1 << 15,
739 NVME_RW_FUA = 1 << 14,
740 NVME_RW_DSM_FREQ_UNSPEC = 0,
741 NVME_RW_DSM_FREQ_TYPICAL = 1,
742 NVME_RW_DSM_FREQ_RARE = 2,
743 NVME_RW_DSM_FREQ_READS = 3,
744 NVME_RW_DSM_FREQ_WRITES = 4,
745 NVME_RW_DSM_FREQ_RW = 5,
746 NVME_RW_DSM_FREQ_ONCE = 6,
747 NVME_RW_DSM_FREQ_PREFETCH = 7,
748 NVME_RW_DSM_FREQ_TEMP = 8,
749 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
750 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
751 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
752 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
753 NVME_RW_DSM_SEQ_REQ = 1 << 6,
754 NVME_RW_DSM_COMPRESSED = 1 << 7,
755 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
756 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
757 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
758 NVME_RW_PRINFO_PRACT = 1 << 13,
759 NVME_RW_DTYPE_STREAMS = 1 << 4,
762 struct nvme_dsm_cmd {
768 union nvme_data_ptr dptr;
775 NVME_DSMGMT_IDR = 1 << 0,
776 NVME_DSMGMT_IDW = 1 << 1,
777 NVME_DSMGMT_AD = 1 << 2,
780 #define NVME_DSM_MAX_RANGES 256
782 struct nvme_dsm_range {
788 struct nvme_write_zeroes_cmd {
795 union nvme_data_ptr dptr;
808 NVME_TEMP_THRESH_MASK = 0xffff,
809 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
810 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
813 struct nvme_feat_auto_pst {
818 NVME_HOST_MEM_ENABLE = (1 << 0),
819 NVME_HOST_MEM_RETURN = (1 << 1),
822 struct nvme_feat_host_behavior {
828 NVME_ENABLE_ACRE = 1,
833 enum nvme_admin_opcode {
834 nvme_admin_delete_sq = 0x00,
835 nvme_admin_create_sq = 0x01,
836 nvme_admin_get_log_page = 0x02,
837 nvme_admin_delete_cq = 0x04,
838 nvme_admin_create_cq = 0x05,
839 nvme_admin_identify = 0x06,
840 nvme_admin_abort_cmd = 0x08,
841 nvme_admin_set_features = 0x09,
842 nvme_admin_get_features = 0x0a,
843 nvme_admin_async_event = 0x0c,
844 nvme_admin_ns_mgmt = 0x0d,
845 nvme_admin_activate_fw = 0x10,
846 nvme_admin_download_fw = 0x11,
847 nvme_admin_dev_self_test = 0x14,
848 nvme_admin_ns_attach = 0x15,
849 nvme_admin_keep_alive = 0x18,
850 nvme_admin_directive_send = 0x19,
851 nvme_admin_directive_recv = 0x1a,
852 nvme_admin_virtual_mgmt = 0x1c,
853 nvme_admin_nvme_mi_send = 0x1d,
854 nvme_admin_nvme_mi_recv = 0x1e,
855 nvme_admin_dbbuf = 0x7C,
856 nvme_admin_format_nvm = 0x80,
857 nvme_admin_security_send = 0x81,
858 nvme_admin_security_recv = 0x82,
859 nvme_admin_sanitize_nvm = 0x84,
860 nvme_admin_get_lba_status = 0x86,
863 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
864 #define show_admin_opcode_name(val) \
865 __print_symbolic(val, \
866 nvme_admin_opcode_name(nvme_admin_delete_sq), \
867 nvme_admin_opcode_name(nvme_admin_create_sq), \
868 nvme_admin_opcode_name(nvme_admin_get_log_page), \
869 nvme_admin_opcode_name(nvme_admin_delete_cq), \
870 nvme_admin_opcode_name(nvme_admin_create_cq), \
871 nvme_admin_opcode_name(nvme_admin_identify), \
872 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
873 nvme_admin_opcode_name(nvme_admin_set_features), \
874 nvme_admin_opcode_name(nvme_admin_get_features), \
875 nvme_admin_opcode_name(nvme_admin_async_event), \
876 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
877 nvme_admin_opcode_name(nvme_admin_activate_fw), \
878 nvme_admin_opcode_name(nvme_admin_download_fw), \
879 nvme_admin_opcode_name(nvme_admin_ns_attach), \
880 nvme_admin_opcode_name(nvme_admin_keep_alive), \
881 nvme_admin_opcode_name(nvme_admin_directive_send), \
882 nvme_admin_opcode_name(nvme_admin_directive_recv), \
883 nvme_admin_opcode_name(nvme_admin_dbbuf), \
884 nvme_admin_opcode_name(nvme_admin_format_nvm), \
885 nvme_admin_opcode_name(nvme_admin_security_send), \
886 nvme_admin_opcode_name(nvme_admin_security_recv), \
887 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
888 nvme_admin_opcode_name(nvme_admin_get_lba_status))
891 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
892 NVME_CQ_IRQ_ENABLED = (1 << 1),
893 NVME_SQ_PRIO_URGENT = (0 << 1),
894 NVME_SQ_PRIO_HIGH = (1 << 1),
895 NVME_SQ_PRIO_MEDIUM = (2 << 1),
896 NVME_SQ_PRIO_LOW = (3 << 1),
897 NVME_FEAT_ARBITRATION = 0x01,
898 NVME_FEAT_POWER_MGMT = 0x02,
899 NVME_FEAT_LBA_RANGE = 0x03,
900 NVME_FEAT_TEMP_THRESH = 0x04,
901 NVME_FEAT_ERR_RECOVERY = 0x05,
902 NVME_FEAT_VOLATILE_WC = 0x06,
903 NVME_FEAT_NUM_QUEUES = 0x07,
904 NVME_FEAT_IRQ_COALESCE = 0x08,
905 NVME_FEAT_IRQ_CONFIG = 0x09,
906 NVME_FEAT_WRITE_ATOMIC = 0x0a,
907 NVME_FEAT_ASYNC_EVENT = 0x0b,
908 NVME_FEAT_AUTO_PST = 0x0c,
909 NVME_FEAT_HOST_MEM_BUF = 0x0d,
910 NVME_FEAT_TIMESTAMP = 0x0e,
911 NVME_FEAT_KATO = 0x0f,
912 NVME_FEAT_HCTM = 0x10,
913 NVME_FEAT_NOPSC = 0x11,
914 NVME_FEAT_RRL = 0x12,
915 NVME_FEAT_PLM_CONFIG = 0x13,
916 NVME_FEAT_PLM_WINDOW = 0x14,
917 NVME_FEAT_HOST_BEHAVIOR = 0x16,
918 NVME_FEAT_SANITIZE = 0x17,
919 NVME_FEAT_SW_PROGRESS = 0x80,
920 NVME_FEAT_HOST_ID = 0x81,
921 NVME_FEAT_RESV_MASK = 0x82,
922 NVME_FEAT_RESV_PERSIST = 0x83,
923 NVME_FEAT_WRITE_PROTECT = 0x84,
924 NVME_LOG_ERROR = 0x01,
925 NVME_LOG_SMART = 0x02,
926 NVME_LOG_FW_SLOT = 0x03,
927 NVME_LOG_CHANGED_NS = 0x04,
928 NVME_LOG_CMD_EFFECTS = 0x05,
929 NVME_LOG_DEVICE_SELF_TEST = 0x06,
930 NVME_LOG_TELEMETRY_HOST = 0x07,
931 NVME_LOG_TELEMETRY_CTRL = 0x08,
932 NVME_LOG_ENDURANCE_GROUP = 0x09,
934 NVME_LOG_DISC = 0x70,
935 NVME_LOG_RESERVATION = 0x80,
936 NVME_FWACT_REPL = (0 << 3),
937 NVME_FWACT_REPL_ACTV = (1 << 3),
938 NVME_FWACT_ACTV = (2 << 3),
941 /* NVMe Namespace Write Protect State */
943 NVME_NS_NO_WRITE_PROTECT = 0,
944 NVME_NS_WRITE_PROTECT,
945 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
946 NVME_NS_WRITE_PROTECT_PERMANENT,
949 #define NVME_MAX_CHANGED_NAMESPACES 1024
951 struct nvme_identify {
957 union nvme_data_ptr dptr;
964 #define NVME_IDENTIFY_DATA_SIZE 4096
966 struct nvme_features {
972 union nvme_data_ptr dptr;
981 struct nvme_host_mem_buf_desc {
987 struct nvme_create_cq {
1001 struct nvme_create_sq {
1015 struct nvme_delete_queue {
1025 struct nvme_abort_cmd {
1035 struct nvme_download_firmware {
1040 union nvme_data_ptr dptr;
1046 struct nvme_format_cmd {
1056 struct nvme_get_log_page_command {
1062 union nvme_data_ptr dptr;
1064 __u8 lsp; /* upper 4 bits reserved */
1078 struct nvme_directive_cmd {
1084 union nvme_data_ptr dptr;
1097 * Fabrics subcommands.
1099 enum nvmf_fabrics_opcode {
1100 nvme_fabrics_command = 0x7f,
1103 enum nvmf_capsule_command {
1104 nvme_fabrics_type_property_set = 0x00,
1105 nvme_fabrics_type_connect = 0x01,
1106 nvme_fabrics_type_property_get = 0x04,
1109 #define nvme_fabrics_type_name(type) { type, #type }
1110 #define show_fabrics_type_name(type) \
1111 __print_symbolic(type, \
1112 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1113 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1114 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1117 * If not fabrics command, fctype will be ignored.
1119 #define show_opcode_name(qid, opcode, fctype) \
1120 ((opcode) == nvme_fabrics_command ? \
1121 show_fabrics_type_name(fctype) : \
1123 show_nvm_opcode_name(opcode) : \
1124 show_admin_opcode_name(opcode)))
1126 struct nvmf_common_command {
1136 * The legal cntlid range a NVMe Target will provide.
1137 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1138 * Devices based on earlier specs did not have the subsystem concept;
1139 * therefore, those devices had their cntlid value set to 0 as a result.
1141 #define NVME_CNTLID_MIN 1
1142 #define NVME_CNTLID_MAX 0xffef
1143 #define NVME_CNTLID_DYNAMIC 0xffff
1145 #define MAX_DISC_LOGS 255
1147 /* Discovery log page entry */
1148 struct nvmf_disc_rsp_page_entry {
1157 char trsvcid[NVMF_TRSVCID_SIZE];
1159 char subnqn[NVMF_NQN_FIELD_LEN];
1160 char traddr[NVMF_TRADDR_SIZE];
1162 char common[NVMF_TSAS_SIZE];
1174 /* Discovery log page header */
1175 struct nvmf_disc_rsp_page_hdr {
1180 struct nvmf_disc_rsp_page_entry entries[0];
1184 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1187 struct nvmf_connect_command {
1193 union nvme_data_ptr dptr;
1203 struct nvmf_connect_data {
1207 char subsysnqn[NVMF_NQN_FIELD_LEN];
1208 char hostnqn[NVMF_NQN_FIELD_LEN];
1212 struct nvmf_property_set_command {
1225 struct nvmf_property_get_command {
1247 struct streams_directive_params {
1259 struct nvme_command {
1261 struct nvme_common_command common;
1262 struct nvme_rw_command rw;
1263 struct nvme_identify identify;
1264 struct nvme_features features;
1265 struct nvme_create_cq create_cq;
1266 struct nvme_create_sq create_sq;
1267 struct nvme_delete_queue delete_queue;
1268 struct nvme_download_firmware dlfw;
1269 struct nvme_format_cmd format;
1270 struct nvme_dsm_cmd dsm;
1271 struct nvme_write_zeroes_cmd write_zeroes;
1272 struct nvme_abort_cmd abort;
1273 struct nvme_get_log_page_command get_log_page;
1274 struct nvmf_common_command fabrics;
1275 struct nvmf_connect_command connect;
1276 struct nvmf_property_set_command prop_set;
1277 struct nvmf_property_get_command prop_get;
1278 struct nvme_dbbuf dbbuf;
1279 struct nvme_directive_cmd directive;
1283 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1285 return cmd->common.opcode == nvme_fabrics_command;
1288 struct nvme_error_slot {
1292 __le16 status_field;
1293 __le16 param_error_location;
1302 static inline bool nvme_is_write(struct nvme_command *cmd)
1307 * Why can't we simply have a Fabrics In and Fabrics out command?
1309 if (unlikely(nvme_is_fabrics(cmd)))
1310 return cmd->fabrics.fctype & 1;
1311 return cmd->common.opcode & 1;
1316 * Generic Command Status:
1318 NVME_SC_SUCCESS = 0x0,
1319 NVME_SC_INVALID_OPCODE = 0x1,
1320 NVME_SC_INVALID_FIELD = 0x2,
1321 NVME_SC_CMDID_CONFLICT = 0x3,
1322 NVME_SC_DATA_XFER_ERROR = 0x4,
1323 NVME_SC_POWER_LOSS = 0x5,
1324 NVME_SC_INTERNAL = 0x6,
1325 NVME_SC_ABORT_REQ = 0x7,
1326 NVME_SC_ABORT_QUEUE = 0x8,
1327 NVME_SC_FUSED_FAIL = 0x9,
1328 NVME_SC_FUSED_MISSING = 0xa,
1329 NVME_SC_INVALID_NS = 0xb,
1330 NVME_SC_CMD_SEQ_ERROR = 0xc,
1331 NVME_SC_SGL_INVALID_LAST = 0xd,
1332 NVME_SC_SGL_INVALID_COUNT = 0xe,
1333 NVME_SC_SGL_INVALID_DATA = 0xf,
1334 NVME_SC_SGL_INVALID_METADATA = 0x10,
1335 NVME_SC_SGL_INVALID_TYPE = 0x11,
1337 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1338 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1340 NVME_SC_SANITIZE_FAILED = 0x1C,
1341 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1343 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1344 NVME_SC_CMD_INTERRUPTED = 0x21,
1346 NVME_SC_LBA_RANGE = 0x80,
1347 NVME_SC_CAP_EXCEEDED = 0x81,
1348 NVME_SC_NS_NOT_READY = 0x82,
1349 NVME_SC_RESERVATION_CONFLICT = 0x83,
1352 * Command Specific Status:
1354 NVME_SC_CQ_INVALID = 0x100,
1355 NVME_SC_QID_INVALID = 0x101,
1356 NVME_SC_QUEUE_SIZE = 0x102,
1357 NVME_SC_ABORT_LIMIT = 0x103,
1358 NVME_SC_ABORT_MISSING = 0x104,
1359 NVME_SC_ASYNC_LIMIT = 0x105,
1360 NVME_SC_FIRMWARE_SLOT = 0x106,
1361 NVME_SC_FIRMWARE_IMAGE = 0x107,
1362 NVME_SC_INVALID_VECTOR = 0x108,
1363 NVME_SC_INVALID_LOG_PAGE = 0x109,
1364 NVME_SC_INVALID_FORMAT = 0x10a,
1365 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1366 NVME_SC_INVALID_QUEUE = 0x10c,
1367 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1368 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1369 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1370 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1371 NVME_SC_FW_NEEDS_RESET = 0x111,
1372 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1373 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1374 NVME_SC_OVERLAPPING_RANGE = 0x114,
1375 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1376 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1377 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1378 NVME_SC_NS_IS_PRIVATE = 0x119,
1379 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1380 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1381 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1382 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1383 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1386 * I/O Command Set Specific - NVM commands:
1388 NVME_SC_BAD_ATTRIBUTES = 0x180,
1389 NVME_SC_INVALID_PI = 0x181,
1390 NVME_SC_READ_ONLY = 0x182,
1391 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1394 * I/O Command Set Specific - Fabrics commands:
1396 NVME_SC_CONNECT_FORMAT = 0x180,
1397 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1398 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1399 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1400 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1402 NVME_SC_DISCOVERY_RESTART = 0x190,
1403 NVME_SC_AUTH_REQUIRED = 0x191,
1406 * Media and Data Integrity Errors:
1408 NVME_SC_WRITE_FAULT = 0x280,
1409 NVME_SC_READ_ERROR = 0x281,
1410 NVME_SC_GUARD_CHECK = 0x282,
1411 NVME_SC_APPTAG_CHECK = 0x283,
1412 NVME_SC_REFTAG_CHECK = 0x284,
1413 NVME_SC_COMPARE_FAILED = 0x285,
1414 NVME_SC_ACCESS_DENIED = 0x286,
1415 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1418 * Path-related Errors:
1420 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1421 NVME_SC_ANA_INACCESSIBLE = 0x302,
1422 NVME_SC_ANA_TRANSITION = 0x303,
1423 NVME_SC_HOST_PATH_ERROR = 0x370,
1424 NVME_SC_HOST_ABORTED_CMD = 0x371,
1426 NVME_SC_CRD = 0x1800,
1427 NVME_SC_DNR = 0x4000,
1430 struct nvme_completion {
1432 * Used by Admin and Fabrics commands to return data:
1439 __le16 sq_head; /* how much of this queue may be reclaimed */
1440 __le16 sq_id; /* submission queue that generated this entry */
1441 __u16 command_id; /* of the command which completed */
1442 __le16 status; /* did the command fail, and if so, why? */
1445 #define NVME_VS(major, minor, tertiary) \
1446 (((major) << 16) | ((minor) << 8) | (tertiary))
1448 #define NVME_MAJOR(ver) ((ver) >> 16)
1449 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1450 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1452 #endif /* _LINUX_NVME_H */