include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _LINUX_NVME_H
  16 #define _LINUX_NVME_H
  17
  18 #include <linux/types.h>
  19 #include <linux/uuid.h>
  20
  21 /* NQN names in commands fields specified one size */
  22 #define NVMF_NQN_FIELD_LEN      256
  23
  24 /* However the max length of a qualified name is another size */
  25 #define NVMF_NQN_SIZE           223
  26
  27 #define NVMF_TRSVCID_SIZE       32
  28 #define NVMF_TRADDR_SIZE        256
  29 #define NVMF_TSAS_SIZE          256
  30
  31 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  32
  33 #define NVME_RDMA_IP_PORT       4420
  34
  35 #define NVME_NSID_ALL           0xffffffff
  36
  37 enum nvme_subsys_type {
  38         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  39         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  40 };
  41
  42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  43 enum {
  44         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  45         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  46         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  47         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  48         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  49 };
  50
  51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  52 enum {
  53         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  54         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  55         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  56         NVMF_TRTYPE_MAX,
  57 };
  58
  59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  60 enum {
  61         NVMF_TREQ_NOT_SPECIFIED = 0,    /* Not specified */
  62         NVMF_TREQ_REQUIRED      = 1,    /* Required */
  63         NVMF_TREQ_NOT_REQUIRED  = 2,    /* Not Required */
  64 };
  65
  66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  67  * RDMA_QPTYPE field
  68  */
  69 enum {
  70         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  71         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  72 };
  73
  74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  75  * RDMA_QPTYPE field
  76  */
  77 enum {
  78         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  79         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  80         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  81         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  82         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  83 };
  84
  85 /* RDMA Connection Management Service Type codes for Discovery Log Page
  86  * entry TSAS RDMA_CMS field
  87  */
  88 enum {
  89         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  90 };
  91
  92 #define NVME_AQ_DEPTH           32
  93
  94 enum {
  95         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
  96         NVME_REG_VS     = 0x0008,       /* Version */
  97         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
  98         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
  99         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 100         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 101         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 102         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 103         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 104         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 105         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 106         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 107         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 108 };
 109
 110 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 111 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 112 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 113 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 114 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 115 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 116
 117 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 118 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 119 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
 120 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
 121
 122 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
 123 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
 124 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
 125 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
 126 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
 127
 128 /*
 129  * Submission and Completion Queue Entry Sizes for the NVM command set.
 130  * (In bytes and specified as a power of two (2^n)).
 131  */
 132 #define NVME_NVM_IOSQES         6
 133 #define NVME_NVM_IOCQES         4
 134
 135 enum {
 136         NVME_CC_ENABLE          = 1 << 0,
 137         NVME_CC_CSS_NVM         = 0 << 4,
 138         NVME_CC_EN_SHIFT        = 0,
 139         NVME_CC_CSS_SHIFT       = 4,
 140         NVME_CC_MPS_SHIFT       = 7,
 141         NVME_CC_AMS_SHIFT       = 11,
 142         NVME_CC_SHN_SHIFT       = 14,
 143         NVME_CC_IOSQES_SHIFT    = 16,
 144         NVME_CC_IOCQES_SHIFT    = 20,
 145         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 146         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 147         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 148         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 149         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 150         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 151         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 152         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 153         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 154         NVME_CSTS_RDY           = 1 << 0,
 155         NVME_CSTS_CFS           = 1 << 1,
 156         NVME_CSTS_NSSRO         = 1 << 4,
 157         NVME_CSTS_PP            = 1 << 5,
 158         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 159         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 160         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 161         NVME_CSTS_SHST_MASK     = 3 << 2,
 162 };
 163
 164 struct nvme_id_power_state {
 165         __le16                  max_power;      /* centiwatts */
 166         __u8                    rsvd2;
 167         __u8                    flags;
 168         __le32                  entry_lat;      /* microseconds */
 169         __le32                  exit_lat;       /* microseconds */
 170         __u8                    read_tput;
 171         __u8                    read_lat;
 172         __u8                    write_tput;
 173         __u8                    write_lat;
 174         __le16                  idle_power;
 175         __u8                    idle_scale;
 176         __u8                    rsvd19;
 177         __le16                  active_power;
 178         __u8                    active_work_scale;
 179         __u8                    rsvd23[9];
 180 };
 181
 182 enum {
 183         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 184         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 185 };
 186
 187 struct nvme_id_ctrl {
 188         __le16                  vid;
 189         __le16                  ssvid;
 190         char                    sn[20];
 191         char                    mn[40];
 192         char                    fr[8];
 193         __u8                    rab;
 194         __u8                    ieee[3];
 195         __u8                    cmic;
 196         __u8                    mdts;
 197         __le16                  cntlid;
 198         __le32                  ver;
 199         __le32                  rtd3r;
 200         __le32                  rtd3e;
 201         __le32                  oaes;
 202         __le32                  ctratt;
 203         __u8                    rsvd100[156];
 204         __le16                  oacs;
 205         __u8                    acl;
 206         __u8                    aerl;
 207         __u8                    frmw;
 208         __u8                    lpa;
 209         __u8                    elpe;
 210         __u8                    npss;
 211         __u8                    avscc;
 212         __u8                    apsta;
 213         __le16                  wctemp;
 214         __le16                  cctemp;
 215         __le16                  mtfa;
 216         __le32                  hmpre;
 217         __le32                  hmmin;
 218         __u8                    tnvmcap[16];
 219         __u8                    unvmcap[16];
 220         __le32                  rpmbs;
 221         __le16                  edstt;
 222         __u8                    dsto;
 223         __u8                    fwug;
 224         __le16                  kas;
 225         __le16                  hctma;
 226         __le16                  mntmt;
 227         __le16                  mxtmt;
 228         __le32                  sanicap;
 229         __u8                    rsvd332[180];
 230         __u8                    sqes;
 231         __u8                    cqes;
 232         __le16                  maxcmd;
 233         __le32                  nn;
 234         __le16                  oncs;
 235         __le16                  fuses;
 236         __u8                    fna;
 237         __u8                    vwc;
 238         __le16                  awun;
 239         __le16                  awupf;
 240         __u8                    nvscc;
 241         __u8                    rsvd531;
 242         __le16                  acwu;
 243         __u8                    rsvd534[2];
 244         __le32                  sgls;
 245         __u8                    rsvd540[228];
 246         char                    subnqn[256];
 247         __u8                    rsvd1024[768];
 248         __le32                  ioccsz;
 249         __le32                  iorcsz;
 250         __le16                  icdoff;
 251         __u8                    ctrattr;
 252         __u8                    msdbd;
 253         __u8                    rsvd1804[244];
 254         struct nvme_id_power_state      psd[32];
 255         __u8                    vs[1024];
 256 };
 257
 258 enum {
 259         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 260         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 261         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 262         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 263         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 264         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 265         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 266         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 267         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 268 };
 269
 270 struct nvme_lbaf {
 271         __le16                  ms;
 272         __u8                    ds;
 273         __u8                    rp;
 274 };
 275
 276 struct nvme_id_ns {
 277         __le64                  nsze;
 278         __le64                  ncap;
 279         __le64                  nuse;
 280         __u8                    nsfeat;
 281         __u8                    nlbaf;
 282         __u8                    flbas;
 283         __u8                    mc;
 284         __u8                    dpc;
 285         __u8                    dps;
 286         __u8                    nmic;
 287         __u8                    rescap;
 288         __u8                    fpi;
 289         __u8                    rsvd33;
 290         __le16                  nawun;
 291         __le16                  nawupf;
 292         __le16                  nacwu;
 293         __le16                  nabsn;
 294         __le16                  nabo;
 295         __le16                  nabspf;
 296         __le16                  noiob;
 297         __u8                    nvmcap[16];
 298         __u8                    rsvd64[40];
 299         __u8                    nguid[16];
 300         __u8                    eui64[8];
 301         struct nvme_lbaf        lbaf[16];
 302         __u8                    rsvd192[192];
 303         __u8                    vs[3712];
 304 };
 305
 306 enum {
 307         NVME_ID_CNS_NS                  = 0x00,
 308         NVME_ID_CNS_CTRL                = 0x01,
 309         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 310         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 311         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 312         NVME_ID_CNS_NS_PRESENT          = 0x11,
 313         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 314         NVME_ID_CNS_CTRL_LIST           = 0x13,
 315 };
 316
 317 enum {
 318         NVME_DIR_IDENTIFY               = 0x00,
 319         NVME_DIR_STREAMS                = 0x01,
 320         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 321         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 322         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 323         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 324         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 325         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 326         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 327         NVME_DIR_ENDIR                  = 0x01,
 328 };
 329
 330 enum {
 331         NVME_NS_FEAT_THIN       = 1 << 0,
 332         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 333         NVME_NS_FLBAS_META_EXT  = 0x10,
 334         NVME_LBAF_RP_BEST       = 0,
 335         NVME_LBAF_RP_BETTER     = 1,
 336         NVME_LBAF_RP_GOOD       = 2,
 337         NVME_LBAF_RP_DEGRADED   = 3,
 338         NVME_NS_DPC_PI_LAST     = 1 << 4,
 339         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 340         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 341         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 342         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 343         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 344         NVME_NS_DPS_PI_MASK     = 0x7,
 345         NVME_NS_DPS_PI_TYPE1    = 1,
 346         NVME_NS_DPS_PI_TYPE2    = 2,
 347         NVME_NS_DPS_PI_TYPE3    = 3,
 348 };
 349
 350 struct nvme_ns_id_desc {
 351         __u8 nidt;
 352         __u8 nidl;
 353         __le16 reserved;
 354 };
 355
 356 #define NVME_NIDT_EUI64_LEN     8
 357 #define NVME_NIDT_NGUID_LEN     16
 358 #define NVME_NIDT_UUID_LEN      16
 359
 360 enum {
 361         NVME_NIDT_EUI64         = 0x01,
 362         NVME_NIDT_NGUID         = 0x02,
 363         NVME_NIDT_UUID          = 0x03,
 364 };
 365
 366 struct nvme_smart_log {
 367         __u8                    critical_warning;
 368         __u8                    temperature[2];
 369         __u8                    avail_spare;
 370         __u8                    spare_thresh;
 371         __u8                    percent_used;
 372         __u8                    rsvd6[26];
 373         __u8                    data_units_read[16];
 374         __u8                    data_units_written[16];
 375         __u8                    host_reads[16];
 376         __u8                    host_writes[16];
 377         __u8                    ctrl_busy_time[16];
 378         __u8                    power_cycles[16];
 379         __u8                    power_on_hours[16];
 380         __u8                    unsafe_shutdowns[16];
 381         __u8                    media_errors[16];
 382         __u8                    num_err_log_entries[16];
 383         __le32                  warning_temp_time;
 384         __le32                  critical_comp_time;
 385         __le16                  temp_sensor[8];
 386         __u8                    rsvd216[296];
 387 };
 388
 389 struct nvme_fw_slot_info_log {
 390         __u8                    afi;
 391         __u8                    rsvd1[7];
 392         __le64                  frs[7];
 393         __u8                    rsvd64[448];
 394 };
 395
 396 enum {
 397         NVME_SMART_CRIT_SPARE           = 1 << 0,
 398         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 399         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 400         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 401         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 402 };
 403
 404 enum {
 405         NVME_AER_NOTICE_NS_CHANGED      = 0x0002,
 406         NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
 407 };
 408
 409 struct nvme_lba_range_type {
 410         __u8                    type;
 411         __u8                    attributes;
 412         __u8                    rsvd2[14];
 413         __u64                   slba;
 414         __u64                   nlb;
 415         __u8                    guid[16];
 416         __u8                    rsvd48[16];
 417 };
 418
 419 enum {
 420         NVME_LBART_TYPE_FS      = 0x01,
 421         NVME_LBART_TYPE_RAID    = 0x02,
 422         NVME_LBART_TYPE_CACHE   = 0x03,
 423         NVME_LBART_TYPE_SWAP    = 0x04,
 424
 425         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 426         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 427 };
 428
 429 struct nvme_reservation_status {
 430         __le32  gen;
 431         __u8    rtype;
 432         __u8    regctl[2];
 433         __u8    resv5[2];
 434         __u8    ptpls;
 435         __u8    resv10[13];
 436         struct {
 437                 __le16  cntlid;
 438                 __u8    rcsts;
 439                 __u8    resv3[5];
 440                 __le64  hostid;
 441                 __le64  rkey;
 442         } regctl_ds[];
 443 };
 444
 445 enum nvme_async_event_type {
 446         NVME_AER_TYPE_ERROR     = 0,
 447         NVME_AER_TYPE_SMART     = 1,
 448         NVME_AER_TYPE_NOTICE    = 2,
 449 };
 450
 451 /* I/O commands */
 452
 453 enum nvme_opcode {
 454         nvme_cmd_flush          = 0x00,
 455         nvme_cmd_write          = 0x01,
 456         nvme_cmd_read           = 0x02,
 457         nvme_cmd_write_uncor    = 0x04,
 458         nvme_cmd_compare        = 0x05,
 459         nvme_cmd_write_zeroes   = 0x08,
 460         nvme_cmd_dsm            = 0x09,
 461         nvme_cmd_resv_register  = 0x0d,
 462         nvme_cmd_resv_report    = 0x0e,
 463         nvme_cmd_resv_acquire   = 0x11,
 464         nvme_cmd_resv_release   = 0x15,
 465 };
 466
 467 /*
 468  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 469  *
 470  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 471  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 472  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 473  *                            request subtype
 474  */
 475 enum {
 476         NVME_SGL_FMT_ADDRESS            = 0x00,
 477         NVME_SGL_FMT_OFFSET             = 0x01,
 478         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 479 };
 480
 481 /*
 482  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 483  *
 484  * For struct nvme_sgl_desc:
 485  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 486  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 487  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 488  *
 489  * For struct nvme_keyed_sgl_desc:
 490  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 491  */
 492 enum {
 493         NVME_SGL_FMT_DATA_DESC          = 0x00,
 494         NVME_SGL_FMT_SEG_DESC           = 0x02,
 495         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 496         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 497 };
 498
 499 struct nvme_sgl_desc {
 500         __le64  addr;
 501         __le32  length;
 502         __u8    rsvd[3];
 503         __u8    type;
 504 };
 505
 506 struct nvme_keyed_sgl_desc {
 507         __le64  addr;
 508         __u8    length[3];
 509         __u8    key[4];
 510         __u8    type;
 511 };
 512
 513 union nvme_data_ptr {
 514         struct {
 515                 __le64  prp1;
 516                 __le64  prp2;
 517         };
 518         struct nvme_sgl_desc    sgl;
 519         struct nvme_keyed_sgl_desc ksgl;
 520 };
 521
 522 /*
 523  * Lowest two bits of our flags field (FUSE field in the spec):
 524  *
 525  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 526  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 527  *
 528  * Highest two bits in our flags field (PSDT field in the spec):
 529  *
 530  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 531  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 532  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 533  *      If used, MPTR contains an address of an SGL segment containing
 534  *      exactly 1 SGL descriptor (qword aligned).
 535  */
 536 enum {
 537         NVME_CMD_FUSE_FIRST     = (1 << 0),
 538         NVME_CMD_FUSE_SECOND    = (1 << 1),
 539
 540         NVME_CMD_SGL_METABUF    = (1 << 6),
 541         NVME_CMD_SGL_METASEG    = (1 << 7),
 542         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 543 };
 544
 545 struct nvme_common_command {
 546         __u8                    opcode;
 547         __u8                    flags;
 548         __u16                   command_id;
 549         __le32                  nsid;
 550         __le32                  cdw2[2];
 551         __le64                  metadata;
 552         union nvme_data_ptr     dptr;
 553         __le32                  cdw10[6];
 554 };
 555
 556 struct nvme_rw_command {
 557         __u8                    opcode;
 558         __u8                    flags;
 559         __u16                   command_id;
 560         __le32                  nsid;
 561         __u64                   rsvd2;
 562         __le64                  metadata;
 563         union nvme_data_ptr     dptr;
 564         __le64                  slba;
 565         __le16                  length;
 566         __le16                  control;
 567         __le32                  dsmgmt;
 568         __le32                  reftag;
 569         __le16                  apptag;
 570         __le16                  appmask;
 571 };
 572
 573 enum {
 574         NVME_RW_LR                      = 1 << 15,
 575         NVME_RW_FUA                     = 1 << 14,
 576         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 577         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 578         NVME_RW_DSM_FREQ_RARE           = 2,
 579         NVME_RW_DSM_FREQ_READS          = 3,
 580         NVME_RW_DSM_FREQ_WRITES         = 4,
 581         NVME_RW_DSM_FREQ_RW             = 5,
 582         NVME_RW_DSM_FREQ_ONCE           = 6,
 583         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 584         NVME_RW_DSM_FREQ_TEMP           = 8,
 585         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 586         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 587         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 588         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 589         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 590         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 591         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 592         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 593         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 594         NVME_RW_PRINFO_PRACT            = 1 << 13,
 595         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 596 };
 597
 598 struct nvme_dsm_cmd {
 599         __u8                    opcode;
 600         __u8                    flags;
 601         __u16                   command_id;
 602         __le32                  nsid;
 603         __u64                   rsvd2[2];
 604         union nvme_data_ptr     dptr;
 605         __le32                  nr;
 606         __le32                  attributes;
 607         __u32                   rsvd12[4];
 608 };
 609
 610 enum {
 611         NVME_DSMGMT_IDR         = 1 << 0,
 612         NVME_DSMGMT_IDW         = 1 << 1,
 613         NVME_DSMGMT_AD          = 1 << 2,
 614 };
 615
 616 #define NVME_DSM_MAX_RANGES     256
 617
 618 struct nvme_dsm_range {
 619         __le32                  cattr;
 620         __le32                  nlb;
 621         __le64                  slba;
 622 };
 623
 624 struct nvme_write_zeroes_cmd {
 625         __u8                    opcode;
 626         __u8                    flags;
 627         __u16                   command_id;
 628         __le32                  nsid;
 629         __u64                   rsvd2;
 630         __le64                  metadata;
 631         union nvme_data_ptr     dptr;
 632         __le64                  slba;
 633         __le16                  length;
 634         __le16                  control;
 635         __le32                  dsmgmt;
 636         __le32                  reftag;
 637         __le16                  apptag;
 638         __le16                  appmask;
 639 };
 640
 641 /* Features */
 642
 643 struct nvme_feat_auto_pst {
 644         __le64 entries[32];
 645 };
 646
 647 enum {
 648         NVME_HOST_MEM_ENABLE    = (1 << 0),
 649         NVME_HOST_MEM_RETURN    = (1 << 1),
 650 };
 651
 652 /* Admin commands */
 653
 654 enum nvme_admin_opcode {
 655         nvme_admin_delete_sq            = 0x00,
 656         nvme_admin_create_sq            = 0x01,
 657         nvme_admin_get_log_page         = 0x02,
 658         nvme_admin_delete_cq            = 0x04,
 659         nvme_admin_create_cq            = 0x05,
 660         nvme_admin_identify             = 0x06,
 661         nvme_admin_abort_cmd            = 0x08,
 662         nvme_admin_set_features         = 0x09,
 663         nvme_admin_get_features         = 0x0a,
 664         nvme_admin_async_event          = 0x0c,
 665         nvme_admin_ns_mgmt              = 0x0d,
 666         nvme_admin_activate_fw          = 0x10,
 667         nvme_admin_download_fw          = 0x11,
 668         nvme_admin_ns_attach            = 0x15,
 669         nvme_admin_keep_alive           = 0x18,
 670         nvme_admin_directive_send       = 0x19,
 671         nvme_admin_directive_recv       = 0x1a,
 672         nvme_admin_dbbuf                = 0x7C,
 673         nvme_admin_format_nvm           = 0x80,
 674         nvme_admin_security_send        = 0x81,
 675         nvme_admin_security_recv        = 0x82,
 676 };
 677
 678 enum {
 679         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 680         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 681         NVME_SQ_PRIO_URGENT     = (0 << 1),
 682         NVME_SQ_PRIO_HIGH       = (1 << 1),
 683         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 684         NVME_SQ_PRIO_LOW        = (3 << 1),
 685         NVME_FEAT_ARBITRATION   = 0x01,
 686         NVME_FEAT_POWER_MGMT    = 0x02,
 687         NVME_FEAT_LBA_RANGE     = 0x03,
 688         NVME_FEAT_TEMP_THRESH   = 0x04,
 689         NVME_FEAT_ERR_RECOVERY  = 0x05,
 690         NVME_FEAT_VOLATILE_WC   = 0x06,
 691         NVME_FEAT_NUM_QUEUES    = 0x07,
 692         NVME_FEAT_IRQ_COALESCE  = 0x08,
 693         NVME_FEAT_IRQ_CONFIG    = 0x09,
 694         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 695         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 696         NVME_FEAT_AUTO_PST      = 0x0c,
 697         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 698         NVME_FEAT_TIMESTAMP     = 0x0e,
 699         NVME_FEAT_KATO          = 0x0f,
 700         NVME_FEAT_SW_PROGRESS   = 0x80,
 701         NVME_FEAT_HOST_ID       = 0x81,
 702         NVME_FEAT_RESV_MASK     = 0x82,
 703         NVME_FEAT_RESV_PERSIST  = 0x83,
 704         NVME_LOG_ERROR          = 0x01,
 705         NVME_LOG_SMART          = 0x02,
 706         NVME_LOG_FW_SLOT        = 0x03,
 707         NVME_LOG_DISC           = 0x70,
 708         NVME_LOG_RESERVATION    = 0x80,
 709         NVME_FWACT_REPL         = (0 << 3),
 710         NVME_FWACT_REPL_ACTV    = (1 << 3),
 711         NVME_FWACT_ACTV         = (2 << 3),
 712 };
 713
 714 struct nvme_identify {
 715         __u8                    opcode;
 716         __u8                    flags;
 717         __u16                   command_id;
 718         __le32                  nsid;
 719         __u64                   rsvd2[2];
 720         union nvme_data_ptr     dptr;
 721         __u8                    cns;
 722         __u8                    rsvd3;
 723         __le16                  ctrlid;
 724         __u32                   rsvd11[5];
 725 };
 726
 727 #define NVME_IDENTIFY_DATA_SIZE 4096
 728
 729 struct nvme_features {
 730         __u8                    opcode;
 731         __u8                    flags;
 732         __u16                   command_id;
 733         __le32                  nsid;
 734         __u64                   rsvd2[2];
 735         union nvme_data_ptr     dptr;
 736         __le32                  fid;
 737         __le32                  dword11;
 738         __le32                  dword12;
 739         __le32                  dword13;
 740         __le32                  dword14;
 741         __le32                  dword15;
 742 };
 743
 744 struct nvme_host_mem_buf_desc {
 745         __le64                  addr;
 746         __le32                  size;
 747         __u32                   rsvd;
 748 };
 749
 750 struct nvme_create_cq {
 751         __u8                    opcode;
 752         __u8                    flags;
 753         __u16                   command_id;
 754         __u32                   rsvd1[5];
 755         __le64                  prp1;
 756         __u64                   rsvd8;
 757         __le16                  cqid;
 758         __le16                  qsize;
 759         __le16                  cq_flags;
 760         __le16                  irq_vector;
 761         __u32                   rsvd12[4];
 762 };
 763
 764 struct nvme_create_sq {
 765         __u8                    opcode;
 766         __u8                    flags;
 767         __u16                   command_id;
 768         __u32                   rsvd1[5];
 769         __le64                  prp1;
 770         __u64                   rsvd8;
 771         __le16                  sqid;
 772         __le16                  qsize;
 773         __le16                  sq_flags;
 774         __le16                  cqid;
 775         __u32                   rsvd12[4];
 776 };
 777
 778 struct nvme_delete_queue {
 779         __u8                    opcode;
 780         __u8                    flags;
 781         __u16                   command_id;
 782         __u32                   rsvd1[9];
 783         __le16                  qid;
 784         __u16                   rsvd10;
 785         __u32                   rsvd11[5];
 786 };
 787
 788 struct nvme_abort_cmd {
 789         __u8                    opcode;
 790         __u8                    flags;
 791         __u16                   command_id;
 792         __u32                   rsvd1[9];
 793         __le16                  sqid;
 794         __u16                   cid;
 795         __u32                   rsvd11[5];
 796 };
 797
 798 struct nvme_download_firmware {
 799         __u8                    opcode;
 800         __u8                    flags;
 801         __u16                   command_id;
 802         __u32                   rsvd1[5];
 803         union nvme_data_ptr     dptr;
 804         __le32                  numd;
 805         __le32                  offset;
 806         __u32                   rsvd12[4];
 807 };
 808
 809 struct nvme_format_cmd {
 810         __u8                    opcode;
 811         __u8                    flags;
 812         __u16                   command_id;
 813         __le32                  nsid;
 814         __u64                   rsvd2[4];
 815         __le32                  cdw10;
 816         __u32                   rsvd11[5];
 817 };
 818
 819 struct nvme_get_log_page_command {
 820         __u8                    opcode;
 821         __u8                    flags;
 822         __u16                   command_id;
 823         __le32                  nsid;
 824         __u64                   rsvd2[2];
 825         union nvme_data_ptr     dptr;
 826         __u8                    lid;
 827         __u8                    rsvd10;
 828         __le16                  numdl;
 829         __le16                  numdu;
 830         __u16                   rsvd11;
 831         __le32                  lpol;
 832         __le32                  lpou;
 833         __u32                   rsvd14[2];
 834 };
 835
 836 struct nvme_directive_cmd {
 837         __u8                    opcode;
 838         __u8                    flags;
 839         __u16                   command_id;
 840         __le32                  nsid;
 841         __u64                   rsvd2[2];
 842         union nvme_data_ptr     dptr;
 843         __le32                  numd;
 844         __u8                    doper;
 845         __u8                    dtype;
 846         __le16                  dspec;
 847         __u8                    endir;
 848         __u8                    tdtype;
 849         __u16                   rsvd15;
 850
 851         __u32                   rsvd16[3];
 852 };
 853
 854 /*
 855  * Fabrics subcommands.
 856  */
 857 enum nvmf_fabrics_opcode {
 858         nvme_fabrics_command            = 0x7f,
 859 };
 860
 861 enum nvmf_capsule_command {
 862         nvme_fabrics_type_property_set  = 0x00,
 863         nvme_fabrics_type_connect       = 0x01,
 864         nvme_fabrics_type_property_get  = 0x04,
 865 };
 866
 867 struct nvmf_common_command {
 868         __u8    opcode;
 869         __u8    resv1;
 870         __u16   command_id;
 871         __u8    fctype;
 872         __u8    resv2[35];
 873         __u8    ts[24];
 874 };
 875
 876 /*
 877  * The legal cntlid range a NVMe Target will provide.
 878  * Note that cntlid of value 0 is considered illegal in the fabrics world.
 879  * Devices based on earlier specs did not have the subsystem concept;
 880  * therefore, those devices had their cntlid value set to 0 as a result.
 881  */
 882 #define NVME_CNTLID_MIN         1
 883 #define NVME_CNTLID_MAX         0xffef
 884 #define NVME_CNTLID_DYNAMIC     0xffff
 885
 886 #define MAX_DISC_LOGS   255
 887
 888 /* Discovery log page entry */
 889 struct nvmf_disc_rsp_page_entry {
 890         __u8            trtype;
 891         __u8            adrfam;
 892         __u8            subtype;
 893         __u8            treq;
 894         __le16          portid;
 895         __le16          cntlid;
 896         __le16          asqsz;
 897         __u8            resv8[22];
 898         char            trsvcid[NVMF_TRSVCID_SIZE];
 899         __u8            resv64[192];
 900         char            subnqn[NVMF_NQN_FIELD_LEN];
 901         char            traddr[NVMF_TRADDR_SIZE];
 902         union tsas {
 903                 char            common[NVMF_TSAS_SIZE];
 904                 struct rdma {
 905                         __u8    qptype;
 906                         __u8    prtype;
 907                         __u8    cms;
 908                         __u8    resv3[5];
 909                         __u16   pkey;
 910                         __u8    resv10[246];
 911                 } rdma;
 912         } tsas;
 913 };
 914
 915 /* Discovery log page header */
 916 struct nvmf_disc_rsp_page_hdr {
 917         __le64          genctr;
 918         __le64          numrec;
 919         __le16          recfmt;
 920         __u8            resv14[1006];
 921         struct nvmf_disc_rsp_page_entry entries[0];
 922 };
 923
 924 struct nvmf_connect_command {
 925         __u8            opcode;
 926         __u8            resv1;
 927         __u16           command_id;
 928         __u8            fctype;
 929         __u8            resv2[19];
 930         union nvme_data_ptr dptr;
 931         __le16          recfmt;
 932         __le16          qid;
 933         __le16          sqsize;
 934         __u8            cattr;
 935         __u8            resv3;
 936         __le32          kato;
 937         __u8            resv4[12];
 938 };
 939
 940 struct nvmf_connect_data {
 941         uuid_t          hostid;
 942         __le16          cntlid;
 943         char            resv4[238];
 944         char            subsysnqn[NVMF_NQN_FIELD_LEN];
 945         char            hostnqn[NVMF_NQN_FIELD_LEN];
 946         char            resv5[256];
 947 };
 948
 949 struct nvmf_property_set_command {
 950         __u8            opcode;
 951         __u8            resv1;
 952         __u16           command_id;
 953         __u8            fctype;
 954         __u8            resv2[35];
 955         __u8            attrib;
 956         __u8            resv3[3];
 957         __le32          offset;
 958         __le64          value;
 959         __u8            resv4[8];
 960 };
 961
 962 struct nvmf_property_get_command {
 963         __u8            opcode;
 964         __u8            resv1;
 965         __u16           command_id;
 966         __u8            fctype;
 967         __u8            resv2[35];
 968         __u8            attrib;
 969         __u8            resv3[3];
 970         __le32          offset;
 971         __u8            resv4[16];
 972 };
 973
 974 struct nvme_dbbuf {
 975         __u8                    opcode;
 976         __u8                    flags;
 977         __u16                   command_id;
 978         __u32                   rsvd1[5];
 979         __le64                  prp1;
 980         __le64                  prp2;
 981         __u32                   rsvd12[6];
 982 };
 983
 984 struct streams_directive_params {
 985         __le16  msl;
 986         __le16  nssa;
 987         __le16  nsso;
 988         __u8    rsvd[10];
 989         __le32  sws;
 990         __le16  sgs;
 991         __le16  nsa;
 992         __le16  nso;
 993         __u8    rsvd2[6];
 994 };
 995
 996 struct nvme_command {
 997         union {
 998                 struct nvme_common_command common;
 999                 struct nvme_rw_command rw;
1000                 struct nvme_identify identify;
1001                 struct nvme_features features;
1002                 struct nvme_create_cq create_cq;
1003                 struct nvme_create_sq create_sq;
1004                 struct nvme_delete_queue delete_queue;
1005                 struct nvme_download_firmware dlfw;
1006                 struct nvme_format_cmd format;
1007                 struct nvme_dsm_cmd dsm;
1008                 struct nvme_write_zeroes_cmd write_zeroes;
1009                 struct nvme_abort_cmd abort;
1010                 struct nvme_get_log_page_command get_log_page;
1011                 struct nvmf_common_command fabrics;
1012                 struct nvmf_connect_command connect;
1013                 struct nvmf_property_set_command prop_set;
1014                 struct nvmf_property_get_command prop_get;
1015                 struct nvme_dbbuf dbbuf;
1016                 struct nvme_directive_cmd directive;
1017         };
1018 };
1019
1020 static inline bool nvme_is_write(struct nvme_command *cmd)
1021 {
1022         /*
1023          * What a mess...
1024          *
1025          * Why can't we simply have a Fabrics In and Fabrics out command?
1026          */
1027         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1028                 return cmd->fabrics.fctype & 1;
1029         return cmd->common.opcode & 1;
1030 }
1031
1032 enum {
1033         /*
1034          * Generic Command Status:
1035          */
1036         NVME_SC_SUCCESS                 = 0x0,
1037         NVME_SC_INVALID_OPCODE          = 0x1,
1038         NVME_SC_INVALID_FIELD           = 0x2,
1039         NVME_SC_CMDID_CONFLICT          = 0x3,
1040         NVME_SC_DATA_XFER_ERROR         = 0x4,
1041         NVME_SC_POWER_LOSS              = 0x5,
1042         NVME_SC_INTERNAL                = 0x6,
1043         NVME_SC_ABORT_REQ               = 0x7,
1044         NVME_SC_ABORT_QUEUE             = 0x8,
1045         NVME_SC_FUSED_FAIL              = 0x9,
1046         NVME_SC_FUSED_MISSING           = 0xa,
1047         NVME_SC_INVALID_NS              = 0xb,
1048         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1049         NVME_SC_SGL_INVALID_LAST        = 0xd,
1050         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1051         NVME_SC_SGL_INVALID_DATA        = 0xf,
1052         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1053         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1054
1055         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1056         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1057
1058         NVME_SC_LBA_RANGE               = 0x80,
1059         NVME_SC_CAP_EXCEEDED            = 0x81,
1060         NVME_SC_NS_NOT_READY            = 0x82,
1061         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1062
1063         /*
1064          * Command Specific Status:
1065          */
1066         NVME_SC_CQ_INVALID              = 0x100,
1067         NVME_SC_QID_INVALID             = 0x101,
1068         NVME_SC_QUEUE_SIZE              = 0x102,
1069         NVME_SC_ABORT_LIMIT             = 0x103,
1070         NVME_SC_ABORT_MISSING           = 0x104,
1071         NVME_SC_ASYNC_LIMIT             = 0x105,
1072         NVME_SC_FIRMWARE_SLOT           = 0x106,
1073         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1074         NVME_SC_INVALID_VECTOR          = 0x108,
1075         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1076         NVME_SC_INVALID_FORMAT          = 0x10a,
1077         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1078         NVME_SC_INVALID_QUEUE           = 0x10c,
1079         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1080         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1081         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1082         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1083         NVME_SC_FW_NEEDS_RESET          = 0x111,
1084         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1085         NVME_SC_FW_ACIVATE_PROHIBITED   = 0x113,
1086         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1087         NVME_SC_NS_INSUFFICENT_CAP      = 0x115,
1088         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1089         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1090         NVME_SC_NS_IS_PRIVATE           = 0x119,
1091         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1092         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1093         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1094
1095         /*
1096          * I/O Command Set Specific - NVM commands:
1097          */
1098         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1099         NVME_SC_INVALID_PI              = 0x181,
1100         NVME_SC_READ_ONLY               = 0x182,
1101         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1102
1103         /*
1104          * I/O Command Set Specific - Fabrics commands:
1105          */
1106         NVME_SC_CONNECT_FORMAT          = 0x180,
1107         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1108         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1109         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1110         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1111
1112         NVME_SC_DISCOVERY_RESTART       = 0x190,
1113         NVME_SC_AUTH_REQUIRED           = 0x191,
1114
1115         /*
1116          * Media and Data Integrity Errors:
1117          */
1118         NVME_SC_WRITE_FAULT             = 0x280,
1119         NVME_SC_READ_ERROR              = 0x281,
1120         NVME_SC_GUARD_CHECK             = 0x282,
1121         NVME_SC_APPTAG_CHECK            = 0x283,
1122         NVME_SC_REFTAG_CHECK            = 0x284,
1123         NVME_SC_COMPARE_FAILED          = 0x285,
1124         NVME_SC_ACCESS_DENIED           = 0x286,
1125         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1126
1127         NVME_SC_DNR                     = 0x4000,
1128
1129
1130         /*
1131          * FC Transport-specific error status values for NVME commands
1132          *
1133          * Transport-specific status code values must be in the range 0xB0..0xBF
1134          */
1135
1136         /* Generic FC failure - catchall */
1137         NVME_SC_FC_TRANSPORT_ERROR      = 0x00B0,
1138
1139         /* I/O failure due to FC ABTS'd */
1140         NVME_SC_FC_TRANSPORT_ABORTED    = 0x00B1,
1141 };
1142
1143 struct nvme_completion {
1144         /*
1145          * Used by Admin and Fabrics commands to return data:
1146          */
1147         union nvme_result {
1148                 __le16  u16;
1149                 __le32  u32;
1150                 __le64  u64;
1151         } result;
1152         __le16  sq_head;        /* how much of this queue may be reclaimed */
1153         __le16  sq_id;          /* submission queue that generated this entry */
1154         __u16   command_id;     /* of the command which completed */
1155         __le16  status;         /* did the command fail, and if so, why? */
1156 };
1157
1158 #define NVME_VS(major, minor, tertiary) \
1159         (((major) << 16) | ((minor) << 8) | (tertiary))
1160
1161 #define NVME_MAJOR(ver)         ((ver) >> 16)
1162 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1163 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1164
1165 #endif /* _LINUX_NVME_H */