4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
195 /* These values come from the PCI Express Spec */
196 enum pcie_link_width {
197 PCIE_LNK_WIDTH_RESRV = 0x00,
205 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
208 /* Based on the PCI Hotplug Spec, but some values are made up by us */
210 PCI_SPEED_33MHz = 0x00,
211 PCI_SPEED_66MHz = 0x01,
212 PCI_SPEED_66MHz_PCIX = 0x02,
213 PCI_SPEED_100MHz_PCIX = 0x03,
214 PCI_SPEED_133MHz_PCIX = 0x04,
215 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
216 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
217 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
218 PCI_SPEED_66MHz_PCIX_266 = 0x09,
219 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
220 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
226 PCI_SPEED_66MHz_PCIX_533 = 0x11,
227 PCI_SPEED_100MHz_PCIX_533 = 0x12,
228 PCI_SPEED_133MHz_PCIX_533 = 0x13,
229 PCIE_SPEED_2_5GT = 0x14,
230 PCIE_SPEED_5_0GT = 0x15,
231 PCIE_SPEED_8_0GT = 0x16,
232 PCI_SPEED_UNKNOWN = 0xff,
235 struct pci_cap_saved_data {
242 struct pci_cap_saved_state {
243 struct hlist_node next;
244 struct pci_cap_saved_data cap;
248 struct pcie_link_state;
254 * The pci_dev structure is used to describe PCI devices.
257 struct list_head bus_list; /* node in per-bus list */
258 struct pci_bus *bus; /* bus this device is on */
259 struct pci_bus *subordinate; /* bus this device bridges to */
261 void *sysdata; /* hook for sys-specific extension */
262 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
263 struct pci_slot *slot; /* Physical slot this device is in */
265 unsigned int devfn; /* encoded device & function index */
266 unsigned short vendor;
267 unsigned short device;
268 unsigned short subsystem_vendor;
269 unsigned short subsystem_device;
270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
271 u8 revision; /* PCI revision, low byte of class word */
272 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
273 #ifdef CONFIG_PCIEAER
274 u16 aer_cap; /* AER capability offset */
276 u8 pcie_cap; /* PCIe capability offset */
277 u8 msi_cap; /* MSI capability offset */
278 u8 msix_cap; /* MSI-X capability offset */
279 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
280 u8 rom_base_reg; /* which config register controls the ROM */
281 u8 pin; /* which interrupt pin this device uses */
282 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
283 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
285 struct pci_driver *driver; /* which driver has allocated this device */
286 u64 dma_mask; /* Mask of the bits of bus address this
287 device implements. Normally this is
288 0xffffffff. You only need to change
289 this if your device has broken DMA
290 or supports 64-bit transfers. */
292 struct device_dma_parameters dma_parms;
294 pci_power_t current_state; /* Current operating state. In ACPI-speak,
295 this is D0-D3, D0 being fully functional,
297 u8 pm_cap; /* PM capability offset */
298 unsigned int pme_support:5; /* Bitmask of states from which PME#
300 unsigned int pme_interrupt:1;
301 unsigned int pme_poll:1; /* Poll device's PME status bit */
302 unsigned int d1_support:1; /* Low power state D1 is supported */
303 unsigned int d2_support:1; /* Low power state D2 is supported */
304 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
305 unsigned int no_d3cold:1; /* D3cold is forbidden */
306 unsigned int bridge_d3:1; /* Allow D3 for bridge */
307 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
308 unsigned int mmio_always_on:1; /* disallow turning off io/mem
309 decoding during bar sizing */
310 unsigned int wakeup_prepared:1;
311 unsigned int runtime_d3cold:1; /* whether go through runtime
312 D3cold, not set for devices
313 powered on/off by the
314 corresponding bridge */
315 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
316 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
317 controlled exclusively by
319 unsigned int d3_delay; /* D3->D0 transition time in ms */
320 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
322 #ifdef CONFIG_PCIEASPM
323 struct pcie_link_state *link_state; /* ASPM link state */
326 pci_channel_state_t error_state; /* current connectivity state */
327 struct device dev; /* Generic device interface */
329 int cfg_size; /* Size of configuration space */
332 * Instead of touching interrupt line and base address registers
333 * directly, use the values stored here. They might be different!
336 struct cpumask *irq_affinity;
337 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
339 bool match_driver; /* Skip attaching driver */
340 /* These fields are used by common fixups */
341 unsigned int transparent:1; /* Subtractive decode PCI bridge */
342 unsigned int multifunction:1;/* Part of multi-function device */
343 /* keep track of device state */
344 unsigned int is_added:1;
345 unsigned int is_busmaster:1; /* device is busmaster */
346 unsigned int no_msi:1; /* device may not use msi */
347 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
348 unsigned int block_cfg_access:1; /* config space access is blocked */
349 unsigned int broken_parity_status:1; /* Device generates false positive parity */
350 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
351 unsigned int msi_enabled:1;
352 unsigned int msix_enabled:1;
353 unsigned int ari_enabled:1; /* ARI forwarding */
354 unsigned int ats_enabled:1; /* Address Translation Service */
355 unsigned int is_managed:1;
356 unsigned int needs_freset:1; /* Dev requires fundamental reset */
357 unsigned int state_saved:1;
358 unsigned int is_physfn:1;
359 unsigned int is_virtfn:1;
360 unsigned int reset_fn:1;
361 unsigned int is_hotplug_bridge:1;
362 unsigned int __aer_firmware_first_valid:1;
363 unsigned int __aer_firmware_first:1;
364 unsigned int broken_intx_masking:1;
365 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
366 unsigned int irq_managed:1;
367 unsigned int has_secondary_link:1;
368 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
369 pci_dev_flags_t dev_flags;
370 atomic_t enable_cnt; /* pci_enable_device has been called */
372 u32 saved_config_space[16]; /* config space saved at suspend time */
373 struct hlist_head saved_cap_space;
374 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
375 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
376 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
377 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
379 #ifdef CONFIG_PCIE_PTM
380 unsigned int ptm_root:1;
381 unsigned int ptm_enabled:1;
384 #ifdef CONFIG_PCI_MSI
385 const struct attribute_group **msi_irq_groups;
388 #ifdef CONFIG_PCI_ATS
390 struct pci_sriov *sriov; /* SR-IOV capability related */
391 struct pci_dev *physfn; /* the PF this VF is associated with */
393 u16 ats_cap; /* ATS Capability offset */
394 u8 ats_stu; /* ATS Smallest Translation Unit */
395 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
397 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
398 size_t romlen; /* Length of ROM if it's not from the BAR */
399 char *driver_override; /* Driver name to force a match */
402 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
404 #ifdef CONFIG_PCI_IOV
411 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
413 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
414 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
416 static inline int pci_channel_offline(struct pci_dev *pdev)
418 return (pdev->error_state != pci_channel_io_normal);
421 struct pci_host_bridge {
423 struct pci_bus *bus; /* root bus */
424 struct list_head windows; /* resource_entry */
425 void (*release_fn)(struct pci_host_bridge *);
427 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
428 /* Resource alignment requirements */
429 resource_size_t (*align_resource)(struct pci_dev *dev,
430 const struct resource *res,
431 resource_size_t start,
432 resource_size_t size,
433 resource_size_t align);
436 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
438 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
440 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
441 void (*release_fn)(struct pci_host_bridge *),
444 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
447 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
448 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
449 * buses below host bridges or subtractive decode bridges) go in the list.
450 * Use pci_bus_for_each_resource() to iterate through all the resources.
454 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
455 * and there's no way to program the bridge with the details of the window.
456 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
457 * decode bit set, because they are explicit and can be programmed with _SRS.
459 #define PCI_SUBTRACTIVE_DECODE 0x1
461 struct pci_bus_resource {
462 struct list_head list;
463 struct resource *res;
467 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
470 struct list_head node; /* node in list of buses */
471 struct pci_bus *parent; /* parent bus this bridge is on */
472 struct list_head children; /* list of child buses */
473 struct list_head devices; /* list of devices on this bus */
474 struct pci_dev *self; /* bridge device as seen by parent */
475 struct list_head slots; /* list of slots on this bus;
476 protected by pci_slot_mutex */
477 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
478 struct list_head resources; /* address space routed to this bus */
479 struct resource busn_res; /* bus numbers routed to this bus */
481 struct pci_ops *ops; /* configuration access functions */
482 struct msi_controller *msi; /* MSI controller */
483 void *sysdata; /* hook for sys-specific extension */
484 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
486 unsigned char number; /* bus number */
487 unsigned char primary; /* number of primary bridge */
488 unsigned char max_bus_speed; /* enum pci_bus_speed */
489 unsigned char cur_bus_speed; /* enum pci_bus_speed */
490 #ifdef CONFIG_PCI_DOMAINS_GENERIC
496 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
497 pci_bus_flags_t bus_flags; /* inherited by child buses */
498 struct device *bridge;
500 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
501 struct bin_attribute *legacy_mem; /* legacy mem */
502 unsigned int is_added:1;
505 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
508 * Returns true if the PCI bus is root (behind host-PCI bridge),
511 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
512 * This is incorrect because "virtual" buses added for SR-IOV (via
513 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
515 static inline bool pci_is_root_bus(struct pci_bus *pbus)
517 return !(pbus->parent);
521 * pci_is_bridge - check if the PCI device is a bridge
524 * Return true if the PCI device is bridge whether it has subordinate
527 static inline bool pci_is_bridge(struct pci_dev *dev)
529 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
530 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
533 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
535 dev = pci_physfn(dev);
536 if (pci_is_root_bus(dev->bus))
539 return dev->bus->self;
542 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
543 void pci_put_host_bridge_device(struct device *dev);
545 #ifdef CONFIG_PCI_MSI
546 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
548 return pci_dev->msi_enabled || pci_dev->msix_enabled;
551 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
555 * Error values that may be returned by PCI functions.
557 #define PCIBIOS_SUCCESSFUL 0x00
558 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
559 #define PCIBIOS_BAD_VENDOR_ID 0x83
560 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
561 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
562 #define PCIBIOS_SET_FAILED 0x88
563 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
566 * Translate above to generic errno for passing back through non-PCI code.
568 static inline int pcibios_err_to_errno(int err)
570 if (err <= PCIBIOS_SUCCESSFUL)
571 return err; /* Assume already errno */
574 case PCIBIOS_FUNC_NOT_SUPPORTED:
576 case PCIBIOS_BAD_VENDOR_ID:
578 case PCIBIOS_DEVICE_NOT_FOUND:
580 case PCIBIOS_BAD_REGISTER_NUMBER:
582 case PCIBIOS_SET_FAILED:
584 case PCIBIOS_BUFFER_TOO_SMALL:
591 /* Low-level architecture-dependent routines */
594 int (*add_bus)(struct pci_bus *bus);
595 void (*remove_bus)(struct pci_bus *bus);
596 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
597 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
598 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
602 * ACPI needs to be able to access PCI config space before we've done a
603 * PCI bus scan and created pci_bus structures.
605 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
606 int reg, int len, u32 *val);
607 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
608 int reg, int len, u32 val);
610 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
611 typedef u64 pci_bus_addr_t;
613 typedef u32 pci_bus_addr_t;
616 struct pci_bus_region {
617 pci_bus_addr_t start;
622 spinlock_t lock; /* protects list, index */
623 struct list_head list; /* for IDs added at runtime */
628 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
629 * a set of callbacks in struct pci_error_handlers, that device driver
630 * will be notified of PCI bus errors, and will be driven to recovery
631 * when an error occurs.
634 typedef unsigned int __bitwise pci_ers_result_t;
636 enum pci_ers_result {
637 /* no result/none/not supported in device driver */
638 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
640 /* Device driver can recover without slot reset */
641 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
643 /* Device driver wants slot to be reset. */
644 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
646 /* Device has completely failed, is unrecoverable */
647 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
649 /* Device driver is fully recovered and operational */
650 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
652 /* No AER capabilities registered for the driver */
653 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
656 /* PCI bus error event callbacks */
657 struct pci_error_handlers {
658 /* PCI bus error detected on this device */
659 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
660 enum pci_channel_state error);
662 /* MMIO has been re-enabled, but not DMA */
663 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
665 /* PCI Express link has been reset */
666 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
668 /* PCI slot has been reset */
669 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
671 /* PCI function reset prepare or completed */
672 void (*reset_notify)(struct pci_dev *dev, bool prepare);
674 /* Device driver may resume normal operations */
675 void (*resume)(struct pci_dev *dev);
681 struct list_head node;
683 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
684 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
685 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
686 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
687 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
688 int (*resume_early) (struct pci_dev *dev);
689 int (*resume) (struct pci_dev *dev); /* Device woken up */
690 void (*shutdown) (struct pci_dev *dev);
691 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
692 const struct pci_error_handlers *err_handler;
693 struct device_driver driver;
694 struct pci_dynids dynids;
697 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
700 * PCI_DEVICE - macro used to describe a specific pci device
701 * @vend: the 16 bit PCI Vendor ID
702 * @dev: the 16 bit PCI Device ID
704 * This macro is used to create a struct pci_device_id that matches a
705 * specific device. The subvendor and subdevice fields will be set to
708 #define PCI_DEVICE(vend,dev) \
709 .vendor = (vend), .device = (dev), \
710 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
713 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
714 * @vend: the 16 bit PCI Vendor ID
715 * @dev: the 16 bit PCI Device ID
716 * @subvend: the 16 bit PCI Subvendor ID
717 * @subdev: the 16 bit PCI Subdevice ID
719 * This macro is used to create a struct pci_device_id that matches a
720 * specific device with subsystem information.
722 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
723 .vendor = (vend), .device = (dev), \
724 .subvendor = (subvend), .subdevice = (subdev)
727 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
728 * @dev_class: the class, subclass, prog-if triple for this device
729 * @dev_class_mask: the class mask for this device
731 * This macro is used to create a struct pci_device_id that matches a
732 * specific PCI class. The vendor, device, subvendor, and subdevice
733 * fields will be set to PCI_ANY_ID.
735 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
736 .class = (dev_class), .class_mask = (dev_class_mask), \
737 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
738 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
741 * PCI_VDEVICE - macro used to describe a specific pci device in short form
742 * @vend: the vendor name
743 * @dev: the 16 bit PCI Device ID
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific PCI device. The subvendor, and subdevice fields will be set
747 * to PCI_ANY_ID. The macro allows the next field to follow as the device
751 #define PCI_VDEVICE(vend, dev) \
752 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
753 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
756 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
757 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
758 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
759 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
760 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
761 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
762 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
765 /* these external functions are only available when PCI support is enabled */
768 extern unsigned int pci_flags;
770 static inline void pci_set_flags(int flags) { pci_flags = flags; }
771 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
772 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
773 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
775 void pcie_bus_configure_settings(struct pci_bus *bus);
777 enum pcie_bus_config_types {
778 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
779 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
780 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
781 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
782 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
785 extern enum pcie_bus_config_types pcie_bus_config;
787 extern struct bus_type pci_bus_type;
789 /* Do NOT directly access these two variables, unless you are arch-specific PCI
790 * code, or PCI core code. */
791 extern struct list_head pci_root_buses; /* list of all known PCI buses */
792 /* Some device drivers need know if PCI is initiated */
793 int no_pci_devices(void);
795 void pcibios_resource_survey_bus(struct pci_bus *bus);
796 void pcibios_bus_add_device(struct pci_dev *pdev);
797 void pcibios_add_bus(struct pci_bus *bus);
798 void pcibios_remove_bus(struct pci_bus *bus);
799 void pcibios_fixup_bus(struct pci_bus *);
800 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
801 /* Architecture-specific versions may override this (weak) */
802 char *pcibios_setup(char *str);
804 /* Used only when drivers/pci/setup.c is used */
805 resource_size_t pcibios_align_resource(void *, const struct resource *,
808 void pcibios_update_irq(struct pci_dev *, int irq);
810 /* Weak but can be overriden by arch */
811 void pci_fixup_cardbus(struct pci_bus *);
813 /* Generic PCI functions used internally */
815 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
816 struct resource *res);
817 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
818 struct pci_bus_region *region);
819 void pcibios_scan_specific_bus(int busn);
820 struct pci_bus *pci_find_bus(int domain, int busnr);
821 void pci_bus_add_devices(const struct pci_bus *bus);
822 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
823 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
824 struct pci_ops *ops, void *sysdata,
825 struct list_head *resources);
826 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
827 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
828 void pci_bus_release_busn_res(struct pci_bus *b);
829 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
830 struct pci_ops *ops, void *sysdata,
831 struct list_head *resources,
832 struct msi_controller *msi);
833 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
834 struct pci_ops *ops, void *sysdata,
835 struct list_head *resources);
836 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
838 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
839 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
841 struct hotplug_slot *hotplug);
842 void pci_destroy_slot(struct pci_slot *slot);
844 void pci_dev_assign_slot(struct pci_dev *dev);
846 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
848 int pci_scan_slot(struct pci_bus *bus, int devfn);
849 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
850 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
851 unsigned int pci_scan_child_bus(struct pci_bus *bus);
852 void pci_bus_add_device(struct pci_dev *dev);
853 void pci_read_bridge_bases(struct pci_bus *child);
854 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
855 struct resource *res);
856 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
857 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
858 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
859 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
860 struct pci_dev *pci_dev_get(struct pci_dev *dev);
861 void pci_dev_put(struct pci_dev *dev);
862 void pci_remove_bus(struct pci_bus *b);
863 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
864 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
865 void pci_stop_root_bus(struct pci_bus *bus);
866 void pci_remove_root_bus(struct pci_bus *bus);
867 void pci_setup_cardbus(struct pci_bus *bus);
868 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
869 void pci_sort_breadthfirst(void);
870 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
871 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
872 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
874 /* Generic PCI functions exported to card drivers */
876 enum pci_lost_interrupt_reason {
877 PCI_LOST_IRQ_NO_INFORMATION = 0,
878 PCI_LOST_IRQ_DISABLE_MSI,
879 PCI_LOST_IRQ_DISABLE_MSIX,
880 PCI_LOST_IRQ_DISABLE_ACPI,
882 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
883 int pci_find_capability(struct pci_dev *dev, int cap);
884 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
885 int pci_find_ext_capability(struct pci_dev *dev, int cap);
886 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
887 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
888 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
889 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
891 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
892 struct pci_dev *from);
893 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
894 unsigned int ss_vendor, unsigned int ss_device,
895 struct pci_dev *from);
896 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
897 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
899 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
902 return pci_get_domain_bus_and_slot(0, bus, devfn);
904 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
905 int pci_dev_present(const struct pci_device_id *ids);
907 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
909 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
910 int where, u16 *val);
911 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
912 int where, u32 *val);
913 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
915 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
917 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
920 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
921 int where, int size, u32 *val);
922 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
923 int where, int size, u32 val);
924 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
925 int where, int size, u32 *val);
926 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
927 int where, int size, u32 val);
929 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
931 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
933 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
935 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
937 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
939 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
942 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
944 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
946 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
948 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
950 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
952 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
955 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
958 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
959 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
960 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
961 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
962 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
964 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
967 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
970 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
973 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
976 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
979 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
982 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
985 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
988 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
991 /* user-space driven config access */
992 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
993 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
994 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
995 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
996 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
997 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
999 int __must_check pci_enable_device(struct pci_dev *dev);
1000 int __must_check pci_enable_device_io(struct pci_dev *dev);
1001 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1002 int __must_check pci_reenable_device(struct pci_dev *);
1003 int __must_check pcim_enable_device(struct pci_dev *pdev);
1004 void pcim_pin_device(struct pci_dev *pdev);
1006 static inline int pci_is_enabled(struct pci_dev *pdev)
1008 return (atomic_read(&pdev->enable_cnt) > 0);
1011 static inline int pci_is_managed(struct pci_dev *pdev)
1013 return pdev->is_managed;
1016 void pci_disable_device(struct pci_dev *dev);
1018 extern unsigned int pcibios_max_latency;
1019 void pci_set_master(struct pci_dev *dev);
1020 void pci_clear_master(struct pci_dev *dev);
1022 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1023 int pci_set_cacheline_size(struct pci_dev *dev);
1024 #define HAVE_PCI_SET_MWI
1025 int __must_check pci_set_mwi(struct pci_dev *dev);
1026 int pci_try_set_mwi(struct pci_dev *dev);
1027 void pci_clear_mwi(struct pci_dev *dev);
1028 void pci_intx(struct pci_dev *dev, int enable);
1029 bool pci_intx_mask_supported(struct pci_dev *dev);
1030 bool pci_check_and_mask_intx(struct pci_dev *dev);
1031 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1032 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1033 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1034 int pcix_get_max_mmrbc(struct pci_dev *dev);
1035 int pcix_get_mmrbc(struct pci_dev *dev);
1036 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1037 int pcie_get_readrq(struct pci_dev *dev);
1038 int pcie_set_readrq(struct pci_dev *dev, int rq);
1039 int pcie_get_mps(struct pci_dev *dev);
1040 int pcie_set_mps(struct pci_dev *dev, int mps);
1041 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1042 enum pcie_link_width *width);
1043 int __pci_reset_function(struct pci_dev *dev);
1044 int __pci_reset_function_locked(struct pci_dev *dev);
1045 int pci_reset_function(struct pci_dev *dev);
1046 int pci_try_reset_function(struct pci_dev *dev);
1047 int pci_probe_reset_slot(struct pci_slot *slot);
1048 int pci_reset_slot(struct pci_slot *slot);
1049 int pci_try_reset_slot(struct pci_slot *slot);
1050 int pci_probe_reset_bus(struct pci_bus *bus);
1051 int pci_reset_bus(struct pci_bus *bus);
1052 int pci_try_reset_bus(struct pci_bus *bus);
1053 void pci_reset_secondary_bus(struct pci_dev *dev);
1054 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1055 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1056 void pci_update_resource(struct pci_dev *dev, int resno);
1057 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1058 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1059 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1060 bool pci_device_is_present(struct pci_dev *pdev);
1061 void pci_ignore_hotplug(struct pci_dev *dev);
1063 /* ROM control related routines */
1064 int pci_enable_rom(struct pci_dev *pdev);
1065 void pci_disable_rom(struct pci_dev *pdev);
1066 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1067 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1068 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1069 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1071 /* Power management related routines */
1072 int pci_save_state(struct pci_dev *dev);
1073 void pci_restore_state(struct pci_dev *dev);
1074 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1075 int pci_load_saved_state(struct pci_dev *dev,
1076 struct pci_saved_state *state);
1077 int pci_load_and_free_saved_state(struct pci_dev *dev,
1078 struct pci_saved_state **state);
1079 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1080 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1082 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1083 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1084 u16 cap, unsigned int size);
1085 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1086 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1087 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1088 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1089 void pci_pme_active(struct pci_dev *dev, bool enable);
1090 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1091 bool runtime, bool enable);
1092 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1093 int pci_prepare_to_sleep(struct pci_dev *dev);
1094 int pci_back_from_sleep(struct pci_dev *dev);
1095 bool pci_dev_run_wake(struct pci_dev *dev);
1096 bool pci_check_pme_status(struct pci_dev *dev);
1097 void pci_pme_wakeup_bus(struct pci_bus *bus);
1098 void pci_d3cold_enable(struct pci_dev *dev);
1099 void pci_d3cold_disable(struct pci_dev *dev);
1101 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1104 return __pci_enable_wake(dev, state, false, enable);
1107 /* PCI Virtual Channel */
1108 int pci_save_vc_state(struct pci_dev *dev);
1109 void pci_restore_vc_state(struct pci_dev *dev);
1110 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1112 /* For use by arch with custom probe code */
1113 void set_pcie_port_type(struct pci_dev *pdev);
1114 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1116 /* Functions for PCI Hotplug drivers to use */
1117 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1118 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1119 unsigned int pci_rescan_bus(struct pci_bus *bus);
1120 void pci_lock_rescan_remove(void);
1121 void pci_unlock_rescan_remove(void);
1123 /* Vital product data routines */
1124 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1125 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1126 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1128 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1129 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1130 void pci_bus_assign_resources(const struct pci_bus *bus);
1131 void pci_bus_claim_resources(struct pci_bus *bus);
1132 void pci_bus_size_bridges(struct pci_bus *bus);
1133 int pci_claim_resource(struct pci_dev *, int);
1134 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1135 void pci_assign_unassigned_resources(void);
1136 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1137 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1138 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1139 void pdev_enable_device(struct pci_dev *);
1140 int pci_enable_resources(struct pci_dev *, int mask);
1141 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1142 int (*)(const struct pci_dev *, u8, u8));
1143 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1144 #define HAVE_PCI_REQ_REGIONS 2
1145 int __must_check pci_request_regions(struct pci_dev *, const char *);
1146 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1147 void pci_release_regions(struct pci_dev *);
1148 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1149 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1150 void pci_release_region(struct pci_dev *, int);
1151 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1152 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1153 void pci_release_selected_regions(struct pci_dev *, int);
1155 /* drivers/pci/bus.c */
1156 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1157 void pci_bus_put(struct pci_bus *bus);
1158 void pci_add_resource(struct list_head *resources, struct resource *res);
1159 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1160 resource_size_t offset);
1161 void pci_free_resource_list(struct list_head *resources);
1162 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1163 unsigned int flags);
1164 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1165 void pci_bus_remove_resources(struct pci_bus *bus);
1166 int devm_request_pci_bus_resources(struct device *dev,
1167 struct list_head *resources);
1169 #define pci_bus_for_each_resource(bus, res, i) \
1171 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1174 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1175 struct resource *res, resource_size_t size,
1176 resource_size_t align, resource_size_t min,
1177 unsigned long type_mask,
1178 resource_size_t (*alignf)(void *,
1179 const struct resource *,
1185 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1186 unsigned long pci_address_to_pio(phys_addr_t addr);
1187 phys_addr_t pci_pio_to_address(unsigned long pio);
1188 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1189 void pci_unmap_iospace(struct resource *res);
1191 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1193 struct pci_bus_region region;
1195 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1196 return region.start;
1199 /* Proper probing supporting hot-pluggable devices */
1200 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1201 const char *mod_name);
1204 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1206 #define pci_register_driver(driver) \
1207 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1209 void pci_unregister_driver(struct pci_driver *dev);
1212 * module_pci_driver() - Helper macro for registering a PCI driver
1213 * @__pci_driver: pci_driver struct
1215 * Helper macro for PCI drivers which do not do anything special in module
1216 * init/exit. This eliminates a lot of boilerplate. Each module may only
1217 * use this macro once, and calling it replaces module_init() and module_exit()
1219 #define module_pci_driver(__pci_driver) \
1220 module_driver(__pci_driver, pci_register_driver, \
1221 pci_unregister_driver)
1224 * builtin_pci_driver() - Helper macro for registering a PCI driver
1225 * @__pci_driver: pci_driver struct
1227 * Helper macro for PCI drivers which do not do anything special in their
1228 * init code. This eliminates a lot of boilerplate. Each driver may only
1229 * use this macro once, and calling it replaces device_initcall(...)
1231 #define builtin_pci_driver(__pci_driver) \
1232 builtin_driver(__pci_driver, pci_register_driver)
1234 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1235 int pci_add_dynid(struct pci_driver *drv,
1236 unsigned int vendor, unsigned int device,
1237 unsigned int subvendor, unsigned int subdevice,
1238 unsigned int class, unsigned int class_mask,
1239 unsigned long driver_data);
1240 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1241 struct pci_dev *dev);
1242 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1245 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1247 int pci_cfg_space_size(struct pci_dev *dev);
1248 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1249 void pci_setup_bridge(struct pci_bus *bus);
1250 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1251 unsigned long type);
1252 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1254 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1255 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1257 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1258 unsigned int command_bits, u32 flags);
1260 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1261 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1262 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1263 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1264 #define PCI_IRQ_ALL_TYPES \
1265 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1267 /* kmem_cache style wrapper around pci_alloc_consistent() */
1269 #include <linux/pci-dma.h>
1270 #include <linux/dmapool.h>
1272 #define pci_pool dma_pool
1273 #define pci_pool_create(name, pdev, size, align, allocation) \
1274 dma_pool_create(name, &pdev->dev, size, align, allocation)
1275 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1276 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1277 #define pci_pool_zalloc(pool, flags, handle) \
1278 dma_pool_zalloc(pool, flags, handle)
1279 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1282 u32 vector; /* kernel uses to write allocated vector */
1283 u16 entry; /* driver uses to specify entry, OS writes */
1286 #ifdef CONFIG_PCI_MSI
1287 int pci_msi_vec_count(struct pci_dev *dev);
1288 void pci_msi_shutdown(struct pci_dev *dev);
1289 void pci_disable_msi(struct pci_dev *dev);
1290 int pci_msix_vec_count(struct pci_dev *dev);
1291 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1292 void pci_msix_shutdown(struct pci_dev *dev);
1293 void pci_disable_msix(struct pci_dev *dev);
1294 void pci_restore_msi_state(struct pci_dev *dev);
1295 int pci_msi_enabled(void);
1296 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1297 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1299 int rc = pci_enable_msi_range(dev, nvec, nvec);
1304 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1305 int minvec, int maxvec);
1306 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1307 struct msix_entry *entries, int nvec)
1309 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1314 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1315 unsigned int max_vecs, unsigned int flags,
1316 const struct irq_affinity *affd);
1318 void pci_free_irq_vectors(struct pci_dev *dev);
1319 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1320 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1323 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1324 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1325 static inline void pci_disable_msi(struct pci_dev *dev) { }
1326 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1327 static inline int pci_enable_msix(struct pci_dev *dev,
1328 struct msix_entry *entries, int nvec)
1330 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1331 static inline void pci_disable_msix(struct pci_dev *dev) { }
1332 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1333 static inline int pci_msi_enabled(void) { return 0; }
1334 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1337 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1339 static inline int pci_enable_msix_range(struct pci_dev *dev,
1340 struct msix_entry *entries, int minvec, int maxvec)
1342 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1343 struct msix_entry *entries, int nvec)
1347 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1348 unsigned int max_vecs, unsigned int flags,
1349 const struct irq_affinity *aff_desc)
1356 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1360 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1362 if (WARN_ON_ONCE(nr > 0))
1366 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1369 return cpu_possible_mask;
1374 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1375 unsigned int max_vecs, unsigned int flags)
1377 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1381 #ifdef CONFIG_PCIEPORTBUS
1382 extern bool pcie_ports_disabled;
1383 extern bool pcie_ports_auto;
1385 #define pcie_ports_disabled true
1386 #define pcie_ports_auto false
1389 #ifdef CONFIG_PCIEASPM
1390 bool pcie_aspm_support_enabled(void);
1392 static inline bool pcie_aspm_support_enabled(void) { return false; }
1395 #ifdef CONFIG_PCIEAER
1396 void pci_no_aer(void);
1397 bool pci_aer_available(void);
1398 int pci_aer_init(struct pci_dev *dev);
1400 static inline void pci_no_aer(void) { }
1401 static inline bool pci_aer_available(void) { return false; }
1402 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1405 #ifdef CONFIG_PCIE_ECRC
1406 void pcie_set_ecrc_checking(struct pci_dev *dev);
1407 void pcie_ecrc_get_policy(char *str);
1409 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1410 static inline void pcie_ecrc_get_policy(char *str) { }
1413 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1415 #ifdef CONFIG_HT_IRQ
1416 /* The functions a driver should call */
1417 int ht_create_irq(struct pci_dev *dev, int idx);
1418 void ht_destroy_irq(unsigned int irq);
1419 #endif /* CONFIG_HT_IRQ */
1421 #ifdef CONFIG_PCI_ATS
1422 /* Address Translation Service */
1423 void pci_ats_init(struct pci_dev *dev);
1424 int pci_enable_ats(struct pci_dev *dev, int ps);
1425 void pci_disable_ats(struct pci_dev *dev);
1426 int pci_ats_queue_depth(struct pci_dev *dev);
1428 static inline void pci_ats_init(struct pci_dev *d) { }
1429 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1430 static inline void pci_disable_ats(struct pci_dev *d) { }
1431 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1434 #ifdef CONFIG_PCIE_PTM
1435 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1437 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1441 void pci_cfg_access_lock(struct pci_dev *dev);
1442 bool pci_cfg_access_trylock(struct pci_dev *dev);
1443 void pci_cfg_access_unlock(struct pci_dev *dev);
1446 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1447 * a PCI domain is defined to be a set of PCI buses which share
1448 * configuration space.
1450 #ifdef CONFIG_PCI_DOMAINS
1451 extern int pci_domains_supported;
1452 int pci_get_new_domain_nr(void);
1454 enum { pci_domains_supported = 0 };
1455 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1456 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1457 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1458 #endif /* CONFIG_PCI_DOMAINS */
1461 * Generic implementation for PCI domain support. If your
1462 * architecture does not need custom management of PCI
1463 * domains then this implementation will be used
1465 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1466 static inline int pci_domain_nr(struct pci_bus *bus)
1468 return bus->domain_nr;
1471 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1473 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1476 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1479 /* some architectures require additional setup to direct VGA traffic */
1480 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1481 unsigned int command_bits, u32 flags);
1482 void pci_register_set_vga_state(arch_set_vga_state_t func);
1485 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1487 return pci_request_selected_regions(pdev,
1488 pci_select_bars(pdev, IORESOURCE_IO), name);
1492 pci_release_io_regions(struct pci_dev *pdev)
1494 return pci_release_selected_regions(pdev,
1495 pci_select_bars(pdev, IORESOURCE_IO));
1499 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1501 return pci_request_selected_regions(pdev,
1502 pci_select_bars(pdev, IORESOURCE_MEM), name);
1506 pci_release_mem_regions(struct pci_dev *pdev)
1508 return pci_release_selected_regions(pdev,
1509 pci_select_bars(pdev, IORESOURCE_MEM));
1512 #else /* CONFIG_PCI is not enabled */
1514 static inline void pci_set_flags(int flags) { }
1515 static inline void pci_add_flags(int flags) { }
1516 static inline void pci_clear_flags(int flags) { }
1517 static inline int pci_has_flag(int flag) { return 0; }
1520 * If the system does not have PCI, clearly these return errors. Define
1521 * these as simple inline functions to avoid hair in drivers.
1524 #define _PCI_NOP(o, s, t) \
1525 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1527 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1529 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1530 _PCI_NOP(o, word, u16 x) \
1531 _PCI_NOP(o, dword, u32 x)
1532 _PCI_NOP_ALL(read, *)
1533 _PCI_NOP_ALL(write,)
1535 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1536 unsigned int device,
1537 struct pci_dev *from)
1540 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1541 unsigned int device,
1542 unsigned int ss_vendor,
1543 unsigned int ss_device,
1544 struct pci_dev *from)
1547 static inline struct pci_dev *pci_get_class(unsigned int class,
1548 struct pci_dev *from)
1551 #define pci_dev_present(ids) (0)
1552 #define no_pci_devices() (1)
1553 #define pci_dev_put(dev) do { } while (0)
1555 static inline void pci_set_master(struct pci_dev *dev) { }
1556 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1557 static inline void pci_disable_device(struct pci_dev *dev) { }
1558 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1560 static inline int __pci_register_driver(struct pci_driver *drv,
1561 struct module *owner)
1563 static inline int pci_register_driver(struct pci_driver *drv)
1565 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1566 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1568 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1571 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1574 /* Power management related routines */
1575 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1576 static inline void pci_restore_state(struct pci_dev *dev) { }
1577 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1579 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1581 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1584 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1588 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1589 struct resource *res)
1591 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1593 static inline void pci_release_regions(struct pci_dev *dev) { }
1595 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1597 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1598 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1600 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1602 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1604 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1607 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1611 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1612 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1613 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1615 #define dev_is_pci(d) (false)
1616 #define dev_is_pf(d) (false)
1617 #define dev_num_vf(d) (0)
1618 #endif /* CONFIG_PCI */
1620 /* Include architecture-dependent settings and functions */
1622 #include <asm/pci.h>
1624 #ifndef pci_root_bus_fwnode
1625 #define pci_root_bus_fwnode(bus) NULL
1628 /* these helpers provide future and backwards compatibility
1629 * for accessing popular PCI BAR info */
1630 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1631 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1632 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1633 #define pci_resource_len(dev,bar) \
1634 ((pci_resource_start((dev), (bar)) == 0 && \
1635 pci_resource_end((dev), (bar)) == \
1636 pci_resource_start((dev), (bar))) ? 0 : \
1638 (pci_resource_end((dev), (bar)) - \
1639 pci_resource_start((dev), (bar)) + 1))
1641 /* Similar to the helpers above, these manipulate per-pci_dev
1642 * driver-specific data. They are really just a wrapper around
1643 * the generic device structure functions of these calls.
1645 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1647 return dev_get_drvdata(&pdev->dev);
1650 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1652 dev_set_drvdata(&pdev->dev, data);
1655 /* If you want to know what to call your pci_dev, ask this function.
1656 * Again, it's a wrapper around the generic device.
1658 static inline const char *pci_name(const struct pci_dev *pdev)
1660 return dev_name(&pdev->dev);
1664 /* Some archs don't want to expose struct resource to userland as-is
1665 * in sysfs and /proc
1667 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1668 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1669 const struct resource *rsrc,
1670 resource_size_t *start, resource_size_t *end);
1672 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1673 const struct resource *rsrc, resource_size_t *start,
1674 resource_size_t *end)
1676 *start = rsrc->start;
1679 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1683 * The world is not perfect and supplies us with broken PCI devices.
1684 * For at least a part of these bugs we need a work-around, so both
1685 * generic (drivers/pci/quirks.c) and per-architecture code can define
1686 * fixup hooks to be called for particular buggy devices.
1690 u16 vendor; /* You can use PCI_ANY_ID here of course */
1691 u16 device; /* You can use PCI_ANY_ID here of course */
1692 u32 class; /* You can use PCI_ANY_ID here too */
1693 unsigned int class_shift; /* should be 0, 8, 16 */
1694 void (*hook)(struct pci_dev *dev);
1697 enum pci_fixup_pass {
1698 pci_fixup_early, /* Before probing BARs */
1699 pci_fixup_header, /* After reading configuration header */
1700 pci_fixup_final, /* Final phase of device fixups */
1701 pci_fixup_enable, /* pci_enable_device() time */
1702 pci_fixup_resume, /* pci_device_resume() */
1703 pci_fixup_suspend, /* pci_device_suspend() */
1704 pci_fixup_resume_early, /* pci_device_resume_early() */
1705 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1708 /* Anonymous variables would be nice... */
1709 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1710 class_shift, hook) \
1711 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1712 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1713 = { vendor, device, class, class_shift, hook };
1715 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1716 class_shift, hook) \
1717 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1718 hook, vendor, device, class, class_shift, hook)
1719 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1720 class_shift, hook) \
1721 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1722 hook, vendor, device, class, class_shift, hook)
1723 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1724 class_shift, hook) \
1725 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1726 hook, vendor, device, class, class_shift, hook)
1727 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1728 class_shift, hook) \
1729 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1730 hook, vendor, device, class, class_shift, hook)
1731 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1732 class_shift, hook) \
1733 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1734 resume##hook, vendor, device, class, \
1736 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1737 class_shift, hook) \
1738 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1739 resume_early##hook, vendor, device, \
1740 class, class_shift, hook)
1741 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1742 class_shift, hook) \
1743 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1744 suspend##hook, vendor, device, class, \
1746 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1747 class_shift, hook) \
1748 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1749 suspend_late##hook, vendor, device, \
1750 class, class_shift, hook)
1752 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1753 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1754 hook, vendor, device, PCI_ANY_ID, 0, hook)
1755 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1756 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1757 hook, vendor, device, PCI_ANY_ID, 0, hook)
1758 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1759 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1760 hook, vendor, device, PCI_ANY_ID, 0, hook)
1761 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1762 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1763 hook, vendor, device, PCI_ANY_ID, 0, hook)
1764 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1765 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1766 resume##hook, vendor, device, \
1767 PCI_ANY_ID, 0, hook)
1768 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1770 resume_early##hook, vendor, device, \
1771 PCI_ANY_ID, 0, hook)
1772 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1773 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1774 suspend##hook, vendor, device, \
1775 PCI_ANY_ID, 0, hook)
1776 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1777 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1778 suspend_late##hook, vendor, device, \
1779 PCI_ANY_ID, 0, hook)
1781 #ifdef CONFIG_PCI_QUIRKS
1782 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1783 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1784 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1786 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1787 struct pci_dev *dev) { }
1788 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1793 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1799 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1800 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1801 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1802 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1803 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1805 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1807 extern int pci_pci_problems;
1808 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1809 #define PCIPCI_TRITON 2
1810 #define PCIPCI_NATOMA 4
1811 #define PCIPCI_VIAETBF 8
1812 #define PCIPCI_VSFX 16
1813 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1814 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1816 extern unsigned long pci_cardbus_io_size;
1817 extern unsigned long pci_cardbus_mem_size;
1818 extern u8 pci_dfl_cache_line_size;
1819 extern u8 pci_cache_line_size;
1821 extern unsigned long pci_hotplug_io_size;
1822 extern unsigned long pci_hotplug_mem_size;
1823 extern unsigned long pci_hotplug_bus_size;
1825 /* Architecture-specific versions may override these (weak) */
1826 void pcibios_disable_device(struct pci_dev *dev);
1827 void pcibios_set_master(struct pci_dev *dev);
1828 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1829 enum pcie_reset_state state);
1830 int pcibios_add_device(struct pci_dev *dev);
1831 void pcibios_release_device(struct pci_dev *dev);
1832 void pcibios_penalize_isa_irq(int irq, int active);
1833 int pcibios_alloc_irq(struct pci_dev *dev);
1834 void pcibios_free_irq(struct pci_dev *dev);
1836 #ifdef CONFIG_HIBERNATE_CALLBACKS
1837 extern struct dev_pm_ops pcibios_pm_ops;
1840 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1841 void __init pci_mmcfg_early_init(void);
1842 void __init pci_mmcfg_late_init(void);
1844 static inline void pci_mmcfg_early_init(void) { }
1845 static inline void pci_mmcfg_late_init(void) { }
1848 int pci_ext_cfg_avail(void);
1850 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1851 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1853 #ifdef CONFIG_PCI_IOV
1854 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1855 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1857 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1858 void pci_disable_sriov(struct pci_dev *dev);
1859 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1860 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1861 int pci_num_vf(struct pci_dev *dev);
1862 int pci_vfs_assigned(struct pci_dev *dev);
1863 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1864 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1865 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1867 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1871 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1875 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1877 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1881 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1882 int id, int reset) { }
1883 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1884 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1885 static inline int pci_vfs_assigned(struct pci_dev *dev)
1887 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1889 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1891 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1895 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1896 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1897 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1901 * pci_pcie_cap - get the saved PCIe capability offset
1904 * PCIe capability offset is calculated at PCI device initialization
1905 * time and saved in the data structure. This function returns saved
1906 * PCIe capability offset. Using this instead of pci_find_capability()
1907 * reduces unnecessary search in the PCI configuration space. If you
1908 * need to calculate PCIe capability offset from raw device for some
1909 * reasons, please use pci_find_capability() instead.
1911 static inline int pci_pcie_cap(struct pci_dev *dev)
1913 return dev->pcie_cap;
1917 * pci_is_pcie - check if the PCI device is PCI Express capable
1920 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1922 static inline bool pci_is_pcie(struct pci_dev *dev)
1924 return pci_pcie_cap(dev);
1928 * pcie_caps_reg - get the PCIe Capabilities Register
1931 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1933 return dev->pcie_flags_reg;
1937 * pci_pcie_type - get the PCIe device/port type
1940 static inline int pci_pcie_type(const struct pci_dev *dev)
1942 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1945 void pci_request_acs(void);
1946 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1947 bool pci_acs_path_enabled(struct pci_dev *start,
1948 struct pci_dev *end, u16 acs_flags);
1950 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1951 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1953 /* Large Resource Data Type Tag Item Names */
1954 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1955 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1956 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1958 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1959 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1960 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1962 /* Small Resource Data Type Tag Item Names */
1963 #define PCI_VPD_STIN_END 0x0f /* End */
1965 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1967 #define PCI_VPD_SRDT_TIN_MASK 0x78
1968 #define PCI_VPD_SRDT_LEN_MASK 0x07
1969 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1971 #define PCI_VPD_LRDT_TAG_SIZE 3
1972 #define PCI_VPD_SRDT_TAG_SIZE 1
1974 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1976 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1977 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1978 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1979 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1982 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1983 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1985 * Returns the extracted Large Resource Data Type length.
1987 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1989 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1993 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1994 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1996 * Returns the extracted Large Resource Data Type Tag item.
1998 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2000 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2004 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2005 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2007 * Returns the extracted Small Resource Data Type length.
2009 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2011 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2015 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2016 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2018 * Returns the extracted Small Resource Data Type Tag Item.
2020 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2022 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2026 * pci_vpd_info_field_size - Extracts the information field length
2027 * @lrdt: Pointer to the beginning of an information field header
2029 * Returns the extracted information field length.
2031 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2033 return info_field[2];
2037 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2038 * @buf: Pointer to buffered vpd data
2039 * @off: The offset into the buffer at which to begin the search
2040 * @len: The length of the vpd buffer
2041 * @rdt: The Resource Data Type to search for
2043 * Returns the index where the Resource Data Type was found or
2044 * -ENOENT otherwise.
2046 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2049 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2050 * @buf: Pointer to buffered vpd data
2051 * @off: The offset into the buffer at which to begin the search
2052 * @len: The length of the buffer area, relative to off, in which to search
2053 * @kw: The keyword to search for
2055 * Returns the index where the information field keyword was found or
2056 * -ENOENT otherwise.
2058 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2059 unsigned int len, const char *kw);
2061 /* PCI <-> OF binding helpers */
2065 void pci_set_of_node(struct pci_dev *dev);
2066 void pci_release_of_node(struct pci_dev *dev);
2067 void pci_set_bus_of_node(struct pci_bus *bus);
2068 void pci_release_bus_of_node(struct pci_bus *bus);
2069 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2071 /* Arch may override this (weak) */
2072 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2074 static inline struct device_node *
2075 pci_device_to_OF_node(const struct pci_dev *pdev)
2077 return pdev ? pdev->dev.of_node : NULL;
2080 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2082 return bus ? bus->dev.of_node : NULL;
2085 #else /* CONFIG_OF */
2086 static inline void pci_set_of_node(struct pci_dev *dev) { }
2087 static inline void pci_release_of_node(struct pci_dev *dev) { }
2088 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2089 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2090 static inline struct device_node *
2091 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2092 static inline struct irq_domain *
2093 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2094 #endif /* CONFIG_OF */
2097 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2100 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2102 static inline struct irq_domain *
2103 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2107 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2109 return pdev->dev.archdata.edev;
2113 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2114 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2115 int pci_for_each_dma_alias(struct pci_dev *pdev,
2116 int (*fn)(struct pci_dev *pdev,
2117 u16 alias, void *data), void *data);
2119 /* helper functions for operation of device flag */
2120 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2122 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2124 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2126 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2128 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2130 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2134 * pci_ari_enabled - query ARI forwarding status
2137 * Returns true if ARI forwarding is enabled.
2139 static inline bool pci_ari_enabled(struct pci_bus *bus)
2141 return bus->self && bus->self->ari_enabled;
2144 /* provide the legacy pci_dma_* API */
2145 #include <linux/pci-dma-compat.h>
2147 #endif /* LINUX_PCI_H */