1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __TI_SYSC_DATA_H__
4 #define __TI_SYSC_DATA_H__
6 enum ti_sysc_module_type {
18 TI_SYSC_OMAP4_USB_HOST_FS,
22 struct ti_sysc_cookie {
28 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
29 * @midle_shift: Offset of the midle bit
30 * @clkact_shift: Offset of the clockactivity bit
31 * @sidle_shift: Offset of the sidle bit
32 * @enwkup_shift: Offset of the enawakeup bit
33 * @srst_shift: Offset of the softreset bit
34 * @autoidle_shift: Offset of the autoidle bit
35 * @dmadisable_shift: Offset of the dmadisable bit
36 * @emufree_shift; Offset of the emufree bit
38 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
39 * feature is not available.
52 #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
53 #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
54 #define SYSC_MODULE_QUIRK_AESS BIT(19)
55 #define SYSC_MODULE_QUIRK_SGX BIT(18)
56 #define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
57 #define SYSC_MODULE_QUIRK_I2C BIT(16)
58 #define SYSC_MODULE_QUIRK_WDT BIT(15)
59 #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
60 #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
61 #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
62 #define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
63 #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10)
64 #define SYSC_QUIRK_LEGACY_IDLE BIT(9)
65 #define SYSC_QUIRK_RESET_STATUS BIT(8)
66 #define SYSC_QUIRK_NO_IDLE BIT(7)
67 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
68 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
69 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
70 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
71 #define SYSC_QUIRK_16BIT BIT(2)
72 #define SYSC_QUIRK_UNCACHED BIT(1)
73 #define SYSC_QUIRK_USE_CLOCKACT BIT(0)
75 #define SYSC_NR_IDLEMODES 4
78 * struct sysc_capabilities - capabilities for an interconnect target module
79 * @type: sysc type identifier for the module
80 * @sysc_mask: bitmask of supported SYSCONFIG register bits
81 * @regbits: bitmask of SYSCONFIG register bits
82 * @mod_quirks: bitmask of module specific quirks
84 struct sysc_capabilities {
85 const enum ti_sysc_module_type type;
87 const struct sysc_regbits *regbits;
92 * struct sysc_config - configuration for an interconnect target module
93 * @sysc_val: configured value for sysc register
94 * @syss_mask: configured mask value for SYSSTATUS register
95 * @midlemodes: bitmask of supported master idle modes
96 * @sidlemodes: bitmask of supported slave idle modes
97 * @srst_udelay: optional delay needed after OCP soft reset
98 * @quirks: bitmask of enabled quirks
109 enum sysc_registers {
117 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
118 * @name: legacy "ti,hwmods" module name
119 * @module_pa: physical address of the interconnect target module
120 * @module_size: size of the interconnect target module
121 * @offsets: array of register offsets as listed in enum sysc_registers
122 * @nr_offsets: number of registers
123 * @cap: interconnect target module capabilities
124 * @cfg: interconnect target module configuration
126 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
127 * based on device tree data parsed by ti-sysc driver.
129 struct ti_sysc_module_data {
135 const struct sysc_capabilities *cap;
136 struct sysc_config *cfg;
142 struct ti_sysc_platform_data {
143 struct of_dev_auxdata *auxdata;
144 int (*init_clockdomain)(struct device *dev, struct clk *fck,
145 struct clk *ick, struct ti_sysc_cookie *cookie);
146 void (*clkdm_deny_idle)(struct device *dev,
147 const struct ti_sysc_cookie *cookie);
148 void (*clkdm_allow_idle)(struct device *dev,
149 const struct ti_sysc_cookie *cookie);
150 int (*init_module)(struct device *dev,
151 const struct ti_sysc_module_data *data,
152 struct ti_sysc_cookie *cookie);
153 int (*enable_module)(struct device *dev,
154 const struct ti_sysc_cookie *cookie);
155 int (*idle_module)(struct device *dev,
156 const struct ti_sysc_cookie *cookie);
157 int (*shutdown_module)(struct device *dev,
158 const struct ti_sysc_cookie *cookie);
161 #endif /* __TI_SYSC_DATA_H__ */