1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/mod_devicetable.h>
12 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
14 /* SDW Broadcast Device Number */
15 #define SDW_BROADCAST_DEV_NUM 15
17 /* SDW Enumeration Device Number */
18 #define SDW_ENUM_DEV_NUM 0
20 /* SDW Group Device Numbers */
21 #define SDW_GROUP12_DEV_NUM 12
22 #define SDW_GROUP13_DEV_NUM 13
24 /* SDW Master Device Number, not supported yet */
25 #define SDW_MASTER_DEV_NUM 14
27 #define SDW_NUM_DEV_ID_REGISTERS 6
28 /* frame shape defines */
31 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
32 * fill hole with 0, one more dummy entry is added
34 #define SDW_FRAME_ROWS 24
35 #define SDW_FRAME_COLS 8
36 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
38 #define SDW_FRAME_CTRL_BITS 48
39 #define SDW_MAX_DEVICES 11
41 #define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1)
44 SDW_PORT_DIRN_SINK = 0,
50 * constants for flow control, ports and transport
52 * these are bit masks as devices can have multiple capabilities
56 * flow modes for SDW port. These can be isochronous, tx controlled,
57 * rx controlled or async
59 #define SDW_PORT_FLOW_MODE_ISOCH 0
60 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
61 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
62 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
64 /* sample packaging for block. It can be per port or per channel */
65 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
66 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
69 * enum sdw_slave_status - Slave status
70 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
71 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
72 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
73 * @SDW_SLAVE_RESERVED: Reserved for future use
75 enum sdw_slave_status {
76 SDW_SLAVE_UNATTACHED = 0,
77 SDW_SLAVE_ATTACHED = 1,
79 SDW_SLAVE_RESERVED = 3,
83 * enum sdw_command_response - Command response as defined by SDW spec
84 * @SDW_CMD_OK: cmd was successful
85 * @SDW_CMD_IGNORED: cmd was ignored
86 * @SDW_CMD_FAIL: cmd was NACKed
87 * @SDW_CMD_TIMEOUT: cmd timedout
88 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
90 * NOTE: The enum is different than actual Spec as response in the Spec is
91 * combination of ACK/NAK bits
93 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
95 enum sdw_command_response {
100 SDW_CMD_FAIL_OTHER = 4,
103 /* block group count enum */
104 enum sdw_dpn_grouping {
105 SDW_BLK_GRP_CNT_1 = 0,
106 SDW_BLK_GRP_CNT_2 = 1,
107 SDW_BLK_GRP_CNT_3 = 2,
108 SDW_BLK_GRP_CNT_4 = 3,
112 * enum sdw_stream_type: data stream type
114 * @SDW_STREAM_PCM: PCM data stream
115 * @SDW_STREAM_PDM: PDM data stream
117 * spec doesn't define this, but is used in implementation
119 enum sdw_stream_type {
125 * enum sdw_data_direction: Data direction
127 * @SDW_DATA_DIR_RX: Data into Port
128 * @SDW_DATA_DIR_TX: Data out of Port
130 enum sdw_data_direction {
136 * enum sdw_port_data_mode: Data Port mode
138 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
140 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
141 * logic 1. The encoding will result in signal transitions at every bitslot
143 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
144 * logic 0. The encoding will result in no signal transitions
145 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
146 * a pseudo random data pattern that is transferred
148 enum sdw_port_data_mode {
149 SDW_PORT_DATA_MODE_NORMAL = 0,
150 SDW_PORT_DATA_MODE_STATIC_1 = 1,
151 SDW_PORT_DATA_MODE_STATIC_0 = 2,
152 SDW_PORT_DATA_MODE_PRBS = 3,
156 * SDW properties, defined in MIPI DisCo spec v1.0
158 enum sdw_clk_stop_reset_behave {
159 SDW_CLK_STOP_KEEP_STATUS = 1,
163 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
165 * @SDW_P15_READ_IGNORED: Read is ignored
166 * @SDW_P15_CMD_OK: Command is ok
168 enum sdw_p15_behave {
169 SDW_P15_READ_IGNORED = 0,
174 * enum sdw_dpn_type - Data port types
175 * @SDW_DPN_FULL: Full Data Port is supported
176 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
177 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
178 * are not implemented.
179 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
180 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
189 * enum sdw_clk_stop_mode - Clock Stop modes
190 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
192 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
193 * not capable of continuing operation seamlessly when the clock restarts
195 enum sdw_clk_stop_mode {
196 SDW_CLK_STOP_MODE0 = 0,
197 SDW_CLK_STOP_MODE1 = 1,
201 * struct sdw_dp0_prop - DP0 properties
202 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
204 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
206 * @num_words: number of wordlengths supported
207 * @words: wordlengths supported
208 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
210 * @simple_ch_prep_sm: If channel prepare sequence is required
211 * @imp_def_interrupts: If set, each bit corresponds to support for
212 * implementation-defined interrupts
214 * The wordlengths are specified by Spec as max, min AND number of
215 * discrete values, implementation can define based on the wordlengths they
218 struct sdw_dp0_prop {
223 bool BRA_flow_controlled;
224 bool simple_ch_prep_sm;
225 bool imp_def_interrupts;
229 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
230 * @bus_min_freq: Minimum bus frequency, in Hz
231 * @bus_max_freq: Maximum bus frequency, in Hz
232 * @bus_num_freq: Number of discrete frequencies supported
233 * @bus_freq: Discrete bus frequencies, in Hz
234 * @min_freq: Minimum sampling frequency, in Hz
235 * @max_freq: Maximum sampling bus frequency, in Hz
236 * @num_freq: Number of discrete sampling frequency supported
237 * @freq: Discrete sampling frequencies, in Hz
238 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
239 * sequence and bus clock configuration
240 * If 0, Channel Prepare can happen at any Bus clock rate
241 * If 1, Channel Prepare sequence shall happen only after Bus clock is
242 * changed to a frequency supported by this mode or compatible modes
243 * described by the next field
244 * @glitchless: Bitmap describing possible glitchless transitions from this
245 * Audio Mode to other Audio Modes
247 struct sdw_dpn_audio_mode {
261 * struct sdw_dpn_prop - Data Port DPn properties
263 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
265 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
267 * @num_words: Number of discrete supported wordlengths
268 * @words: Discrete supported wordlength
269 * @type: Data port type. Full, Simplified or Reduced
270 * @max_grouping: Maximum number of samples that can be grouped together for
272 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
274 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
275 * @imp_def_interrupts: If set, each bit corresponds to support for
276 * implementation-defined interrupts
277 * @max_ch: Maximum channels supported
278 * @min_ch: Minimum channels supported
279 * @num_ch: Number of discrete channels supported
280 * @ch: Discrete channels supported
281 * @num_ch_combinations: Number of channel combinations supported
282 * @ch_combinations: Channel combinations supported
283 * @modes: SDW mode supported
284 * @max_async_buffer: Number of samples that this port can buffer in
286 * @block_pack_mode: Type of block port mode supported
287 * @port_encoding: Payload Channel Sample encoding schemes supported
288 * @audio_modes: Audio modes supported
290 struct sdw_dpn_prop {
296 enum sdw_dpn_type type;
298 bool simple_ch_prep_sm;
300 u32 imp_def_interrupts;
305 u32 num_ch_combinations;
306 u32 *ch_combinations;
308 u32 max_async_buffer;
309 bool block_pack_mode;
311 struct sdw_dpn_audio_mode *audio_modes;
315 * struct sdw_slave_prop - SoundWire Slave properties
316 * @mipi_revision: Spec version of the implementation
317 * @wake_capable: Wake-up events are supported
318 * @test_mode_capable: If test mode is supported
319 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
320 * @simple_clk_stop_capable: Simple clock mode is supported
321 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
322 * Machine transitions, in milliseconds
323 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
324 * transitions, in milliseconds
325 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
326 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
327 * @high_PHY_capable: Slave is HighPHY capable
328 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
330 * @bank_delay_support: Slave implements bank delay/bridge support registers
331 * SCP_BankDelay and SCP_NextFrame
332 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
334 * @lane_control_support: Slave supports lane control
335 * @master_count: Number of Masters present on this Slave
336 * @source_ports: Bitmap identifying source ports
337 * @sink_ports: Bitmap identifying sink ports
338 * @dp0_prop: Data Port 0 properties
339 * @src_dpn_prop: Source Data Port N properties
340 * @sink_dpn_prop: Sink Data Port N properties
342 struct sdw_slave_prop {
345 bool test_mode_capable;
347 bool simple_clk_stop_capable;
348 u32 clk_stop_timeout;
350 enum sdw_clk_stop_reset_behave reset_behave;
351 bool high_PHY_capable;
353 bool bank_delay_support;
354 enum sdw_p15_behave p15_behave;
355 bool lane_control_support;
359 struct sdw_dp0_prop *dp0_prop;
360 struct sdw_dpn_prop *src_dpn_prop;
361 struct sdw_dpn_prop *sink_dpn_prop;
365 * struct sdw_master_prop - Master properties
366 * @revision: MIPI spec version of the implementation
367 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
368 * @max_clk_freq: Maximum Bus clock frequency, in Hz
369 * @num_clk_gears: Number of clock gears supported
370 * @clk_gears: Clock gears supported
371 * @num_clk_freq: Number of clock frequencies supported, in Hz
372 * @clk_freq: Clock frequencies supported, in Hz
373 * @default_frame_rate: Controller default Frame rate, in Hz
374 * @default_row: Number of rows
375 * @default_col: Number of columns
376 * @dynamic_frame: Dynamic frame shape supported
377 * @err_threshold: Number of times that software may retry sending a single
379 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
380 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
382 struct sdw_master_prop {
390 u32 default_frame_rate;
399 int sdw_master_read_prop(struct sdw_bus *bus);
400 int sdw_slave_read_prop(struct sdw_slave *slave);
403 * SDW Slave Structures and APIs
406 #define SDW_IGNORED_UNIQUE_ID 0xFF
409 * struct sdw_slave_id - Slave ID
410 * @mfg_id: MIPI Manufacturer ID
411 * @part_id: Device Part ID
412 * @class_id: MIPI Class ID, unused now.
413 * Currently a placeholder in MIPI SoundWire Spec
414 * @unique_id: Device unique ID
415 * @sdw_version: SDW version implemented
417 * The order of the IDs here does not follow the DisCo spec definitions
419 struct sdw_slave_id {
428 * struct sdw_slave_intr_status - Slave interrupt status
429 * @control_port: control port status
430 * @port: data port status
432 struct sdw_slave_intr_status {
438 * sdw_reg_bank - SoundWire register banks
439 * @SDW_BANK0: Soundwire register bank 0
440 * @SDW_BANK1: Soundwire register bank 1
448 * struct sdw_bus_conf: Bus configuration
450 * @clk_freq: Clock frequency, in Hz
451 * @num_rows: Number of rows in frame
452 * @num_cols: Number of columns in frame
453 * @bank: Next register bank
455 struct sdw_bus_conf {
456 unsigned int clk_freq;
457 unsigned int num_rows;
458 unsigned int num_cols;
463 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
466 * @ch_mask: Active channel mask
467 * @prepare: Prepare (true) /de-prepare (false) channel
468 * @bank: Register bank, which bank Slave/Master driver should program for
469 * implementation defined registers. This is always updated to next_bank
470 * value read from bus params.
473 struct sdw_prepare_ch {
475 unsigned int ch_mask;
481 * enum sdw_port_prep_ops: Prepare operations for Data Port
483 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
484 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
485 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
487 enum sdw_port_prep_ops {
488 SDW_OPS_PORT_PRE_PREP = 0,
489 SDW_OPS_PORT_PREP = 1,
490 SDW_OPS_PORT_POST_PREP = 2,
494 * struct sdw_bus_params: Structure holding bus configuration
496 * @curr_bank: Current bank in use (BANK0/BANK1)
497 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
499 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
500 * @curr_dr_freq: Current double rate clock frequency, in Hz
501 * @bandwidth: Current bandwidth
502 * @col: Active columns
505 struct sdw_bus_params {
506 enum sdw_reg_bank curr_bank;
507 enum sdw_reg_bank next_bank;
508 unsigned int max_dr_freq;
509 unsigned int curr_dr_freq;
510 unsigned int bandwidth;
516 * struct sdw_slave_ops: Slave driver callback ops
518 * @read_prop: Read Slave properties
519 * @interrupt_callback: Device interrupt notification (invoked in thread
521 * @update_status: Update Slave status
522 * @bus_config: Update the bus config for Slave
523 * @port_prep: Prepare the port with parameters
525 struct sdw_slave_ops {
526 int (*read_prop)(struct sdw_slave *sdw);
527 int (*interrupt_callback)(struct sdw_slave *slave,
528 struct sdw_slave_intr_status *status);
529 int (*update_status)(struct sdw_slave *slave,
530 enum sdw_slave_status status);
531 int (*bus_config)(struct sdw_slave *slave,
532 struct sdw_bus_params *params);
533 int (*port_prep)(struct sdw_slave *slave,
534 struct sdw_prepare_ch *prepare_ch,
535 enum sdw_port_prep_ops pre_ops);
539 * struct sdw_slave - SoundWire Slave
540 * @id: MIPI device ID
542 * @status: Status reported by the Slave
544 * @ops: Slave callback ops
545 * @prop: Slave properties
546 * @debugfs: Slave debugfs
547 * @node: node for bus list
548 * @port_ready: Port ready completion flag for each Slave port
549 * @dev_num: Device Number assigned by Bus
552 struct sdw_slave_id id;
554 enum sdw_slave_status status;
556 const struct sdw_slave_ops *ops;
557 struct sdw_slave_prop prop;
558 #ifdef CONFIG_DEBUG_FS
559 struct dentry *debugfs;
561 struct list_head node;
562 struct completion *port_ready;
566 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
571 int (*probe)(struct sdw_slave *sdw,
572 const struct sdw_device_id *id);
573 int (*remove)(struct sdw_slave *sdw);
574 void (*shutdown)(struct sdw_slave *sdw);
576 const struct sdw_device_id *id_table;
577 const struct sdw_slave_ops *ops;
579 struct device_driver driver;
582 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
583 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
584 .driver_data = (unsigned long)(_drv_data) }
586 int sdw_handle_slave_status(struct sdw_bus *bus,
587 enum sdw_slave_status status[]);
590 * SDW master structures and APIs
594 * struct sdw_port_params: Data Port parameters
597 * @bps: Word length of the Port
598 * @flow_mode: Port Data flow mode
599 * @data_mode: Test modes or normal mode
601 * This is used to program the Data Port based on Data Port stream
604 struct sdw_port_params {
607 unsigned int flow_mode;
608 unsigned int data_mode;
612 * struct sdw_transport_params: Data Port Transport Parameters
614 * @blk_grp_ctrl_valid: Port implements block group control
616 * @blk_grp_ctrl: Block group control value
617 * @sample_interval: Sample interval
618 * @offset1: Blockoffset of the payload data
619 * @offset2: Blockoffset of the payload data
620 * @hstart: Horizontal start of the payload data
621 * @hstop: Horizontal stop of the payload data
622 * @blk_pkg_mode: Block per channel or block per port
623 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
624 * data lane is supported in bus
626 * This is used to program the Data Port based on Data Port transport
627 * parameters. All these parameters are banked and can be modified
628 * during a bank switch without any artifacts in audio stream.
630 struct sdw_transport_params {
631 bool blk_grp_ctrl_valid;
632 unsigned int port_num;
633 unsigned int blk_grp_ctrl;
634 unsigned int sample_interval;
635 unsigned int offset1;
636 unsigned int offset2;
639 unsigned int blk_pkg_mode;
640 unsigned int lane_ctrl;
644 * struct sdw_enable_ch: Enable/disable Data Port channel
647 * @ch_mask: Active channel mask
648 * @enable: Enable (true) /disable (false) channel
650 struct sdw_enable_ch {
651 unsigned int port_num;
652 unsigned int ch_mask;
657 * struct sdw_master_port_ops: Callback functions from bus to Master
658 * driver to set Master Data ports.
660 * @dpn_set_port_params: Set the Port parameters for the Master Port.
662 * @dpn_set_port_transport_params: Set transport parameters for the Master
663 * Port. Mandatory callback
664 * @dpn_port_prep: Port prepare operations for the Master Data Port.
665 * @dpn_port_enable_ch: Enable the channels of Master Port.
667 struct sdw_master_port_ops {
668 int (*dpn_set_port_params)(struct sdw_bus *bus,
669 struct sdw_port_params *port_params,
671 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
672 struct sdw_transport_params *transport_params,
673 enum sdw_reg_bank bank);
674 int (*dpn_port_prep)(struct sdw_bus *bus,
675 struct sdw_prepare_ch *prepare_ch);
676 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
677 struct sdw_enable_ch *enable_ch, unsigned int bank);
683 * struct sdw_defer - SDW deffered message
684 * @length: message length
685 * @complete: message completion
690 struct completion complete;
695 * struct sdw_master_ops - Master driver ops
696 * @read_prop: Read Master properties
697 * @xfer_msg: Transfer message callback
698 * @xfer_msg_defer: Defer version of transfer message callback
699 * @reset_page_addr: Reset the SCP page address registers
700 * @set_bus_conf: Set the bus configuration
701 * @pre_bank_switch: Callback for pre bank switch
702 * @post_bank_switch: Callback for post bank switch
704 struct sdw_master_ops {
705 int (*read_prop)(struct sdw_bus *bus);
707 enum sdw_command_response (*xfer_msg)
708 (struct sdw_bus *bus, struct sdw_msg *msg);
709 enum sdw_command_response (*xfer_msg_defer)
710 (struct sdw_bus *bus, struct sdw_msg *msg,
711 struct sdw_defer *defer);
712 enum sdw_command_response (*reset_page_addr)
713 (struct sdw_bus *bus, unsigned int dev_num);
714 int (*set_bus_conf)(struct sdw_bus *bus,
715 struct sdw_bus_params *params);
716 int (*pre_bank_switch)(struct sdw_bus *bus);
717 int (*post_bank_switch)(struct sdw_bus *bus);
722 * struct sdw_bus - SoundWire bus
723 * @dev: Master linux device
724 * @link_id: Link id number, can be 0 to N, unique for each Master
725 * @slaves: list of Slaves on this bus
726 * @assigned: Bitmap for Slave device numbers.
727 * Bit set implies used number, bit clear implies unused number.
728 * @bus_lock: bus lock
729 * @msg_lock: message lock
730 * @compute_params: points to Bus resource management implementation
731 * @ops: Master callback ops
732 * @port_ops: Master port callback ops
733 * @params: Current bus parameters
734 * @prop: Master properties
735 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
736 * is used to compute and program bus bandwidth, clock, frame shape,
737 * transport and port parameters
738 * @debugfs: Bus debugfs
739 * @defer_msg: Defer message
740 * @clk_stop_timeout: Clock stop timeout computed
741 * @bank_switch_timeout: Bank switch timeout computed
742 * @multi_link: Store bus property that indicates if multi links
743 * are supported. This flag is populated by drivers after reading
744 * appropriate firmware (ACPI/DT).
748 unsigned int link_id;
749 struct list_head slaves;
750 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
751 struct mutex bus_lock;
752 struct mutex msg_lock;
753 int (*compute_params)(struct sdw_bus *bus);
754 const struct sdw_master_ops *ops;
755 const struct sdw_master_port_ops *port_ops;
756 struct sdw_bus_params params;
757 struct sdw_master_prop prop;
758 struct list_head m_rt_list;
759 #ifdef CONFIG_DEBUG_FS
760 struct dentry *debugfs;
762 struct sdw_defer defer_msg;
763 unsigned int clk_stop_timeout;
764 u32 bank_switch_timeout;
768 int sdw_add_bus_master(struct sdw_bus *bus);
769 void sdw_delete_bus_master(struct sdw_bus *bus);
772 * sdw_port_config: Master or Slave Port configuration
775 * @ch_mask: channels mask for port
777 struct sdw_port_config {
779 unsigned int ch_mask;
783 * sdw_stream_config: Master or Slave stream configuration
785 * @frame_rate: Audio frame rate of the stream, in Hz
786 * @ch_count: Channel count of the stream
787 * @bps: Number of bits per audio sample
788 * @direction: Data direction
789 * @type: Stream type PCM or PDM
791 struct sdw_stream_config {
792 unsigned int frame_rate;
793 unsigned int ch_count;
795 enum sdw_data_direction direction;
796 enum sdw_stream_type type;
800 * sdw_stream_state: Stream states
802 * @SDW_STREAM_ALLOCATED: New stream allocated.
803 * @SDW_STREAM_CONFIGURED: Stream configured
804 * @SDW_STREAM_PREPARED: Stream prepared
805 * @SDW_STREAM_ENABLED: Stream enabled
806 * @SDW_STREAM_DISABLED: Stream disabled
807 * @SDW_STREAM_DEPREPARED: Stream de-prepared
808 * @SDW_STREAM_RELEASED: Stream released
810 enum sdw_stream_state {
811 SDW_STREAM_ALLOCATED = 0,
812 SDW_STREAM_CONFIGURED = 1,
813 SDW_STREAM_PREPARED = 2,
814 SDW_STREAM_ENABLED = 3,
815 SDW_STREAM_DISABLED = 4,
816 SDW_STREAM_DEPREPARED = 5,
817 SDW_STREAM_RELEASED = 6,
821 * sdw_stream_params: Stream parameters
823 * @rate: Sampling frequency, in Hz
824 * @ch_count: Number of channels
825 * @bps: bits per channel sample
827 struct sdw_stream_params {
829 unsigned int ch_count;
834 * sdw_stream_runtime: Runtime stream parameters
836 * @name: SoundWire stream name
837 * @params: Stream parameters
838 * @state: Current state of the stream
839 * @type: Stream type PCM or PDM
840 * @master_list: List of Master runtime(s) in this stream.
841 * master_list can contain only one m_rt per Master instance
843 * @m_rt_count: Count of Master runtime(s) in this stream
845 struct sdw_stream_runtime {
847 struct sdw_stream_params params;
848 enum sdw_stream_state state;
849 enum sdw_stream_type type;
850 struct list_head master_list;
854 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
855 void sdw_release_stream(struct sdw_stream_runtime *stream);
856 int sdw_stream_add_master(struct sdw_bus *bus,
857 struct sdw_stream_config *stream_config,
858 struct sdw_port_config *port_config,
859 unsigned int num_ports,
860 struct sdw_stream_runtime *stream);
861 int sdw_stream_add_slave(struct sdw_slave *slave,
862 struct sdw_stream_config *stream_config,
863 struct sdw_port_config *port_config,
864 unsigned int num_ports,
865 struct sdw_stream_runtime *stream);
866 int sdw_stream_remove_master(struct sdw_bus *bus,
867 struct sdw_stream_runtime *stream);
868 int sdw_stream_remove_slave(struct sdw_slave *slave,
869 struct sdw_stream_runtime *stream);
870 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
871 int sdw_enable_stream(struct sdw_stream_runtime *stream);
872 int sdw_disable_stream(struct sdw_stream_runtime *stream);
873 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
875 /* messaging and data APIs */
877 int sdw_read(struct sdw_slave *slave, u32 addr);
878 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
879 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
880 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
882 #endif /* __SOUNDWIRE_H */