1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 #define IFH_INJ_BYPASS BIT(31)
15 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
17 #define IFH_TAG_TYPE_C 0
18 #define IFH_TAG_TYPE_S 1
20 #define IFH_REW_OP_NOOP 0x0
21 #define IFH_REW_OP_DSCP 0x1
22 #define IFH_REW_OP_ONE_STEP_PTP 0x2
23 #define IFH_REW_OP_TWO_STEP_PTP 0x3
24 #define IFH_REW_OP_ORIGIN_PTP 0x5
26 #define OCELOT_TAG_LEN 16
27 #define OCELOT_SHORT_PREFIX_LEN 4
28 #define OCELOT_LONG_PREFIX_LEN 16
30 #define OCELOT_SPEED_2500 0
31 #define OCELOT_SPEED_1000 1
32 #define OCELOT_SPEED_100 2
33 #define OCELOT_SPEED_10 3
35 #define TARGET_OFFSET 24
36 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
37 #define REG(reg, offset) [reg & REG_MASK] = offset
39 #define REG_RESERVED_ADDR 0xffffffff
40 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
56 ANA_ADVLEARN = ANA << TARGET_OFFSET,
80 ANA_TABLES_STREAMDATA,
83 ANA_TABLES_VLANACCESS,
85 ANA_TABLES_ISDXACCESS,
88 ANA_TABLES_PTP_ID_HIGH,
89 ANA_TABLES_PTP_ID_LOW,
90 ANA_TABLES_STREAMACCESS,
91 ANA_TABLES_STREAMTIDX,
92 ANA_TABLES_SEQ_HISTORY,
95 ANA_TABLES_SFIDACCESS,
105 ANA_SG_GCL_GS_CONFIG,
106 ANA_SG_GCL_TI_CONFIG,
114 ANA_PORT_VCAP_S1_KEY_CFG,
115 ANA_PORT_VCAP_S2_CFG,
116 ANA_PORT_PCP_DEI_MAP,
117 ANA_PORT_CPU_FWD_CFG,
118 ANA_PORT_CPU_FWD_BPDU_CFG,
119 ANA_PORT_CPU_FWD_GARP_CFG,
120 ANA_PORT_CPU_FWD_CCM_CFG,
124 ANA_PORT_PTP_DLY1_CFG,
125 ANA_PORT_PTP_DLY2_CFG,
139 ANA_VCAP_RNG_TYPE_CFG,
140 ANA_VCAP_RNG_VAL_CFG,
155 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
167 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
168 QSYS_SWITCH_PORT_MODE,
180 QSYS_TIMED_FRAME_ENTRY,
183 QSYS_TFRM_TIMER_CFG_1,
184 QSYS_TFRM_TIMER_CFG_2,
185 QSYS_TFRM_TIMER_CFG_3,
186 QSYS_TFRM_TIMER_CFG_4,
187 QSYS_TFRM_TIMER_CFG_5,
188 QSYS_TFRM_TIMER_CFG_6,
189 QSYS_TFRM_TIMER_CFG_7,
190 QSYS_TFRM_TIMER_CFG_8,
218 QSYS_TAS_PARAM_CFG_CTRL,
220 QSYS_PARAM_CFG_REG_1,
221 QSYS_PARAM_CFG_REG_2,
222 QSYS_PARAM_CFG_REG_3,
223 QSYS_PARAM_CFG_REG_4,
224 QSYS_PARAM_CFG_REG_5,
227 QSYS_PARAM_STATUS_REG_1,
228 QSYS_PARAM_STATUS_REG_2,
229 QSYS_PARAM_STATUS_REG_3,
230 QSYS_PARAM_STATUS_REG_4,
231 QSYS_PARAM_STATUS_REG_5,
232 QSYS_PARAM_STATUS_REG_6,
233 QSYS_PARAM_STATUS_REG_7,
234 QSYS_PARAM_STATUS_REG_8,
235 QSYS_PARAM_STATUS_REG_9,
236 QSYS_GCL_STATUS_REG_1,
237 QSYS_GCL_STATUS_REG_2,
238 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
242 REW_PCP_DEI_QOS_MAP_CFG,
246 REW_DSCP_REMAP_DP1_CFG,
251 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
252 SYS_COUNT_RX_UNICAST,
253 SYS_COUNT_RX_MULTICAST,
254 SYS_COUNT_RX_BROADCAST,
256 SYS_COUNT_RX_FRAGMENTS,
257 SYS_COUNT_RX_JABBERS,
258 SYS_COUNT_RX_CRC_ALIGN_ERRS,
259 SYS_COUNT_RX_SYM_ERRS,
262 SYS_COUNT_RX_128_255,
263 SYS_COUNT_RX_256_1023,
264 SYS_COUNT_RX_1024_1526,
265 SYS_COUNT_RX_1527_MAX,
267 SYS_COUNT_RX_CONTROL,
269 SYS_COUNT_RX_CLASSIFIED_DROPS,
271 SYS_COUNT_TX_UNICAST,
272 SYS_COUNT_TX_MULTICAST,
273 SYS_COUNT_TX_BROADCAST,
274 SYS_COUNT_TX_COLLISION,
279 SYS_COUNT_TX_128_511,
280 SYS_COUNT_TX_512_1023,
281 SYS_COUNT_TX_1024_1526,
282 SYS_COUNT_TX_1527_MAX,
293 SYS_REW_MAC_HIGH_CFG,
295 SYS_TIMESTAMP_OFFSET,
317 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
324 PTP_PIN_CFG = PTP << TARGET_OFFSET,
330 PTP_CLK_CFG_ADJ_FREQ,
331 GCB_SOFT_RST = GCB << TARGET_OFFSET,
334 enum ocelot_regfield {
335 ANA_ADVLEARN_VLAN_CHK,
336 ANA_ADVLEARN_LEARN_MIRROR,
337 ANA_ANEVENTS_FLOOD_DISCARD,
338 ANA_ANEVENTS_MSTI_DROP,
339 ANA_ANEVENTS_ACLKILL,
340 ANA_ANEVENTS_ACLUSED,
341 ANA_ANEVENTS_AUTOAGE,
342 ANA_ANEVENTS_VS2TTL1,
343 ANA_ANEVENTS_STORM_DROP,
344 ANA_ANEVENTS_LEARN_DROP,
345 ANA_ANEVENTS_AGED_ENTRY,
346 ANA_ANEVENTS_CPU_LEARN_FAILED,
347 ANA_ANEVENTS_AUTO_LEARN_FAILED,
348 ANA_ANEVENTS_LEARN_REMOVE,
349 ANA_ANEVENTS_AUTO_LEARNED,
350 ANA_ANEVENTS_AUTO_MOVED,
351 ANA_ANEVENTS_DROPPED,
352 ANA_ANEVENTS_CLASSIFIED_DROP,
353 ANA_ANEVENTS_CLASSIFIED_COPY,
354 ANA_ANEVENTS_VLAN_DISCARD,
355 ANA_ANEVENTS_FWD_DISCARD,
356 ANA_ANEVENTS_MULTICAST_FLOOD,
357 ANA_ANEVENTS_UNICAST_FLOOD,
358 ANA_ANEVENTS_DEST_KNOWN,
359 ANA_ANEVENTS_BUCKET3_MATCH,
360 ANA_ANEVENTS_BUCKET2_MATCH,
361 ANA_ANEVENTS_BUCKET1_MATCH,
362 ANA_ANEVENTS_BUCKET0_MATCH,
363 ANA_ANEVENTS_CPU_OPERATION,
364 ANA_ANEVENTS_DMAC_LOOKUP,
365 ANA_ANEVENTS_SMAC_LOOKUP,
366 ANA_ANEVENTS_SEQ_GEN_ERR_0,
367 ANA_ANEVENTS_SEQ_GEN_ERR_1,
368 ANA_TABLES_MACACCESS_B_DOM,
369 ANA_TABLES_MACTINDX_BUCKET,
370 ANA_TABLES_MACTINDX_M_INDEX,
371 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
372 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
373 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
374 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
375 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
376 SYS_RESET_CFG_CORE_ENA,
377 SYS_RESET_CFG_MEM_ENA,
378 SYS_RESET_CFG_MEM_INIT,
379 GCB_SOFT_RST_SWC_RST,
383 enum ocelot_clk_pins {
390 struct ocelot_stat_layout {
392 char name[ETH_GSTRING_LEN];
395 enum ocelot_tag_prefix {
396 OCELOT_TAG_PREFIX_DISABLED = 0,
397 OCELOT_TAG_PREFIX_NONE,
398 OCELOT_TAG_PREFIX_SHORT,
399 OCELOT_TAG_PREFIX_LONG,
405 void (*pcs_init)(struct ocelot *ocelot, int port);
406 int (*reset)(struct ocelot *ocelot);
410 struct ocelot *ocelot;
414 /* Ingress default VLAN (pvid) */
417 /* Egress default VLAN (vid) */
421 struct sk_buff_head tx_skbs;
424 phy_interface_t phy_mode;
430 const struct ocelot_ops *ops;
431 struct regmap *targets[TARGET_MAX];
432 struct regmap_field *regfields[REGFIELD_MAX];
433 const u32 *const *map;
434 const struct ocelot_stat_layout *stats_layout;
435 unsigned int num_stats;
439 struct net_device *hw_bridge_dev;
443 struct ocelot_port **ports;
445 u8 base_mac[ETH_ALEN];
447 /* Keep track of the vlan port masks */
448 u32 vlan_mask[VLAN_N_VID];
456 struct list_head multicast;
458 /* Workqueue to check statistics for overflow with its lock */
459 struct mutex stats_lock;
461 struct delayed_work stats_work;
462 struct workqueue_struct *stats_queue;
465 struct ptp_clock *ptp_clock;
466 struct ptp_clock_info ptp_info;
467 struct hwtstamp_config hwtstamp_config;
468 /* Protects the PTP interface state */
469 struct mutex ptp_lock;
470 /* Protects the PTP clock */
471 spinlock_t ptp_clock_lock;
473 void (*port_pcs_init)(struct ocelot_port *port);
476 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
477 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
478 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
479 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
481 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
482 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
483 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
484 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
486 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
487 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
488 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
489 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
492 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
493 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
494 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
495 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
496 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
499 /* Hardware initialization */
500 int ocelot_regfields_init(struct ocelot *ocelot,
501 const struct reg_field *const regfields);
502 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
503 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
504 enum ocelot_tag_prefix injection,
505 enum ocelot_tag_prefix extraction);
506 int ocelot_init(struct ocelot *ocelot);
507 void ocelot_deinit(struct ocelot *ocelot);
508 void ocelot_init_port(struct ocelot *ocelot, int port);
511 void ocelot_port_enable(struct ocelot *ocelot, int port,
512 struct phy_device *phy);
513 void ocelot_port_disable(struct ocelot *ocelot, int port);
514 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
515 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
516 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
517 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
518 struct ethtool_ts_info *info);
519 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
520 void ocelot_adjust_link(struct ocelot *ocelot, int port,
521 struct phy_device *phydev);
522 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
524 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
525 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
526 struct net_device *bridge);
527 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
528 struct net_device *bridge);
529 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
530 dsa_fdb_dump_cb_t *cb, void *data);
531 int ocelot_fdb_add(struct ocelot *ocelot, int port,
532 const unsigned char *addr, u16 vid, bool vlan_aware);
533 int ocelot_fdb_del(struct ocelot *ocelot, int port,
534 const unsigned char *addr, u16 vid);
535 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
537 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
538 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
539 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
540 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
541 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
542 struct sk_buff *skb);
543 void ocelot_get_txtstamp(struct ocelot *ocelot);