4 * Copyright Red Hat, Inc. 2013-2014
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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38 #ifndef VIRTIO_GPU_HW_H
39 #define VIRTIO_GPU_HW_H
41 #include <linux/types.h>
44 * VIRTIO_GPU_CMD_CTX_*
47 #define VIRTIO_GPU_F_VIRGL 0
50 * VIRTIO_GPU_CMD_GET_EDID
52 #define VIRTIO_GPU_F_EDID 1
54 enum virtio_gpu_ctrl_type {
55 VIRTIO_GPU_UNDEFINED = 0,
58 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
59 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
60 VIRTIO_GPU_CMD_RESOURCE_UNREF,
61 VIRTIO_GPU_CMD_SET_SCANOUT,
62 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
63 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
64 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
65 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
66 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
67 VIRTIO_GPU_CMD_GET_CAPSET,
68 VIRTIO_GPU_CMD_GET_EDID,
71 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
72 VIRTIO_GPU_CMD_CTX_DESTROY,
73 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
74 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
75 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
76 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
77 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
78 VIRTIO_GPU_CMD_SUBMIT_3D,
81 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
82 VIRTIO_GPU_CMD_MOVE_CURSOR,
84 /* success responses */
85 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
86 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
87 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
88 VIRTIO_GPU_RESP_OK_CAPSET,
89 VIRTIO_GPU_RESP_OK_EDID,
92 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
93 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
94 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
95 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
96 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
97 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
100 #define VIRTIO_GPU_FLAG_FENCE (1 << 0)
102 struct virtio_gpu_ctrl_hdr {
110 /* data passed in the cursor vq */
112 struct virtio_gpu_cursor_pos {
119 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
120 struct virtio_gpu_update_cursor {
121 struct virtio_gpu_ctrl_hdr hdr;
122 struct virtio_gpu_cursor_pos pos; /* update & move */
123 __le32 resource_id; /* update only */
124 __le32 hot_x; /* update only */
125 __le32 hot_y; /* update only */
129 /* data passed in the control vq, 2d related */
131 struct virtio_gpu_rect {
138 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
139 struct virtio_gpu_resource_unref {
140 struct virtio_gpu_ctrl_hdr hdr;
145 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
146 struct virtio_gpu_resource_create_2d {
147 struct virtio_gpu_ctrl_hdr hdr;
154 /* VIRTIO_GPU_CMD_SET_SCANOUT */
155 struct virtio_gpu_set_scanout {
156 struct virtio_gpu_ctrl_hdr hdr;
157 struct virtio_gpu_rect r;
162 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
163 struct virtio_gpu_resource_flush {
164 struct virtio_gpu_ctrl_hdr hdr;
165 struct virtio_gpu_rect r;
170 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
171 struct virtio_gpu_transfer_to_host_2d {
172 struct virtio_gpu_ctrl_hdr hdr;
173 struct virtio_gpu_rect r;
179 struct virtio_gpu_mem_entry {
185 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
186 struct virtio_gpu_resource_attach_backing {
187 struct virtio_gpu_ctrl_hdr hdr;
192 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
193 struct virtio_gpu_resource_detach_backing {
194 struct virtio_gpu_ctrl_hdr hdr;
199 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
200 #define VIRTIO_GPU_MAX_SCANOUTS 16
201 struct virtio_gpu_resp_display_info {
202 struct virtio_gpu_ctrl_hdr hdr;
203 struct virtio_gpu_display_one {
204 struct virtio_gpu_rect r;
207 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
210 /* data passed in the control vq, 3d related */
212 struct virtio_gpu_box {
217 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
218 struct virtio_gpu_transfer_host_3d {
219 struct virtio_gpu_ctrl_hdr hdr;
220 struct virtio_gpu_box box;
228 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
229 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
230 struct virtio_gpu_resource_create_3d {
231 struct virtio_gpu_ctrl_hdr hdr;
246 /* VIRTIO_GPU_CMD_CTX_CREATE */
247 struct virtio_gpu_ctx_create {
248 struct virtio_gpu_ctrl_hdr hdr;
254 /* VIRTIO_GPU_CMD_CTX_DESTROY */
255 struct virtio_gpu_ctx_destroy {
256 struct virtio_gpu_ctrl_hdr hdr;
259 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
260 struct virtio_gpu_ctx_resource {
261 struct virtio_gpu_ctrl_hdr hdr;
266 /* VIRTIO_GPU_CMD_SUBMIT_3D */
267 struct virtio_gpu_cmd_submit {
268 struct virtio_gpu_ctrl_hdr hdr;
273 #define VIRTIO_GPU_CAPSET_VIRGL 1
274 #define VIRTIO_GPU_CAPSET_VIRGL2 2
276 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
277 struct virtio_gpu_get_capset_info {
278 struct virtio_gpu_ctrl_hdr hdr;
283 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
284 struct virtio_gpu_resp_capset_info {
285 struct virtio_gpu_ctrl_hdr hdr;
287 __le32 capset_max_version;
288 __le32 capset_max_size;
292 /* VIRTIO_GPU_CMD_GET_CAPSET */
293 struct virtio_gpu_get_capset {
294 struct virtio_gpu_ctrl_hdr hdr;
296 __le32 capset_version;
299 /* VIRTIO_GPU_RESP_OK_CAPSET */
300 struct virtio_gpu_resp_capset {
301 struct virtio_gpu_ctrl_hdr hdr;
305 /* VIRTIO_GPU_CMD_GET_EDID */
306 struct virtio_gpu_cmd_get_edid {
307 struct virtio_gpu_ctrl_hdr hdr;
312 /* VIRTIO_GPU_RESP_OK_EDID */
313 struct virtio_gpu_resp_edid {
314 struct virtio_gpu_ctrl_hdr hdr;
320 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
322 struct virtio_gpu_config {
329 /* simple formats for fbcon/X use */
330 enum virtio_gpu_formats {
331 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
332 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
333 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
334 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
336 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
337 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
339 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
340 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,