2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef MLX5_ABI_USER_H
34 #define MLX5_ABI_USER_H
36 #include <linux/types.h>
37 #include <linux/if_ether.h> /* For ETH_ALEN. */
40 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
41 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
45 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
49 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
52 /* Increment this value if any changes that break userspace ABI
53 * compatibility are made.
55 #define MLX5_IB_UVERBS_ABI_VERSION 1
57 /* Make sure that all structs defined in this file remain laid out so
58 * that they pack the same way on 32-bit and 64-bit architectures (to
59 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
60 * In particular do not use pointer types -- pass pointers in __u64
64 struct mlx5_ib_alloc_ucontext_req {
65 __u32 total_num_bfregs;
66 __u32 num_low_latency_bfregs;
70 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
73 struct mlx5_ib_alloc_ucontext_req_v2 {
74 __u32 total_num_bfregs;
75 __u32 num_low_latency_bfregs;
85 enum mlx5_ib_alloc_ucontext_resp_mask {
86 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
89 enum mlx5_user_cmds_supp_uhw {
90 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
91 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
94 /* The eth_min_inline response value is set to off-by-one vs the FW
95 * returned value to allow user-space to deal with older kernels.
97 enum mlx5_user_inline_mode {
98 MLX5_USER_INLINE_MODE_NA,
99 MLX5_USER_INLINE_MODE_NONE,
100 MLX5_USER_INLINE_MODE_L2,
101 MLX5_USER_INLINE_MODE_IP,
102 MLX5_USER_INLINE_MODE_TCP_UDP,
105 struct mlx5_ib_alloc_ucontext_resp {
109 __u32 cache_line_size;
110 __u16 max_sq_desc_sz;
111 __u16 max_rq_desc_sz;
112 __u32 max_send_wqebb;
114 __u32 max_srq_recv_wr;
118 __u32 response_length;
123 __u64 hca_core_clock_offset;
125 __u32 num_uars_per_page;
128 struct mlx5_ib_alloc_pd_resp {
132 struct mlx5_ib_tso_caps {
133 __u32 max_tso; /* Maximum tso payload size in bytes */
135 /* Corresponding bit will be set if qp type from
136 * 'enum ib_qp_type' is supported, e.g.
137 * supported_qpts |= 1 << IB_QPT_UD
139 __u32 supported_qpts;
142 struct mlx5_ib_rss_caps {
143 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
144 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
148 enum mlx5_ib_cqe_comp_res_format {
149 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
150 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
151 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
154 struct mlx5_ib_cqe_comp_caps {
156 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
159 struct mlx5_packet_pacing_caps {
160 __u32 qp_rate_limit_min;
161 __u32 qp_rate_limit_max; /* In kpbs */
163 /* Corresponding bit will be set if qp type from
164 * 'enum ib_qp_type' is supported, e.g.
165 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
167 __u32 supported_qpts;
171 struct mlx5_ib_query_device_resp {
173 __u32 response_length;
174 struct mlx5_ib_tso_caps tso_caps;
175 struct mlx5_ib_rss_caps rss_caps;
176 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
177 struct mlx5_packet_pacing_caps packet_pacing_caps;
178 __u32 mlx5_ib_support_multi_pkt_send_wqes;
182 struct mlx5_ib_create_cq {
187 __u8 cqe_comp_res_format;
188 __u16 reserved; /* explicit padding (optional on i386) */
191 struct mlx5_ib_create_cq_resp {
196 struct mlx5_ib_resize_cq {
203 struct mlx5_ib_create_srq {
207 __u32 reserved0; /* explicit padding (optional on i386) */
212 struct mlx5_ib_create_srq_resp {
217 struct mlx5_ib_create_qp {
229 /* RX Hash function flags */
230 enum mlx5_rx_hash_function_flags {
231 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
235 * RX Hash flags, these flags allows to set which incoming packet's field should
236 * participates in RX Hash. Each flag represent certain packet's field,
237 * when the flag is set the field that is represented by the flag will
238 * participate in RX Hash calculation.
239 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
240 * and *TCP and *UDP flags can't be enabled together on the same QP.
242 enum mlx5_rx_hash_fields {
243 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
244 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
245 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
246 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
247 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
248 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
249 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
250 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
253 struct mlx5_ib_create_qp_rss {
254 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
255 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
256 __u8 rx_key_len; /* valid only for Toeplitz */
258 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
263 struct mlx5_ib_create_qp_resp {
267 struct mlx5_ib_alloc_mw {
274 struct mlx5_ib_create_wq {
285 struct mlx5_ib_create_ah_resp {
286 __u32 response_length;
291 struct mlx5_ib_create_wq_resp {
292 __u32 response_length;
296 struct mlx5_ib_create_rwq_ind_tbl_resp {
297 __u32 response_length;
301 struct mlx5_ib_modify_wq {
305 #endif /* MLX5_ABI_USER_H */