1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Christoph Hellwig.
5 * DMA operations that map physical memory directly without using an IOMMU.
7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h>
10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h>
12 #include <linux/dma-contiguous.h>
13 #include <linux/dma-noncoherent.h>
14 #include <linux/pfn.h>
15 #include <linux/set_memory.h>
16 #include <linux/swiotlb.h>
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
20 * some use it for entirely different regions:
22 #ifndef ARCH_ZONE_DMA_BITS
23 #define ARCH_ZONE_DMA_BITS 24
26 static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
29 dev_err_once(dev, "DMA map on device without dma_mask\n");
30 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
32 "overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
33 &dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
38 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
41 if (force_dma_unencrypted(dev))
42 return __phys_to_dma(dev, phys);
43 return phys_to_dma(dev, phys);
46 u64 dma_direct_get_required_mask(struct device *dev)
48 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT);
50 if (dev->bus_dma_mask && dev->bus_dma_mask < max_dma)
51 max_dma = dev->bus_dma_mask;
53 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
56 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
59 if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
60 dma_mask = dev->bus_dma_mask;
62 if (force_dma_unencrypted(dev))
63 *phys_mask = __dma_to_phys(dev, dma_mask);
65 *phys_mask = dma_to_phys(dev, dma_mask);
68 * Optimistically try the zone that the physical address mask falls
69 * into first. If that returns memory that isn't actually addressable
70 * we will fallback to the next lower zone and try again.
72 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
75 if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
77 if (*phys_mask <= DMA_BIT_MASK(32))
82 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
84 return phys_to_dma_direct(dev, phys) + size - 1 <=
85 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
88 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
89 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
91 struct page *page = NULL;
94 if (attrs & DMA_ATTR_NO_WARN)
97 /* we always manually zero the memory once we are done: */
99 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
102 page = dma_alloc_contiguous(dev, size, gfp);
103 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
104 dma_free_contiguous(dev, page, size);
107 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
108 phys_mask < DMA_BIT_MASK(64) &&
109 !(gfp & (GFP_DMA32 | GFP_DMA))) {
114 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
115 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
123 void *dma_direct_alloc_pages(struct device *dev, size_t size,
124 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
129 page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
133 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
134 /* remove any dirty cache lines on the kernel alias */
135 if (!PageHighMem(page))
136 arch_dma_prep_coherent(page, size);
137 /* return the page pointer as the opaque cookie */
141 if (PageHighMem(page)) {
143 * Depending on the cma= arguments and per-arch setup
144 * dma_alloc_contiguous could return highmem pages.
145 * Without remapping there is no way to return them here,
146 * so log an error and fail.
148 dev_info(dev, "Rejecting highmem page from CMA.\n");
149 __dma_direct_free_pages(dev, size, page);
153 ret = page_address(page);
154 if (force_dma_unencrypted(dev)) {
155 set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
156 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
158 *dma_handle = phys_to_dma(dev, page_to_phys(page));
160 memset(ret, 0, size);
162 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
163 dma_alloc_need_uncached(dev, attrs)) {
164 arch_dma_prep_coherent(page, size);
165 ret = uncached_kernel_address(ret);
171 void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page)
173 dma_free_contiguous(dev, page, size);
176 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
177 dma_addr_t dma_addr, unsigned long attrs)
179 unsigned int page_order = get_order(size);
181 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
182 /* cpu_addr is a struct page cookie, not a kernel address */
183 __dma_direct_free_pages(dev, size, cpu_addr);
187 if (force_dma_unencrypted(dev))
188 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
190 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
191 dma_alloc_need_uncached(dev, attrs))
192 cpu_addr = cached_kernel_address(cpu_addr);
193 __dma_direct_free_pages(dev, size, virt_to_page(cpu_addr));
196 void *dma_direct_alloc(struct device *dev, size_t size,
197 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
199 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
200 dma_alloc_need_uncached(dev, attrs))
201 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
202 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
205 void dma_direct_free(struct device *dev, size_t size,
206 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
208 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
209 dma_alloc_need_uncached(dev, attrs))
210 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
212 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
215 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
216 defined(CONFIG_SWIOTLB)
217 void dma_direct_sync_single_for_device(struct device *dev,
218 dma_addr_t addr, size_t size, enum dma_data_direction dir)
220 phys_addr_t paddr = dma_to_phys(dev, addr);
222 if (unlikely(is_swiotlb_buffer(paddr)))
223 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
225 if (!dev_is_dma_coherent(dev))
226 arch_sync_dma_for_device(dev, paddr, size, dir);
228 EXPORT_SYMBOL(dma_direct_sync_single_for_device);
230 void dma_direct_sync_sg_for_device(struct device *dev,
231 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
233 struct scatterlist *sg;
236 for_each_sg(sgl, sg, nents, i) {
237 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
239 if (unlikely(is_swiotlb_buffer(paddr)))
240 swiotlb_tbl_sync_single(dev, paddr, sg->length,
241 dir, SYNC_FOR_DEVICE);
243 if (!dev_is_dma_coherent(dev))
244 arch_sync_dma_for_device(dev, paddr, sg->length,
248 EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
251 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
252 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
253 defined(CONFIG_SWIOTLB)
254 void dma_direct_sync_single_for_cpu(struct device *dev,
255 dma_addr_t addr, size_t size, enum dma_data_direction dir)
257 phys_addr_t paddr = dma_to_phys(dev, addr);
259 if (!dev_is_dma_coherent(dev)) {
260 arch_sync_dma_for_cpu(dev, paddr, size, dir);
261 arch_sync_dma_for_cpu_all(dev);
264 if (unlikely(is_swiotlb_buffer(paddr)))
265 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
267 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
269 void dma_direct_sync_sg_for_cpu(struct device *dev,
270 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
272 struct scatterlist *sg;
275 for_each_sg(sgl, sg, nents, i) {
276 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
278 if (!dev_is_dma_coherent(dev))
279 arch_sync_dma_for_cpu(dev, paddr, sg->length, dir);
281 if (unlikely(is_swiotlb_buffer(paddr)))
282 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
286 if (!dev_is_dma_coherent(dev))
287 arch_sync_dma_for_cpu_all(dev);
289 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
291 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
292 size_t size, enum dma_data_direction dir, unsigned long attrs)
294 phys_addr_t phys = dma_to_phys(dev, addr);
296 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
297 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
299 if (unlikely(is_swiotlb_buffer(phys)))
300 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
302 EXPORT_SYMBOL(dma_direct_unmap_page);
304 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
305 int nents, enum dma_data_direction dir, unsigned long attrs)
307 struct scatterlist *sg;
310 for_each_sg(sgl, sg, nents, i)
311 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
314 EXPORT_SYMBOL(dma_direct_unmap_sg);
317 static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
320 return swiotlb_force != SWIOTLB_FORCE &&
321 dma_capable(dev, dma_addr, size);
324 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
325 unsigned long offset, size_t size, enum dma_data_direction dir,
328 phys_addr_t phys = page_to_phys(page) + offset;
329 dma_addr_t dma_addr = phys_to_dma(dev, phys);
331 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) &&
332 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) {
333 report_addr(dev, dma_addr, size);
334 return DMA_MAPPING_ERROR;
337 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
338 arch_sync_dma_for_device(dev, phys, size, dir);
341 EXPORT_SYMBOL(dma_direct_map_page);
343 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
344 enum dma_data_direction dir, unsigned long attrs)
347 struct scatterlist *sg;
349 for_each_sg(sgl, sg, nents, i) {
350 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
351 sg->offset, sg->length, dir, attrs);
352 if (sg->dma_address == DMA_MAPPING_ERROR)
354 sg_dma_len(sg) = sg->length;
360 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
363 EXPORT_SYMBOL(dma_direct_map_sg);
365 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
366 size_t size, enum dma_data_direction dir, unsigned long attrs)
368 dma_addr_t dma_addr = paddr;
370 if (unlikely(!dma_direct_possible(dev, dma_addr, size))) {
371 report_addr(dev, dma_addr, size);
372 return DMA_MAPPING_ERROR;
377 EXPORT_SYMBOL(dma_direct_map_resource);
380 * Because 32-bit DMA masks are so common we expect every architecture to be
381 * able to satisfy them - either by not supporting more physical memory, or by
382 * providing a ZONE_DMA32. If neither is the case, the architecture needs to
383 * use an IOMMU instead of the direct mapping.
385 int dma_direct_supported(struct device *dev, u64 mask)
389 if (IS_ENABLED(CONFIG_ZONE_DMA))
390 min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
392 min_mask = DMA_BIT_MASK(32);
394 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
397 * This check needs to be against the actual bit mask value, so
398 * use __phys_to_dma() here so that the SME encryption mask isn't
401 return mask >= __phys_to_dma(dev, min_mask);
404 size_t dma_direct_max_mapping_size(struct device *dev)
406 /* If SWIOTLB is active, use its maximum mapping size */
407 if (is_swiotlb_active() &&
408 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
409 return swiotlb_max_mapping_size(dev);