1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediated virtual PCI serial host device driver
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 * Author: Neo Jia <cjia@nvidia.com>
7 * Kirti Wankhede <kwankhede@nvidia.com>
9 * Sample driver that creates mdev device that simulates serial port over PCI
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/kernel.h>
18 #include <linux/poll.h>
19 #include <linux/slab.h>
20 #include <linux/cdev.h>
21 #include <linux/sched.h>
22 #include <linux/wait.h>
23 #include <linux/uuid.h>
24 #include <linux/vfio.h>
25 #include <linux/iommu.h>
26 #include <linux/sysfs.h>
27 #include <linux/ctype.h>
28 #include <linux/file.h>
29 #include <linux/mdev.h>
30 #include <linux/pci.h>
31 #include <linux/serial.h>
32 #include <uapi/linux/serial_reg.h>
33 #include <linux/eventfd.h>
38 #define VERSION_STRING "0.1"
39 #define DRIVER_AUTHOR "NVIDIA Corporation"
41 #define MTTY_CLASS_NAME "mtty"
43 #define MTTY_NAME "mtty"
45 #define MTTY_STRING_LEN 16
47 #define MTTY_CONFIG_SPACE_SIZE 0xff
48 #define MTTY_IO_BAR_SIZE 0x8
49 #define MTTY_MMIO_BAR_SIZE 0x100000
51 #define STORE_LE16(addr, val) (*(u16 *)addr = val)
52 #define STORE_LE32(addr, val) (*(u32 *)addr = val)
54 #define MAX_FIFO_SIZE 16
56 #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
58 #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
60 #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
61 #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
62 ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
63 #define MTTY_VFIO_PCI_OFFSET_MASK \
64 (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
71 static struct mtty_dev {
73 struct class *vd_class;
79 struct mdev_region_info {
86 #if defined(DEBUG_REGS)
87 static const char *wr_reg[] = {
98 static const char *rd_reg[] = {
110 /* loop back buffer */
112 u8 fifo[MAX_FIFO_SIZE];
118 u8 uart_reg[8]; /* 8 registers */
119 struct rxtx rxtx; /* loop back buffer */
123 u8 fcr; /* FIFO control register */
125 u8 intr_trigger_level; /* interrupt trigger level */
128 /* State of each mdev device */
131 struct eventfd_ctx *intx_evtfd;
132 struct eventfd_ctx *msi_evtfd;
135 struct mutex ops_lock;
136 struct mdev_device *mdev;
137 struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
138 u32 bar_mask[VFIO_PCI_NUM_REGIONS];
139 struct list_head next;
140 struct serial_port s[2];
141 struct mutex rxtx_lock;
142 struct vfio_device_info dev_info;
146 static struct mutex mdev_list_lock;
147 static struct list_head mdev_devices_list;
149 static const struct file_operations vd_fops = {
150 .owner = THIS_MODULE,
153 /* function prototypes */
155 static int mtty_trigger_interrupt(struct mdev_state *mdev_state);
157 /* Helper functions */
159 static void dump_buffer(u8 *buf, uint32_t count)
164 pr_info("Buffer:\n");
165 for (i = 0; i < count; i++) {
166 pr_info("%2x ", *(buf + i));
167 if ((i + 1) % 16 == 0)
173 static void mtty_create_config_space(struct mdev_state *mdev_state)
176 STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
178 /* Control: I/O+, Mem-, BusMaster- */
179 STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
181 /* Status: capabilities list absent */
182 STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
185 mdev_state->vconfig[0x8] = 0x10;
187 /* programming interface class : 16550-compatible serial controller */
188 mdev_state->vconfig[0x9] = 0x02;
191 mdev_state->vconfig[0xa] = 0x00;
193 /* Base class : Simple Communication controllers */
194 mdev_state->vconfig[0xb] = 0x07;
196 /* base address registers */
198 STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
199 mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
201 if (mdev_state->nr_ports == 2) {
203 STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
204 mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
208 STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
210 mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
211 mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
213 /* Vendor specific data */
214 mdev_state->vconfig[0x40] = 0x23;
215 mdev_state->vconfig[0x43] = 0x80;
216 mdev_state->vconfig[0x44] = 0x23;
217 mdev_state->vconfig[0x48] = 0x23;
218 mdev_state->vconfig[0x4c] = 0x23;
220 mdev_state->vconfig[0x60] = 0x50;
221 mdev_state->vconfig[0x61] = 0x43;
222 mdev_state->vconfig[0x62] = 0x49;
223 mdev_state->vconfig[0x63] = 0x20;
224 mdev_state->vconfig[0x64] = 0x53;
225 mdev_state->vconfig[0x65] = 0x65;
226 mdev_state->vconfig[0x66] = 0x72;
227 mdev_state->vconfig[0x67] = 0x69;
228 mdev_state->vconfig[0x68] = 0x61;
229 mdev_state->vconfig[0x69] = 0x6c;
230 mdev_state->vconfig[0x6a] = 0x2f;
231 mdev_state->vconfig[0x6b] = 0x55;
232 mdev_state->vconfig[0x6c] = 0x41;
233 mdev_state->vconfig[0x6d] = 0x52;
234 mdev_state->vconfig[0x6e] = 0x54;
237 static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
240 u32 cfg_addr, bar_mask, bar_index = 0;
243 case 0x04: /* device control */
244 case 0x06: /* device status */
247 case 0x3c: /* interrupt line */
248 mdev_state->vconfig[0x3c] = buf[0];
252 * Interrupt Pin is hardwired to INTA.
253 * This field is write protected by hardware
256 case 0x10: /* BAR0 */
257 case 0x14: /* BAR1 */
260 else if (offset == 0x14)
263 if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
264 STORE_LE32(&mdev_state->vconfig[offset], 0);
268 cfg_addr = *(u32 *)buf;
269 pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
271 if (cfg_addr == 0xffffffff) {
272 bar_mask = mdev_state->bar_mask[bar_index];
273 cfg_addr = (cfg_addr & bar_mask);
276 cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
277 STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
279 case 0x18: /* BAR2 */
280 case 0x1c: /* BAR3 */
281 case 0x20: /* BAR4 */
282 STORE_LE32(&mdev_state->vconfig[offset], 0);
285 pr_info("PCI config write @0x%x of %d bytes not handled\n",
291 static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
292 u16 offset, u8 *buf, u32 count)
296 /* Handle data written by guest */
299 /* if DLAB set, data is LSB of divisor */
300 if (mdev_state->s[index].dlab) {
301 mdev_state->s[index].divisor |= data;
305 mutex_lock(&mdev_state->rxtx_lock);
307 /* save in TX buffer */
308 if (mdev_state->s[index].rxtx.count <
309 mdev_state->s[index].max_fifo_size) {
310 mdev_state->s[index].rxtx.fifo[
311 mdev_state->s[index].rxtx.head] = data;
312 mdev_state->s[index].rxtx.count++;
313 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
314 mdev_state->s[index].overrun = false;
317 * Trigger interrupt if receive data interrupt is
318 * enabled and fifo reached trigger level
320 if ((mdev_state->s[index].uart_reg[UART_IER] &
322 (mdev_state->s[index].rxtx.count ==
323 mdev_state->s[index].intr_trigger_level)) {
324 /* trigger interrupt */
325 #if defined(DEBUG_INTR)
326 pr_err("Serial port %d: Fifo level trigger\n",
329 mtty_trigger_interrupt(mdev_state);
332 #if defined(DEBUG_INTR)
333 pr_err("Serial port %d: Buffer Overflow\n", index);
335 mdev_state->s[index].overrun = true;
338 * Trigger interrupt if receiver line status interrupt
341 if (mdev_state->s[index].uart_reg[UART_IER] &
343 mtty_trigger_interrupt(mdev_state);
345 mutex_unlock(&mdev_state->rxtx_lock);
349 /* if DLAB set, data is MSB of divisor */
350 if (mdev_state->s[index].dlab)
351 mdev_state->s[index].divisor |= (u16)data << 8;
353 mdev_state->s[index].uart_reg[offset] = data;
354 mutex_lock(&mdev_state->rxtx_lock);
355 if ((data & UART_IER_THRI) &&
356 (mdev_state->s[index].rxtx.head ==
357 mdev_state->s[index].rxtx.tail)) {
358 #if defined(DEBUG_INTR)
359 pr_err("Serial port %d: IER_THRI write\n",
362 mtty_trigger_interrupt(mdev_state);
365 mutex_unlock(&mdev_state->rxtx_lock);
371 mdev_state->s[index].fcr = data;
373 mutex_lock(&mdev_state->rxtx_lock);
374 if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
375 /* clear loop back FIFO */
376 mdev_state->s[index].rxtx.count = 0;
377 mdev_state->s[index].rxtx.head = 0;
378 mdev_state->s[index].rxtx.tail = 0;
380 mutex_unlock(&mdev_state->rxtx_lock);
382 switch (data & UART_FCR_TRIGGER_MASK) {
383 case UART_FCR_TRIGGER_1:
384 mdev_state->s[index].intr_trigger_level = 1;
387 case UART_FCR_TRIGGER_4:
388 mdev_state->s[index].intr_trigger_level = 4;
391 case UART_FCR_TRIGGER_8:
392 mdev_state->s[index].intr_trigger_level = 8;
395 case UART_FCR_TRIGGER_14:
396 mdev_state->s[index].intr_trigger_level = 14;
401 * Set trigger level to 1 otherwise or implement timer with
402 * timeout of 4 characters and on expiring that timer set
403 * Recevice data timeout in IIR register
405 mdev_state->s[index].intr_trigger_level = 1;
406 if (data & UART_FCR_ENABLE_FIFO)
407 mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
409 mdev_state->s[index].max_fifo_size = 1;
410 mdev_state->s[index].intr_trigger_level = 1;
416 if (data & UART_LCR_DLAB) {
417 mdev_state->s[index].dlab = true;
418 mdev_state->s[index].divisor = 0;
420 mdev_state->s[index].dlab = false;
422 mdev_state->s[index].uart_reg[offset] = data;
426 mdev_state->s[index].uart_reg[offset] = data;
428 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
429 (data & UART_MCR_OUT2)) {
430 #if defined(DEBUG_INTR)
431 pr_err("Serial port %d: MCR_OUT2 write\n", index);
433 mtty_trigger_interrupt(mdev_state);
436 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
437 (data & (UART_MCR_RTS | UART_MCR_DTR))) {
438 #if defined(DEBUG_INTR)
439 pr_err("Serial port %d: MCR RTS/DTR write\n", index);
441 mtty_trigger_interrupt(mdev_state);
451 mdev_state->s[index].uart_reg[offset] = data;
459 static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
460 u16 offset, u8 *buf, u32 count)
462 /* Handle read requests by guest */
465 /* if DLAB set, data is LSB of divisor */
466 if (mdev_state->s[index].dlab) {
467 *buf = (u8)mdev_state->s[index].divisor;
471 mutex_lock(&mdev_state->rxtx_lock);
472 /* return data in tx buffer */
473 if (mdev_state->s[index].rxtx.head !=
474 mdev_state->s[index].rxtx.tail) {
475 *buf = mdev_state->s[index].rxtx.fifo[
476 mdev_state->s[index].rxtx.tail];
477 mdev_state->s[index].rxtx.count--;
478 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
481 if (mdev_state->s[index].rxtx.head ==
482 mdev_state->s[index].rxtx.tail) {
484 * Trigger interrupt if tx buffer empty interrupt is
485 * enabled and fifo is empty
487 #if defined(DEBUG_INTR)
488 pr_err("Serial port %d: Buffer Empty\n", index);
490 if (mdev_state->s[index].uart_reg[UART_IER] &
492 mtty_trigger_interrupt(mdev_state);
494 mutex_unlock(&mdev_state->rxtx_lock);
499 if (mdev_state->s[index].dlab) {
500 *buf = (u8)(mdev_state->s[index].divisor >> 8);
503 *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
508 u8 ier = mdev_state->s[index].uart_reg[UART_IER];
511 mutex_lock(&mdev_state->rxtx_lock);
512 /* Interrupt priority 1: Parity, overrun, framing or break */
513 if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
514 *buf |= UART_IIR_RLSI;
516 /* Interrupt priority 2: Fifo trigger level reached */
517 if ((ier & UART_IER_RDI) &&
518 (mdev_state->s[index].rxtx.count >=
519 mdev_state->s[index].intr_trigger_level))
520 *buf |= UART_IIR_RDI;
522 /* Interrupt priotiry 3: transmitter holding register empty */
523 if ((ier & UART_IER_THRI) &&
524 (mdev_state->s[index].rxtx.head ==
525 mdev_state->s[index].rxtx.tail))
526 *buf |= UART_IIR_THRI;
528 /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
529 if ((ier & UART_IER_MSI) &&
530 (mdev_state->s[index].uart_reg[UART_MCR] &
531 (UART_MCR_RTS | UART_MCR_DTR)))
532 *buf |= UART_IIR_MSI;
534 /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
536 *buf = UART_IIR_NO_INT;
538 /* set bit 6 & 7 to be 16550 compatible */
540 mutex_unlock(&mdev_state->rxtx_lock);
546 *buf = mdev_state->s[index].uart_reg[offset];
553 mutex_lock(&mdev_state->rxtx_lock);
554 /* atleast one char in FIFO */
555 if (mdev_state->s[index].rxtx.head !=
556 mdev_state->s[index].rxtx.tail)
559 /* if FIFO overrun */
560 if (mdev_state->s[index].overrun)
563 /* transmit FIFO empty and tramsitter empty */
564 if (mdev_state->s[index].rxtx.head ==
565 mdev_state->s[index].rxtx.tail)
566 lsr |= UART_LSR_TEMT | UART_LSR_THRE;
568 mutex_unlock(&mdev_state->rxtx_lock);
573 *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
575 mutex_lock(&mdev_state->rxtx_lock);
576 /* if AFE is 1 and FIFO have space, set CTS bit */
577 if (mdev_state->s[index].uart_reg[UART_MCR] &
579 if (mdev_state->s[index].rxtx.count <
580 mdev_state->s[index].max_fifo_size)
581 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
583 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
584 mutex_unlock(&mdev_state->rxtx_lock);
589 *buf = mdev_state->s[index].uart_reg[offset];
597 static void mdev_read_base(struct mdev_state *mdev_state)
600 u32 start_lo, start_hi;
603 pos = PCI_BASE_ADDRESS_0;
605 for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
607 if (!mdev_state->region_info[index].size)
610 start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
611 PCI_BASE_ADDRESS_MEM_MASK;
612 mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
613 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
616 case PCI_BASE_ADDRESS_MEM_TYPE_64:
617 start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
620 case PCI_BASE_ADDRESS_MEM_TYPE_32:
621 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
622 /* 1M mem BAR treated as 32-bit BAR */
624 /* mem unknown type treated as 32-bit BAR */
629 mdev_state->region_info[index].start = ((u64)start_hi << 32) |
634 static ssize_t mdev_access(struct mdev_device *mdev, u8 *buf, size_t count,
635 loff_t pos, bool is_write)
637 struct mdev_state *mdev_state;
645 mdev_state = mdev_get_drvdata(mdev);
647 pr_err("%s mdev_state not found\n", __func__);
651 mutex_lock(&mdev_state->ops_lock);
653 index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
654 offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
656 case VFIO_PCI_CONFIG_REGION_INDEX:
659 pr_info("%s: PCI config space %s at offset 0x%llx\n",
660 __func__, is_write ? "write" : "read", offset);
663 dump_buffer(buf, count);
664 handle_pci_cfg_write(mdev_state, offset, buf, count);
666 memcpy(buf, (mdev_state->vconfig + offset), count);
667 dump_buffer(buf, count);
672 case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
673 if (!mdev_state->region_info[index].start)
674 mdev_read_base(mdev_state);
677 dump_buffer(buf, count);
679 #if defined(DEBUG_REGS)
680 pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
681 __func__, index, offset, wr_reg[offset],
682 *buf, mdev_state->s[index].dlab);
684 handle_bar_write(index, mdev_state, offset, buf, count);
686 handle_bar_read(index, mdev_state, offset, buf, count);
687 dump_buffer(buf, count);
689 #if defined(DEBUG_REGS)
690 pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
691 __func__, index, offset, rd_reg[offset],
692 *buf, mdev_state->s[index].dlab);
706 mutex_unlock(&mdev_state->ops_lock);
711 static int mtty_create(struct kobject *kobj, struct mdev_device *mdev)
713 struct mdev_state *mdev_state;
714 char name[MTTY_STRING_LEN];
720 for (i = 0; i < 2; i++) {
721 snprintf(name, MTTY_STRING_LEN, "%s-%d",
722 dev_driver_string(mdev_parent_dev(mdev)), i + 1);
723 if (!strcmp(kobj->name, name)) {
732 mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
733 if (mdev_state == NULL)
736 mdev_state->nr_ports = nr_ports;
737 mdev_state->irq_index = -1;
738 mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
739 mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
740 mutex_init(&mdev_state->rxtx_lock);
741 mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
743 if (mdev_state->vconfig == NULL) {
748 mutex_init(&mdev_state->ops_lock);
749 mdev_state->mdev = mdev;
750 mdev_set_drvdata(mdev, mdev_state);
752 mtty_create_config_space(mdev_state);
754 mutex_lock(&mdev_list_lock);
755 list_add(&mdev_state->next, &mdev_devices_list);
756 mutex_unlock(&mdev_list_lock);
761 static int mtty_remove(struct mdev_device *mdev)
763 struct mdev_state *mds, *tmp_mds;
764 struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
767 mutex_lock(&mdev_list_lock);
768 list_for_each_entry_safe(mds, tmp_mds, &mdev_devices_list, next) {
769 if (mdev_state == mds) {
770 list_del(&mdev_state->next);
771 mdev_set_drvdata(mdev, NULL);
772 kfree(mdev_state->vconfig);
778 mutex_unlock(&mdev_list_lock);
783 static int mtty_reset(struct mdev_device *mdev)
785 struct mdev_state *mdev_state;
790 mdev_state = mdev_get_drvdata(mdev);
794 pr_info("%s: called\n", __func__);
799 static ssize_t mtty_read(struct mdev_device *mdev, char __user *buf,
800 size_t count, loff_t *ppos)
802 unsigned int done = 0;
808 if (count >= 4 && !(*ppos % 4)) {
811 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
816 if (copy_to_user(buf, &val, sizeof(val)))
820 } else if (count >= 2 && !(*ppos % 2)) {
823 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
828 if (copy_to_user(buf, &val, sizeof(val)))
835 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
840 if (copy_to_user(buf, &val, sizeof(val)))
858 static ssize_t mtty_write(struct mdev_device *mdev, const char __user *buf,
859 size_t count, loff_t *ppos)
861 unsigned int done = 0;
867 if (count >= 4 && !(*ppos % 4)) {
870 if (copy_from_user(&val, buf, sizeof(val)))
873 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
879 } else if (count >= 2 && !(*ppos % 2)) {
882 if (copy_from_user(&val, buf, sizeof(val)))
885 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
894 if (copy_from_user(&val, buf, sizeof(val)))
897 ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
915 static int mtty_set_irqs(struct mdev_device *mdev, uint32_t flags,
916 unsigned int index, unsigned int start,
917 unsigned int count, void *data)
920 struct mdev_state *mdev_state;
925 mdev_state = mdev_get_drvdata(mdev);
929 mutex_lock(&mdev_state->ops_lock);
931 case VFIO_PCI_INTX_IRQ_INDEX:
932 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
933 case VFIO_IRQ_SET_ACTION_MASK:
934 case VFIO_IRQ_SET_ACTION_UNMASK:
936 case VFIO_IRQ_SET_ACTION_TRIGGER:
938 if (flags & VFIO_IRQ_SET_DATA_NONE) {
939 pr_info("%s: disable INTx\n", __func__);
940 if (mdev_state->intx_evtfd)
941 eventfd_ctx_put(mdev_state->intx_evtfd);
945 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
946 int fd = *(int *)data;
949 struct eventfd_ctx *evt;
951 evt = eventfd_ctx_fdget(fd);
956 mdev_state->intx_evtfd = evt;
957 mdev_state->irq_fd = fd;
958 mdev_state->irq_index = index;
966 case VFIO_PCI_MSI_IRQ_INDEX:
967 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
968 case VFIO_IRQ_SET_ACTION_MASK:
969 case VFIO_IRQ_SET_ACTION_UNMASK:
971 case VFIO_IRQ_SET_ACTION_TRIGGER:
972 if (flags & VFIO_IRQ_SET_DATA_NONE) {
973 if (mdev_state->msi_evtfd)
974 eventfd_ctx_put(mdev_state->msi_evtfd);
975 pr_info("%s: disable MSI\n", __func__);
976 mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
979 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
980 int fd = *(int *)data;
981 struct eventfd_ctx *evt;
986 if (mdev_state->msi_evtfd)
989 evt = eventfd_ctx_fdget(fd);
994 mdev_state->msi_evtfd = evt;
995 mdev_state->irq_fd = fd;
996 mdev_state->irq_index = index;
1001 case VFIO_PCI_MSIX_IRQ_INDEX:
1002 pr_info("%s: MSIX_IRQ\n", __func__);
1004 case VFIO_PCI_ERR_IRQ_INDEX:
1005 pr_info("%s: ERR_IRQ\n", __func__);
1007 case VFIO_PCI_REQ_IRQ_INDEX:
1008 pr_info("%s: REQ_IRQ\n", __func__);
1012 mutex_unlock(&mdev_state->ops_lock);
1016 static int mtty_trigger_interrupt(struct mdev_state *mdev_state)
1020 if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
1021 (!mdev_state->msi_evtfd))
1023 else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
1024 (!mdev_state->intx_evtfd)) {
1025 pr_info("%s: Intr eventfd not found\n", __func__);
1029 if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
1030 ret = eventfd_signal(mdev_state->msi_evtfd, 1);
1032 ret = eventfd_signal(mdev_state->intx_evtfd, 1);
1034 #if defined(DEBUG_INTR)
1035 pr_info("Intx triggered\n");
1038 pr_err("%s: eventfd signal failed (%d)\n", __func__, ret);
1043 static int mtty_get_region_info(struct mdev_device *mdev,
1044 struct vfio_region_info *region_info,
1045 u16 *cap_type_id, void **cap_type)
1047 unsigned int size = 0;
1048 struct mdev_state *mdev_state;
1054 mdev_state = mdev_get_drvdata(mdev);
1058 bar_index = region_info->index;
1059 if (bar_index >= VFIO_PCI_NUM_REGIONS)
1062 mutex_lock(&mdev_state->ops_lock);
1064 switch (bar_index) {
1065 case VFIO_PCI_CONFIG_REGION_INDEX:
1066 size = MTTY_CONFIG_SPACE_SIZE;
1068 case VFIO_PCI_BAR0_REGION_INDEX:
1069 size = MTTY_IO_BAR_SIZE;
1071 case VFIO_PCI_BAR1_REGION_INDEX:
1072 if (mdev_state->nr_ports == 2)
1073 size = MTTY_IO_BAR_SIZE;
1080 mdev_state->region_info[bar_index].size = size;
1081 mdev_state->region_info[bar_index].vfio_offset =
1082 MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1084 region_info->size = size;
1085 region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1086 region_info->flags = VFIO_REGION_INFO_FLAG_READ |
1087 VFIO_REGION_INFO_FLAG_WRITE;
1088 mutex_unlock(&mdev_state->ops_lock);
1092 static int mtty_get_irq_info(struct mdev_device *mdev,
1093 struct vfio_irq_info *irq_info)
1095 switch (irq_info->index) {
1096 case VFIO_PCI_INTX_IRQ_INDEX:
1097 case VFIO_PCI_MSI_IRQ_INDEX:
1098 case VFIO_PCI_REQ_IRQ_INDEX:
1105 irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
1106 irq_info->count = 1;
1108 if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
1109 irq_info->flags |= (VFIO_IRQ_INFO_MASKABLE |
1110 VFIO_IRQ_INFO_AUTOMASKED);
1112 irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
1117 static int mtty_get_device_info(struct mdev_device *mdev,
1118 struct vfio_device_info *dev_info)
1120 dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
1121 dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
1122 dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
1127 static long mtty_ioctl(struct mdev_device *mdev, unsigned int cmd,
1131 unsigned long minsz;
1132 struct mdev_state *mdev_state;
1137 mdev_state = mdev_get_drvdata(mdev);
1142 case VFIO_DEVICE_GET_INFO:
1144 struct vfio_device_info info;
1146 minsz = offsetofend(struct vfio_device_info, num_irqs);
1148 if (copy_from_user(&info, (void __user *)arg, minsz))
1151 if (info.argsz < minsz)
1154 ret = mtty_get_device_info(mdev, &info);
1158 memcpy(&mdev_state->dev_info, &info, sizeof(info));
1160 if (copy_to_user((void __user *)arg, &info, minsz))
1165 case VFIO_DEVICE_GET_REGION_INFO:
1167 struct vfio_region_info info;
1168 u16 cap_type_id = 0;
1169 void *cap_type = NULL;
1171 minsz = offsetofend(struct vfio_region_info, offset);
1173 if (copy_from_user(&info, (void __user *)arg, minsz))
1176 if (info.argsz < minsz)
1179 ret = mtty_get_region_info(mdev, &info, &cap_type_id,
1184 if (copy_to_user((void __user *)arg, &info, minsz))
1190 case VFIO_DEVICE_GET_IRQ_INFO:
1192 struct vfio_irq_info info;
1194 minsz = offsetofend(struct vfio_irq_info, count);
1196 if (copy_from_user(&info, (void __user *)arg, minsz))
1199 if ((info.argsz < minsz) ||
1200 (info.index >= mdev_state->dev_info.num_irqs))
1203 ret = mtty_get_irq_info(mdev, &info);
1207 if (copy_to_user((void __user *)arg, &info, minsz))
1212 case VFIO_DEVICE_SET_IRQS:
1214 struct vfio_irq_set hdr;
1215 u8 *data = NULL, *ptr = NULL;
1216 size_t data_size = 0;
1218 minsz = offsetofend(struct vfio_irq_set, count);
1220 if (copy_from_user(&hdr, (void __user *)arg, minsz))
1223 ret = vfio_set_irqs_validate_and_prepare(&hdr,
1224 mdev_state->dev_info.num_irqs,
1231 ptr = data = memdup_user((void __user *)(arg + minsz),
1234 return PTR_ERR(data);
1237 ret = mtty_set_irqs(mdev, hdr.flags, hdr.index, hdr.start,
1243 case VFIO_DEVICE_RESET:
1244 return mtty_reset(mdev);
1249 static int mtty_open(struct mdev_device *mdev)
1251 pr_info("%s\n", __func__);
1255 static void mtty_close(struct mdev_device *mdev)
1257 pr_info("%s\n", __func__);
1261 sample_mtty_dev_show(struct device *dev, struct device_attribute *attr,
1264 return sprintf(buf, "This is phy device\n");
1267 static DEVICE_ATTR_RO(sample_mtty_dev);
1269 static struct attribute *mtty_dev_attrs[] = {
1270 &dev_attr_sample_mtty_dev.attr,
1274 static const struct attribute_group mtty_dev_group = {
1276 .attrs = mtty_dev_attrs,
1279 static const struct attribute_group *mtty_dev_groups[] = {
1285 sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
1288 if (mdev_from_dev(dev))
1289 return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
1291 return sprintf(buf, "\n");
1294 static DEVICE_ATTR_RO(sample_mdev_dev);
1296 static struct attribute *mdev_dev_attrs[] = {
1297 &dev_attr_sample_mdev_dev.attr,
1301 static const struct attribute_group mdev_dev_group = {
1303 .attrs = mdev_dev_attrs,
1306 static const struct attribute_group *mdev_dev_groups[] = {
1312 name_show(struct kobject *kobj, struct device *dev, char *buf)
1314 char name[MTTY_STRING_LEN];
1316 const char *name_str[2] = {"Single port serial", "Dual port serial"};
1318 for (i = 0; i < 2; i++) {
1319 snprintf(name, MTTY_STRING_LEN, "%s-%d",
1320 dev_driver_string(dev), i + 1);
1321 if (!strcmp(kobj->name, name))
1322 return sprintf(buf, "%s\n", name_str[i]);
1328 static MDEV_TYPE_ATTR_RO(name);
1331 available_instances_show(struct kobject *kobj, struct device *dev, char *buf)
1333 char name[MTTY_STRING_LEN];
1335 struct mdev_state *mds;
1336 int ports = 0, used = 0;
1338 for (i = 0; i < 2; i++) {
1339 snprintf(name, MTTY_STRING_LEN, "%s-%d",
1340 dev_driver_string(dev), i + 1);
1341 if (!strcmp(kobj->name, name)) {
1350 list_for_each_entry(mds, &mdev_devices_list, next)
1351 used += mds->nr_ports;
1353 return sprintf(buf, "%d\n", (MAX_MTTYS - used)/ports);
1356 static MDEV_TYPE_ATTR_RO(available_instances);
1359 static ssize_t device_api_show(struct kobject *kobj, struct device *dev,
1362 return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
1365 static MDEV_TYPE_ATTR_RO(device_api);
1367 static struct attribute *mdev_types_attrs[] = {
1368 &mdev_type_attr_name.attr,
1369 &mdev_type_attr_device_api.attr,
1370 &mdev_type_attr_available_instances.attr,
1374 static struct attribute_group mdev_type_group1 = {
1376 .attrs = mdev_types_attrs,
1379 static struct attribute_group mdev_type_group2 = {
1381 .attrs = mdev_types_attrs,
1384 static struct attribute_group *mdev_type_groups[] = {
1390 static const struct mdev_parent_ops mdev_fops = {
1391 .owner = THIS_MODULE,
1392 .dev_attr_groups = mtty_dev_groups,
1393 .mdev_attr_groups = mdev_dev_groups,
1394 .supported_type_groups = mdev_type_groups,
1395 .create = mtty_create,
1396 .remove = mtty_remove,
1398 .release = mtty_close,
1400 .write = mtty_write,
1401 .ioctl = mtty_ioctl,
1404 static void mtty_device_release(struct device *dev)
1406 dev_dbg(dev, "mtty: released\n");
1409 static int __init mtty_dev_init(void)
1413 pr_info("mtty_dev: %s\n", __func__);
1415 memset(&mtty_dev, 0, sizeof(mtty_dev));
1417 idr_init(&mtty_dev.vd_idr);
1419 ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK + 1,
1423 pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
1427 cdev_init(&mtty_dev.vd_cdev, &vd_fops);
1428 cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK + 1);
1430 pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
1432 mtty_dev.vd_class = class_create(THIS_MODULE, MTTY_CLASS_NAME);
1434 if (IS_ERR(mtty_dev.vd_class)) {
1435 pr_err("Error: failed to register mtty_dev class\n");
1436 ret = PTR_ERR(mtty_dev.vd_class);
1440 mtty_dev.dev.class = mtty_dev.vd_class;
1441 mtty_dev.dev.release = mtty_device_release;
1442 dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
1444 ret = device_register(&mtty_dev.dev);
1448 ret = mdev_register_device(&mtty_dev.dev, &mdev_fops);
1452 mutex_init(&mdev_list_lock);
1453 INIT_LIST_HEAD(&mdev_devices_list);
1459 device_unregister(&mtty_dev.dev);
1461 class_destroy(mtty_dev.vd_class);
1464 cdev_del(&mtty_dev.vd_cdev);
1465 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
1471 static void __exit mtty_dev_exit(void)
1473 mtty_dev.dev.bus = NULL;
1474 mdev_unregister_device(&mtty_dev.dev);
1476 device_unregister(&mtty_dev.dev);
1477 idr_destroy(&mtty_dev.vd_idr);
1478 cdev_del(&mtty_dev.vd_cdev);
1479 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
1480 class_destroy(mtty_dev.vd_class);
1481 mtty_dev.vd_class = NULL;
1482 pr_info("mtty_dev: Unloaded!\n");
1485 module_init(mtty_dev_init)
1486 module_exit(mtty_dev_exit)
1488 MODULE_LICENSE("GPL v2");
1489 MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
1490 MODULE_VERSION(VERSION_STRING);
1491 MODULE_AUTHOR(DRIVER_AUTHOR);