sound/drivers/ml403-ac97cr.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ALSA driver for Xilinx ML403 AC97 Controller Reference
   4  *   IP: opb_ac97_controller_ref_v1_00_a (EDK 8.1i)
   5  *   IP: opb_ac97_controller_ref_v1_00_a (EDK 9.1i)
   6  *
   7  *  Copyright (c) by 2007  Joachim Foerster <JOFT@gmx.de>
   8  */
   9
  10 /* Some notes / status of this driver:
  11  *
  12  * - Don't wonder about some strange implementations of things - especially the
  13  * (heavy) shadowing of codec registers, with which I tried to reduce read
  14  * accesses to a minimum, because after a variable amount of accesses, the AC97
  15  * controller doesn't raise the register access finished bit anymore ...
  16  *
  17  * - Playback support seems to be pretty stable - no issues here.
  18  * - Capture support "works" now, too. Overruns don't happen any longer so often.
  19  *   But there might still be some ...
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/interrupt.h>
  31
  32 /* HZ */
  33 #include <linux/param.h>
  34 /* jiffies, time_*() */
  35 #include <linux/jiffies.h>
  36 /* schedule_timeout*() */
  37 #include <linux/sched.h>
  38 /* spin_lock*() */
  39 #include <linux/spinlock.h>
  40 /* struct mutex, mutex_init(), mutex_*lock() */
  41 #include <linux/mutex.h>
  42
  43 /* snd_printk(), snd_printd() */
  44 #include <sound/core.h>
  45 #include <sound/pcm.h>
  46 #include <sound/pcm_params.h>
  47 #include <sound/initval.h>
  48 #include <sound/ac97_codec.h>
  49
  50 #include "pcm-indirect2.h"
  51
  52
  53 #define SND_ML403_AC97CR_DRIVER "ml403-ac97cr"
  54
  55 MODULE_AUTHOR("Joachim Foerster <JOFT@gmx.de>");
  56 MODULE_DESCRIPTION("Xilinx ML403 AC97 Controller Reference");
  57 MODULE_LICENSE("GPL");
  58 MODULE_SUPPORTED_DEVICE("{{Xilinx,ML403 AC97 Controller Reference}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  62 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE;
  63
  64 module_param_array(index, int, NULL, 0444);
  65 MODULE_PARM_DESC(index, "Index value for ML403 AC97 Controller Reference.");
  66 module_param_array(id, charp, NULL, 0444);
  67 MODULE_PARM_DESC(id, "ID string for ML403 AC97 Controller Reference.");
  68 module_param_array(enable, bool, NULL, 0444);
  69 MODULE_PARM_DESC(enable, "Enable this ML403 AC97 Controller Reference.");
  70
  71 /* Special feature options */
  72 /*#define CODEC_WRITE_CHECK_RAF*/ /* don't return after a write to a codec
  73                                    * register, while RAF bit is not set
  74                                    */
  75 /* Debug options for code which may be removed completely in a final version */
  76 #ifdef CONFIG_SND_DEBUG
  77 /*#define CODEC_STAT*/            /* turn on some minimal "statistics"
  78                                    * about codec register usage
  79                                    */
  80 #define SND_PCM_INDIRECT2_STAT    /* turn on some "statistics" about the
  81                                    * process of copying bytes from the
  82                                    * intermediate buffer to the hardware
  83                                    * fifo and the other way round
  84                                    */
  85 #endif
  86
  87 /* Definition of a "level/facility dependent" printk(); may be removed
  88  * completely in a final version
  89  */
  90 #undef PDEBUG
  91 #ifdef CONFIG_SND_DEBUG
  92 /* "facilities" for PDEBUG */
  93 #define UNKNOWN       (1<<0)
  94 #define CODEC_SUCCESS (1<<1)
  95 #define CODEC_FAKE    (1<<2)
  96 #define INIT_INFO     (1<<3)
  97 #define INIT_FAILURE  (1<<4)
  98 #define WORK_INFO     (1<<5)
  99 #define WORK_FAILURE  (1<<6)
 100
 101 #define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE)
 102
 103 #define PDEBUG(fac, fmt, args...) do { \
 104                 if (fac & PDEBUG_FACILITIES) \
 105                         snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \
 106                                    fmt, ##args); \
 107         } while (0)
 108 #else
 109 #define PDEBUG(fac, fmt, args...) /* nothing */
 110 #endif
 111
 112
 113
 114 /* Defines for "waits"/timeouts (portions of HZ=250 on arch/ppc by default) */
 115 #define CODEC_TIMEOUT_ON_INIT       5   /* timeout for checking for codec
 116                                          * readiness (after insmod)
 117                                          */
 118 #ifndef CODEC_WRITE_CHECK_RAF
 119 #define CODEC_WAIT_AFTER_WRITE    100   /* general, static wait after a write
 120                                          * access to a codec register, may be
 121                                          * 0 to completely remove wait
 122                                          */
 123 #else
 124 #define CODEC_TIMEOUT_AFTER_WRITE   5   /* timeout after a write access to a
 125                                          * codec register, if RAF bit is used
 126                                          */
 127 #endif
 128 #define CODEC_TIMEOUT_AFTER_READ    5   /* timeout after a read access to a
 129                                          * codec register (checking RAF bit)
 130                                          */
 131
 132 /* Infrastructure for codec register shadowing */
 133 #define LM4550_REG_OK        (1<<0)   /* register exists */
 134 #define LM4550_REG_DONEREAD  (1<<1)   /* read register once, value should be
 135                                        * the same currently in the register
 136                                        */
 137 #define LM4550_REG_NOSAVE    (1<<2)   /* values written to this register will
 138                                        * not be saved in the register
 139                                        */
 140 #define LM4550_REG_NOSHADOW  (1<<3)   /* don't do register shadowing, use plain
 141                                        * hardware access
 142                                        */
 143 #define LM4550_REG_READONLY  (1<<4)   /* register is read only */
 144 #define LM4550_REG_FAKEPROBE (1<<5)   /* fake write _and_ read actions during
 145                                        * probe() correctly
 146                                        */
 147 #define LM4550_REG_FAKEREAD  (1<<6)   /* fake read access, always return
 148                                        * default value
 149                                        */
 150 #define LM4550_REG_ALLFAKE   (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE)
 151
 152 struct lm4550_reg {
 153         u16 value;
 154         u16 flag;
 155         u16 wmask;
 156         u16 def;
 157 };
 158
 159 struct lm4550_reg lm4550_regfile[64] = {
 160         [AC97_RESET / 2]              = {.flag = LM4550_REG_OK \
 161                                                 | LM4550_REG_NOSAVE \
 162                                                 | LM4550_REG_FAKEREAD,
 163                                          .def = 0x0D50},
 164         [AC97_MASTER / 2]             = {.flag = LM4550_REG_OK
 165                                                 | LM4550_REG_FAKEPROBE,
 166                                          .wmask = 0x9F1F,
 167                                          .def = 0x8000},
 168         [AC97_HEADPHONE / 2]          = {.flag = LM4550_REG_OK \
 169                                                 | LM4550_REG_FAKEPROBE,
 170                                          .wmask = 0x9F1F,
 171                                          .def = 0x8000},
 172         [AC97_MASTER_MONO / 2]        = {.flag = LM4550_REG_OK \
 173                                                 | LM4550_REG_FAKEPROBE,
 174                                          .wmask = 0x801F,
 175                                          .def = 0x8000},
 176         [AC97_PC_BEEP / 2]            = {.flag = LM4550_REG_OK \
 177                                                 | LM4550_REG_FAKEPROBE,
 178                                          .wmask = 0x801E,
 179                                          .def = 0x0},
 180         [AC97_PHONE / 2]              = {.flag = LM4550_REG_OK \
 181                                                 | LM4550_REG_FAKEPROBE,
 182                                          .wmask = 0x801F,
 183                                          .def = 0x8008},
 184         [AC97_MIC / 2]                = {.flag = LM4550_REG_OK \
 185                                                 | LM4550_REG_FAKEPROBE,
 186                                          .wmask = 0x805F,
 187                                          .def = 0x8008},
 188         [AC97_LINE / 2]               = {.flag = LM4550_REG_OK \
 189                                                 | LM4550_REG_FAKEPROBE,
 190                                          .wmask = 0x9F1F,
 191                                          .def = 0x8808},
 192         [AC97_CD / 2]                 = {.flag = LM4550_REG_OK \
 193                                                 | LM4550_REG_FAKEPROBE,
 194                                          .wmask = 0x9F1F,
 195                                          .def = 0x8808},
 196         [AC97_VIDEO / 2]              = {.flag = LM4550_REG_OK \
 197                                                 | LM4550_REG_FAKEPROBE,
 198                                          .wmask = 0x9F1F,
 199                                          .def = 0x8808},
 200         [AC97_AUX / 2]                = {.flag = LM4550_REG_OK \
 201                                                 | LM4550_REG_FAKEPROBE,
 202                                          .wmask = 0x9F1F,
 203                                          .def = 0x8808},
 204         [AC97_PCM / 2]                = {.flag = LM4550_REG_OK \
 205                                                 | LM4550_REG_FAKEPROBE,
 206                                          .wmask = 0x9F1F,
 207                                          .def = 0x8008},
 208         [AC97_REC_SEL / 2]            = {.flag = LM4550_REG_OK \
 209                                                 | LM4550_REG_FAKEPROBE,
 210                                          .wmask = 0x707,
 211                                          .def = 0x0},
 212         [AC97_REC_GAIN / 2]           = {.flag = LM4550_REG_OK \
 213                                                 | LM4550_REG_FAKEPROBE,
 214                                          .wmask = 0x8F0F,
 215                                          .def = 0x8000},
 216         [AC97_GENERAL_PURPOSE / 2]    = {.flag = LM4550_REG_OK \
 217                                                 | LM4550_REG_FAKEPROBE,
 218                                          .def = 0x0,
 219                                          .wmask = 0xA380},
 220         [AC97_3D_CONTROL / 2]         = {.flag = LM4550_REG_OK \
 221                                                 | LM4550_REG_FAKEREAD \
 222                                                 | LM4550_REG_READONLY,
 223                                          .def = 0x0101},
 224         [AC97_POWERDOWN / 2]          = {.flag = LM4550_REG_OK \
 225                                                 | LM4550_REG_NOSHADOW \
 226                                                 | LM4550_REG_NOSAVE,
 227                                          .wmask = 0xFF00},
 228                                         /* may not write ones to
 229                                          * REF/ANL/DAC/ADC bits
 230                                          * FIXME: Is this ok?
 231                                          */
 232         [AC97_EXTENDED_ID / 2]        = {.flag = LM4550_REG_OK \
 233                                                 | LM4550_REG_FAKEREAD \
 234                                                 | LM4550_REG_READONLY,
 235                                          .def = 0x0201}, /* primary codec */
 236         [AC97_EXTENDED_STATUS / 2]    = {.flag = LM4550_REG_OK \
 237                                                 | LM4550_REG_NOSHADOW \
 238                                                 | LM4550_REG_NOSAVE,
 239                                          .wmask = 0x1},
 240         [AC97_PCM_FRONT_DAC_RATE / 2] = {.flag = LM4550_REG_OK \
 241                                                 | LM4550_REG_FAKEPROBE,
 242                                          .def = 0xBB80,
 243                                          .wmask = 0xFFFF},
 244         [AC97_PCM_LR_ADC_RATE / 2]    = {.flag = LM4550_REG_OK \
 245                                                 | LM4550_REG_FAKEPROBE,
 246                                          .def = 0xBB80,
 247                                          .wmask = 0xFFFF},
 248         [AC97_VENDOR_ID1 / 2]         = {.flag = LM4550_REG_OK \
 249                                                 | LM4550_REG_READONLY \
 250                                                 | LM4550_REG_FAKEREAD,
 251                                          .def = 0x4E53},
 252         [AC97_VENDOR_ID2 / 2]         = {.flag = LM4550_REG_OK \
 253                                                 | LM4550_REG_READONLY \
 254                                                 | LM4550_REG_FAKEREAD,
 255                                          .def = 0x4350}
 256 };
 257
 258 #define LM4550_RF_OK(reg)    (lm4550_regfile[reg / 2].flag & LM4550_REG_OK)
 259
 260 static void lm4550_regfile_init(void)
 261 {
 262         int i;
 263         for (i = 0; i < 64; i++)
 264                 if (lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE)
 265                         lm4550_regfile[i].value = lm4550_regfile[i].def;
 266 }
 267
 268 static void lm4550_regfile_write_values_after_init(struct snd_ac97 *ac97)
 269 {
 270         int i;
 271         for (i = 0; i < 64; i++)
 272                 if ((lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) &&
 273                     (lm4550_regfile[i].value != lm4550_regfile[i].def)) {
 274                         PDEBUG(CODEC_FAKE, "lm4550_regfile_write_values_after_"
 275                                "init(): reg=0x%x value=0x%x / %d is different "
 276                                "from def=0x%x / %d\n",
 277                                i, lm4550_regfile[i].value,
 278                                lm4550_regfile[i].value, lm4550_regfile[i].def,
 279                                lm4550_regfile[i].def);
 280                         snd_ac97_write(ac97, i * 2, lm4550_regfile[i].value);
 281                         lm4550_regfile[i].flag |= LM4550_REG_DONEREAD;
 282                 }
 283 }
 284
 285
 286 /* direct registers */
 287 #define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x)
 288
 289 #define CR_REG_PLAYFIFO         0x00
 290 #define   CR_PLAYDATA(a)        ((a) & 0xFFFF)
 291
 292 #define CR_REG_RECFIFO          0x04
 293 #define   CR_RECDATA(a)         ((a) & 0xFFFF)
 294
 295 #define CR_REG_STATUS           0x08
 296 #define   CR_RECOVER            (1<<7)
 297 #define   CR_PLAYUNDER          (1<<6)
 298 #define   CR_CODECREADY         (1<<5)
 299 #define   CR_RAF                (1<<4)
 300 #define   CR_RECEMPTY           (1<<3)
 301 #define   CR_RECFULL            (1<<2)
 302 #define   CR_PLAYHALF           (1<<1)
 303 #define   CR_PLAYFULL           (1<<0)
 304
 305 #define CR_REG_RESETFIFO        0x0C
 306 #define   CR_RECRESET           (1<<1)
 307 #define   CR_PLAYRESET          (1<<0)
 308
 309 #define CR_REG_CODEC_ADDR       0x10
 310 /* UG082 says:
 311  * #define   CR_CODEC_ADDR(a)  ((a) << 1)
 312  * #define   CR_CODEC_READ     (1<<0)
 313  * #define   CR_CODEC_WRITE    (0<<0)
 314  */
 315 /* RefDesign example says: */
 316 #define   CR_CODEC_ADDR(a)      ((a) << 0)
 317 #define   CR_CODEC_READ         (1<<7)
 318 #define   CR_CODEC_WRITE        (0<<7)
 319
 320 #define CR_REG_CODEC_DATAREAD   0x14
 321 #define   CR_CODEC_DATAREAD(v)  ((v) & 0xFFFF)
 322
 323 #define CR_REG_CODEC_DATAWRITE  0x18
 324 #define   CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF)
 325
 326 #define CR_FIFO_SIZE            32
 327
 328 struct snd_ml403_ac97cr {
 329         /* lock for access to (controller) registers */
 330         spinlock_t reg_lock;
 331         /* mutex for the whole sequence of accesses to (controller) registers
 332          * which affect codec registers
 333          */
 334         struct mutex cdc_mutex;
 335
 336         int irq; /* for playback */
 337         int enable_irq; /* for playback */
 338
 339         int capture_irq;
 340         int enable_capture_irq;
 341
 342         struct resource *res_port;
 343         void *port;
 344
 345         struct snd_ac97 *ac97;
 346         int ac97_fake;
 347 #ifdef CODEC_STAT
 348         int ac97_read;
 349         int ac97_write;
 350 #endif
 351
 352         struct platform_device *pfdev;
 353         struct snd_card *card;
 354         struct snd_pcm *pcm;
 355         struct snd_pcm_substream *playback_substream;
 356         struct snd_pcm_substream *capture_substream;
 357
 358         struct snd_pcm_indirect2 ind_rec; /* for playback */
 359         struct snd_pcm_indirect2 capture_ind2_rec;
 360 };
 361
 362 static const struct snd_pcm_hardware snd_ml403_ac97cr_playback = {
 363         .info =             (SNDRV_PCM_INFO_MMAP |
 364                              SNDRV_PCM_INFO_INTERLEAVED |
 365                              SNDRV_PCM_INFO_MMAP_VALID),
 366         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 367         .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 368                              SNDRV_PCM_RATE_8000_48000),
 369         .rate_min =         4000,
 370         .rate_max =         48000,
 371         .channels_min =     2,
 372         .channels_max =     2,
 373         .buffer_bytes_max = (128*1024),
 374         .period_bytes_min = CR_FIFO_SIZE/2,
 375         .period_bytes_max = (64*1024),
 376         .periods_min =      2,
 377         .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 378         .fifo_size =        0,
 379 };
 380
 381 static const struct snd_pcm_hardware snd_ml403_ac97cr_capture = {
 382         .info =             (SNDRV_PCM_INFO_MMAP |
 383                              SNDRV_PCM_INFO_INTERLEAVED |
 384                              SNDRV_PCM_INFO_MMAP_VALID),
 385         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 386         .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 387                              SNDRV_PCM_RATE_8000_48000),
 388         .rate_min =         4000,
 389         .rate_max =         48000,
 390         .channels_min =     2,
 391         .channels_max =     2,
 392         .buffer_bytes_max = (128*1024),
 393         .period_bytes_min = CR_FIFO_SIZE/2,
 394         .period_bytes_max = (64*1024),
 395         .periods_min =      2,
 396         .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 397         .fifo_size =        0,
 398 };
 399
 400 static size_t
 401 snd_ml403_ac97cr_playback_ind2_zero(struct snd_pcm_substream *substream,
 402                                     struct snd_pcm_indirect2 *rec)
 403 {
 404         struct snd_ml403_ac97cr *ml403_ac97cr;
 405         int copied_words = 0;
 406         u32 full = 0;
 407
 408         ml403_ac97cr = snd_pcm_substream_chip(substream);
 409
 410         spin_lock(&ml403_ac97cr->reg_lock);
 411         while ((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 412                         CR_PLAYFULL)) != CR_PLAYFULL) {
 413                 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 0);
 414                 copied_words++;
 415         }
 416         rec->hw_ready = 0;
 417         spin_unlock(&ml403_ac97cr->reg_lock);
 418
 419         return (size_t) (copied_words * 2);
 420 }
 421
 422 static size_t
 423 snd_ml403_ac97cr_playback_ind2_copy(struct snd_pcm_substream *substream,
 424                                     struct snd_pcm_indirect2 *rec,
 425                                     size_t bytes)
 426 {
 427         struct snd_ml403_ac97cr *ml403_ac97cr;
 428         u16 *src;
 429         int copied_words = 0;
 430         u32 full = 0;
 431
 432         ml403_ac97cr = snd_pcm_substream_chip(substream);
 433         src = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 434
 435         spin_lock(&ml403_ac97cr->reg_lock);
 436         while (((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 437                          CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) {
 438                 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO),
 439                          CR_PLAYDATA(src[copied_words]));
 440                 copied_words++;
 441                 bytes = bytes - 2;
 442         }
 443         if (full != CR_PLAYFULL)
 444                 rec->hw_ready = 1;
 445         else
 446                 rec->hw_ready = 0;
 447         spin_unlock(&ml403_ac97cr->reg_lock);
 448
 449         return (size_t) (copied_words * 2);
 450 }
 451
 452 static size_t
 453 snd_ml403_ac97cr_capture_ind2_null(struct snd_pcm_substream *substream,
 454                                    struct snd_pcm_indirect2 *rec)
 455 {
 456         struct snd_ml403_ac97cr *ml403_ac97cr;
 457         int copied_words = 0;
 458         u32 empty = 0;
 459
 460         ml403_ac97cr = snd_pcm_substream_chip(substream);
 461
 462         spin_lock(&ml403_ac97cr->reg_lock);
 463         while ((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 464                          CR_RECEMPTY)) != CR_RECEMPTY) {
 465                 volatile u32 trash;
 466
 467                 trash = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO)));
 468                 /* Hmmmm, really necessary? Don't want call to in_be32()
 469                  * to be optimised away!
 470                  */
 471                 trash++;
 472                 copied_words++;
 473         }
 474         rec->hw_ready = 0;
 475         spin_unlock(&ml403_ac97cr->reg_lock);
 476
 477         return (size_t) (copied_words * 2);
 478 }
 479
 480 static size_t
 481 snd_ml403_ac97cr_capture_ind2_copy(struct snd_pcm_substream *substream,
 482                                    struct snd_pcm_indirect2 *rec, size_t bytes)
 483 {
 484         struct snd_ml403_ac97cr *ml403_ac97cr;
 485         u16 *dst;
 486         int copied_words = 0;
 487         u32 empty = 0;
 488
 489         ml403_ac97cr = snd_pcm_substream_chip(substream);
 490         dst = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 491
 492         spin_lock(&ml403_ac97cr->reg_lock);
 493         while (((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 494                           CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) {
 495                 dst[copied_words] = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr,
 496                                                               RECFIFO)));
 497                 copied_words++;
 498                 bytes = bytes - 2;
 499         }
 500         if (empty != CR_RECEMPTY)
 501                 rec->hw_ready = 1;
 502         else
 503                 rec->hw_ready = 0;
 504         spin_unlock(&ml403_ac97cr->reg_lock);
 505
 506         return (size_t) (copied_words * 2);
 507 }
 508
 509 static snd_pcm_uframes_t
 510 snd_ml403_ac97cr_pcm_pointer(struct snd_pcm_substream *substream)
 511 {
 512         struct snd_ml403_ac97cr *ml403_ac97cr;
 513         struct snd_pcm_indirect2 *ind2_rec = NULL;
 514
 515         ml403_ac97cr = snd_pcm_substream_chip(substream);
 516
 517         if (substream == ml403_ac97cr->playback_substream)
 518                 ind2_rec = &ml403_ac97cr->ind_rec;
 519         if (substream == ml403_ac97cr->capture_substream)
 520                 ind2_rec = &ml403_ac97cr->capture_ind2_rec;
 521
 522         if (ind2_rec != NULL)
 523                 return snd_pcm_indirect2_pointer(substream, ind2_rec);
 524         return (snd_pcm_uframes_t) 0;
 525 }
 526
 527 static int
 528 snd_ml403_ac97cr_pcm_playback_trigger(struct snd_pcm_substream *substream,
 529                                       int cmd)
 530 {
 531         struct snd_ml403_ac97cr *ml403_ac97cr;
 532         int err = 0;
 533
 534         ml403_ac97cr = snd_pcm_substream_chip(substream);
 535
 536         switch (cmd) {
 537         case SNDRV_PCM_TRIGGER_START:
 538                 PDEBUG(WORK_INFO, "trigger(playback): START\n");
 539                 ml403_ac97cr->ind_rec.hw_ready = 1;
 540
 541                 /* clear play FIFO */
 542                 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_PLAYRESET);
 543
 544                 /* enable play irq */
 545                 ml403_ac97cr->enable_irq = 1;
 546                 enable_irq(ml403_ac97cr->irq);
 547                 break;
 548         case SNDRV_PCM_TRIGGER_STOP:
 549                 PDEBUG(WORK_INFO, "trigger(playback): STOP\n");
 550                 ml403_ac97cr->ind_rec.hw_ready = 0;
 551 #ifdef SND_PCM_INDIRECT2_STAT
 552                 snd_pcm_indirect2_stat(substream, &ml403_ac97cr->ind_rec);
 553 #endif
 554                 /* disable play irq */
 555                 disable_irq_nosync(ml403_ac97cr->irq);
 556                 ml403_ac97cr->enable_irq = 0;
 557                 break;
 558         default:
 559                 err = -EINVAL;
 560                 break;
 561         }
 562         PDEBUG(WORK_INFO, "trigger(playback): (done)\n");
 563         return err;
 564 }
 565
 566 static int
 567 snd_ml403_ac97cr_pcm_capture_trigger(struct snd_pcm_substream *substream,
 568                                       int cmd)
 569 {
 570         struct snd_ml403_ac97cr *ml403_ac97cr;
 571         int err = 0;
 572
 573         ml403_ac97cr = snd_pcm_substream_chip(substream);
 574
 575         switch (cmd) {
 576         case SNDRV_PCM_TRIGGER_START:
 577                 PDEBUG(WORK_INFO, "trigger(capture): START\n");
 578                 ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 579
 580                 /* clear record FIFO */
 581                 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_RECRESET);
 582
 583                 /* enable record irq */
 584                 ml403_ac97cr->enable_capture_irq = 1;
 585                 enable_irq(ml403_ac97cr->capture_irq);
 586                 break;
 587         case SNDRV_PCM_TRIGGER_STOP:
 588                 PDEBUG(WORK_INFO, "trigger(capture): STOP\n");
 589                 ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 590 #ifdef SND_PCM_INDIRECT2_STAT
 591                 snd_pcm_indirect2_stat(substream,
 592                                        &ml403_ac97cr->capture_ind2_rec);
 593 #endif
 594                 /* disable capture irq */
 595                 disable_irq_nosync(ml403_ac97cr->capture_irq);
 596                 ml403_ac97cr->enable_capture_irq = 0;
 597                 break;
 598         default:
 599                 err = -EINVAL;
 600                 break;
 601         }
 602         PDEBUG(WORK_INFO, "trigger(capture): (done)\n");
 603         return err;
 604 }
 605
 606 static int
 607 snd_ml403_ac97cr_pcm_playback_prepare(struct snd_pcm_substream *substream)
 608 {
 609         struct snd_ml403_ac97cr *ml403_ac97cr;
 610         struct snd_pcm_runtime *runtime;
 611
 612         ml403_ac97cr = snd_pcm_substream_chip(substream);
 613         runtime = substream->runtime;
 614
 615         PDEBUG(WORK_INFO,
 616                "prepare(): period_bytes=%d, minperiod_bytes=%d\n",
 617                snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 618
 619         /* set sampling rate */
 620         snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_FRONT_DAC_RATE,
 621                           runtime->rate);
 622         PDEBUG(WORK_INFO, "prepare(): rate=%d\n", runtime->rate);
 623
 624         /* init struct for intermediate buffer */
 625         memset(&ml403_ac97cr->ind_rec, 0,
 626                sizeof(struct snd_pcm_indirect2));
 627         ml403_ac97cr->ind_rec.hw_buffer_size = CR_FIFO_SIZE;
 628         ml403_ac97cr->ind_rec.sw_buffer_size =
 629                 snd_pcm_lib_buffer_bytes(substream);
 630         ml403_ac97cr->ind_rec.min_periods = -1;
 631         ml403_ac97cr->ind_rec.min_multiple =
 632                 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 633         PDEBUG(WORK_INFO, "prepare(): hw_buffer_size=%d, "
 634                "sw_buffer_size=%d, min_multiple=%d\n",
 635                CR_FIFO_SIZE, ml403_ac97cr->ind_rec.sw_buffer_size,
 636                ml403_ac97cr->ind_rec.min_multiple);
 637         return 0;
 638 }
 639
 640 static int
 641 snd_ml403_ac97cr_pcm_capture_prepare(struct snd_pcm_substream *substream)
 642 {
 643         struct snd_ml403_ac97cr *ml403_ac97cr;
 644         struct snd_pcm_runtime *runtime;
 645
 646         ml403_ac97cr = snd_pcm_substream_chip(substream);
 647         runtime = substream->runtime;
 648
 649         PDEBUG(WORK_INFO,
 650                "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n",
 651                snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 652
 653         /* set sampling rate */
 654         snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_LR_ADC_RATE,
 655                           runtime->rate);
 656         PDEBUG(WORK_INFO, "prepare(capture): rate=%d\n", runtime->rate);
 657
 658         /* init struct for intermediate buffer */
 659         memset(&ml403_ac97cr->capture_ind2_rec, 0,
 660                sizeof(struct snd_pcm_indirect2));
 661         ml403_ac97cr->capture_ind2_rec.hw_buffer_size = CR_FIFO_SIZE;
 662         ml403_ac97cr->capture_ind2_rec.sw_buffer_size =
 663                 snd_pcm_lib_buffer_bytes(substream);
 664         ml403_ac97cr->capture_ind2_rec.min_multiple =
 665                 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 666         PDEBUG(WORK_INFO, "prepare(capture): hw_buffer_size=%d, "
 667                "sw_buffer_size=%d, min_multiple=%d\n", CR_FIFO_SIZE,
 668                ml403_ac97cr->capture_ind2_rec.sw_buffer_size,
 669                ml403_ac97cr->capture_ind2_rec.min_multiple);
 670         return 0;
 671 }
 672
 673 static int snd_ml403_ac97cr_playback_open(struct snd_pcm_substream *substream)
 674 {
 675         struct snd_ml403_ac97cr *ml403_ac97cr;
 676         struct snd_pcm_runtime *runtime;
 677
 678         ml403_ac97cr = snd_pcm_substream_chip(substream);
 679         runtime = substream->runtime;
 680
 681         PDEBUG(WORK_INFO, "open(playback)\n");
 682         ml403_ac97cr->playback_substream = substream;
 683         runtime->hw = snd_ml403_ac97cr_playback;
 684
 685         snd_pcm_hw_constraint_step(runtime, 0,
 686                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 687                                    CR_FIFO_SIZE / 2);
 688         return 0;
 689 }
 690
 691 static int snd_ml403_ac97cr_capture_open(struct snd_pcm_substream *substream)
 692 {
 693         struct snd_ml403_ac97cr *ml403_ac97cr;
 694         struct snd_pcm_runtime *runtime;
 695
 696         ml403_ac97cr = snd_pcm_substream_chip(substream);
 697         runtime = substream->runtime;
 698
 699         PDEBUG(WORK_INFO, "open(capture)\n");
 700         ml403_ac97cr->capture_substream = substream;
 701         runtime->hw = snd_ml403_ac97cr_capture;
 702
 703         snd_pcm_hw_constraint_step(runtime, 0,
 704                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 705                                    CR_FIFO_SIZE / 2);
 706         return 0;
 707 }
 708
 709 static int snd_ml403_ac97cr_playback_close(struct snd_pcm_substream *substream)
 710 {
 711         struct snd_ml403_ac97cr *ml403_ac97cr;
 712
 713         ml403_ac97cr = snd_pcm_substream_chip(substream);
 714
 715         PDEBUG(WORK_INFO, "close(playback)\n");
 716         ml403_ac97cr->playback_substream = NULL;
 717         return 0;
 718 }
 719
 720 static int snd_ml403_ac97cr_capture_close(struct snd_pcm_substream *substream)
 721 {
 722         struct snd_ml403_ac97cr *ml403_ac97cr;
 723
 724         ml403_ac97cr = snd_pcm_substream_chip(substream);
 725
 726         PDEBUG(WORK_INFO, "close(capture)\n");
 727         ml403_ac97cr->capture_substream = NULL;
 728         return 0;
 729 }
 730
 731 static const struct snd_pcm_ops snd_ml403_ac97cr_playback_ops = {
 732         .open = snd_ml403_ac97cr_playback_open,
 733         .close = snd_ml403_ac97cr_playback_close,
 734         .prepare = snd_ml403_ac97cr_pcm_playback_prepare,
 735         .trigger = snd_ml403_ac97cr_pcm_playback_trigger,
 736         .pointer = snd_ml403_ac97cr_pcm_pointer,
 737 };
 738
 739 static const struct snd_pcm_ops snd_ml403_ac97cr_capture_ops = {
 740         .open = snd_ml403_ac97cr_capture_open,
 741         .close = snd_ml403_ac97cr_capture_close,
 742         .prepare = snd_ml403_ac97cr_pcm_capture_prepare,
 743         .trigger = snd_ml403_ac97cr_pcm_capture_trigger,
 744         .pointer = snd_ml403_ac97cr_pcm_pointer,
 745 };
 746
 747 static irqreturn_t snd_ml403_ac97cr_irq(int irq, void *dev_id)
 748 {
 749         struct snd_ml403_ac97cr *ml403_ac97cr;
 750         struct platform_device *pfdev;
 751         int cmp_irq;
 752
 753         ml403_ac97cr = (struct snd_ml403_ac97cr *)dev_id;
 754         if (ml403_ac97cr == NULL)
 755                 return IRQ_NONE;
 756
 757         pfdev = ml403_ac97cr->pfdev;
 758
 759         /* playback interrupt */
 760         cmp_irq = platform_get_irq(pfdev, 0);
 761         if (irq == cmp_irq) {
 762                 if (ml403_ac97cr->enable_irq)
 763                         snd_pcm_indirect2_playback_interrupt(
 764                                 ml403_ac97cr->playback_substream,
 765                                 &ml403_ac97cr->ind_rec,
 766                                 snd_ml403_ac97cr_playback_ind2_copy,
 767                                 snd_ml403_ac97cr_playback_ind2_zero);
 768                 else
 769                         goto __disable_irq;
 770         } else {
 771                 /* record interrupt */
 772                 cmp_irq = platform_get_irq(pfdev, 1);
 773                 if (irq == cmp_irq) {
 774                         if (ml403_ac97cr->enable_capture_irq)
 775                                 snd_pcm_indirect2_capture_interrupt(
 776                                         ml403_ac97cr->capture_substream,
 777                                         &ml403_ac97cr->capture_ind2_rec,
 778                                         snd_ml403_ac97cr_capture_ind2_copy,
 779                                         snd_ml403_ac97cr_capture_ind2_null);
 780                         else
 781                                 goto __disable_irq;
 782                 } else
 783                         return IRQ_NONE;
 784         }
 785         return IRQ_HANDLED;
 786
 787 __disable_irq:
 788         PDEBUG(INIT_INFO, "irq(): irq %d is meant to be disabled! So, now try "
 789                "to disable it _really_!\n", irq);
 790         disable_irq_nosync(irq);
 791         return IRQ_HANDLED;
 792 }
 793
 794 static unsigned short
 795 snd_ml403_ac97cr_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 796 {
 797         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 798 #ifdef CODEC_STAT
 799         u32 stat;
 800         u32 rafaccess = 0;
 801 #endif
 802         unsigned long end_time;
 803         u16 value = 0;
 804
 805         if (!LM4550_RF_OK(reg)) {
 806                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 807                            "access to unknown/unused codec register 0x%x "
 808                            "ignored!\n", reg);
 809                 return 0;
 810         }
 811         /* check if we can fake/answer this access from our shadow register */
 812         if ((lm4550_regfile[reg / 2].flag &
 813              (LM4550_REG_DONEREAD | LM4550_REG_ALLFAKE)) &&
 814             !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 815                 if (lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEREAD) {
 816                         PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 817                                "reg=0x%x, val=0x%x / %d\n",
 818                                reg, lm4550_regfile[reg / 2].def,
 819                                lm4550_regfile[reg / 2].def);
 820                         return lm4550_regfile[reg / 2].def;
 821                 } else if ((lm4550_regfile[reg / 2].flag &
 822                             LM4550_REG_FAKEPROBE) &&
 823                            ml403_ac97cr->ac97_fake) {
 824                         PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 825                                "reg=0x%x, val=0x%x / %d (probe)\n",
 826                                reg, lm4550_regfile[reg / 2].value,
 827                                lm4550_regfile[reg / 2].value);
 828                         return lm4550_regfile[reg / 2].value;
 829                 } else {
 830 #ifdef CODEC_STAT
 831                         PDEBUG(CODEC_FAKE, "codec_read(): read access "
 832                                "answered by shadow register 0x%x (value=0x%x "
 833                                "/ %d) (cw=%d cr=%d)\n",
 834                                reg, lm4550_regfile[reg / 2].value,
 835                                lm4550_regfile[reg / 2].value,
 836                                ml403_ac97cr->ac97_write,
 837                                ml403_ac97cr->ac97_read);
 838 #else
 839                         PDEBUG(CODEC_FAKE, "codec_read(): read access "
 840                                "answered by shadow register 0x%x (value=0x%x "
 841                                "/ %d)\n",
 842                                reg, lm4550_regfile[reg / 2].value,
 843                                lm4550_regfile[reg / 2].value);
 844 #endif
 845                         return lm4550_regfile[reg / 2].value;
 846                 }
 847         }
 848         /* if we are here, we _have_ to access the codec really, no faking */
 849         if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 850                 return 0;
 851 #ifdef CODEC_STAT
 852         ml403_ac97cr->ac97_read++;
 853 #endif
 854         spin_lock(&ml403_ac97cr->reg_lock);
 855         out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
 856                  CR_CODEC_ADDR(reg) | CR_CODEC_READ);
 857         spin_unlock(&ml403_ac97cr->reg_lock);
 858         end_time = jiffies + (HZ / CODEC_TIMEOUT_AFTER_READ);
 859         do {
 860                 spin_lock(&ml403_ac97cr->reg_lock);
 861 #ifdef CODEC_STAT
 862                 rafaccess++;
 863                 stat = in_be32(CR_REG(ml403_ac97cr, STATUS));
 864                 if ((stat & CR_RAF) == CR_RAF) {
 865                         value = CR_CODEC_DATAREAD(
 866                                 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 867                         PDEBUG(CODEC_SUCCESS, "codec_read(): (done) reg=0x%x, "
 868                                "value=0x%x / %d (STATUS=0x%x)\n",
 869                                reg, value, value, stat);
 870 #else
 871                 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 872                      CR_RAF) == CR_RAF) {
 873                         value = CR_CODEC_DATAREAD(
 874                                 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 875                         PDEBUG(CODEC_SUCCESS, "codec_read(): (done) "
 876                                "reg=0x%x, value=0x%x / %d\n",
 877                                reg, value, value);
 878 #endif
 879                         lm4550_regfile[reg / 2].value = value;
 880                         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 881                         spin_unlock(&ml403_ac97cr->reg_lock);
 882                         mutex_unlock(&ml403_ac97cr->cdc_mutex);
 883                         return value;
 884                 }
 885                 spin_unlock(&ml403_ac97cr->reg_lock);
 886                 schedule_timeout_uninterruptible(1);
 887         } while (time_after(end_time, jiffies));
 888         /* read the DATAREAD register anyway, see comment below */
 889         spin_lock(&ml403_ac97cr->reg_lock);
 890         value =
 891             CR_CODEC_DATAREAD(in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 892         spin_unlock(&ml403_ac97cr->reg_lock);
 893 #ifdef CODEC_STAT
 894         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 895                    "timeout while codec read! "
 896                    "(reg=0x%x, last STATUS=0x%x, DATAREAD=0x%x / %d, %d) "
 897                    "(cw=%d, cr=%d)\n",
 898                    reg, stat, value, value, rafaccess,
 899                    ml403_ac97cr->ac97_write, ml403_ac97cr->ac97_read);
 900 #else
 901         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 902                    "timeout while codec read! "
 903                    "(reg=0x%x, DATAREAD=0x%x / %d)\n",
 904                    reg, value, value);
 905 #endif
 906         /* BUG: This is PURE speculation! But after _most_ read timeouts the
 907          * value in the register is ok!
 908          */
 909         lm4550_regfile[reg / 2].value = value;
 910         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 911         mutex_unlock(&ml403_ac97cr->cdc_mutex);
 912         return value;
 913 }
 914
 915 static void
 916 snd_ml403_ac97cr_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 917                              unsigned short val)
 918 {
 919         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 920
 921 #ifdef CODEC_STAT
 922         u32 stat;
 923         u32 rafaccess = 0;
 924 #endif
 925 #ifdef CODEC_WRITE_CHECK_RAF
 926         unsigned long end_time;
 927 #endif
 928
 929         if (!LM4550_RF_OK(reg)) {
 930                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 931                            "access to unknown/unused codec register 0x%x "
 932                            "ignored!\n", reg);
 933                 return;
 934         }
 935         if (lm4550_regfile[reg / 2].flag & LM4550_REG_READONLY) {
 936                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 937                            "write access to read only codec register 0x%x "
 938                            "ignored!\n", reg);
 939                 return;
 940         }
 941         if ((val & lm4550_regfile[reg / 2].wmask) != val) {
 942                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 943                            "write access to codec register 0x%x "
 944                            "with bad value 0x%x / %d!\n",
 945                            reg, val, val);
 946                 val = val & lm4550_regfile[reg / 2].wmask;
 947         }
 948         if (((lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEPROBE) &&
 949              ml403_ac97cr->ac97_fake) &&
 950             !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 951                 PDEBUG(CODEC_FAKE, "codec_write(): faking write to reg=0x%x, "
 952                        "val=0x%x / %d\n", reg, val, val);
 953                 lm4550_regfile[reg / 2].value = (val &
 954                                                 lm4550_regfile[reg / 2].wmask);
 955                 return;
 956         }
 957         if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 958                 return;
 959 #ifdef CODEC_STAT
 960         ml403_ac97cr->ac97_write++;
 961 #endif
 962         spin_lock(&ml403_ac97cr->reg_lock);
 963         out_be32(CR_REG(ml403_ac97cr, CODEC_DATAWRITE),
 964                  CR_CODEC_DATAWRITE(val));
 965         out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
 966                  CR_CODEC_ADDR(reg) | CR_CODEC_WRITE);
 967         spin_unlock(&ml403_ac97cr->reg_lock);
 968 #ifdef CODEC_WRITE_CHECK_RAF
 969         /* check CR_CODEC_RAF bit to see if write access to register is done;
 970          * loop until bit is set or timeout happens
 971          */
 972         end_time = jiffies + HZ / CODEC_TIMEOUT_AFTER_WRITE;
 973         do {
 974                 spin_lock(&ml403_ac97cr->reg_lock);
 975 #ifdef CODEC_STAT
 976                 rafaccess++;
 977                 stat = in_be32(CR_REG(ml403_ac97cr, STATUS))
 978                 if ((stat & CR_RAF) == CR_RAF) {
 979 #else
 980                 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 981                      CR_RAF) == CR_RAF) {
 982 #endif
 983                         PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
 984                                "reg=0x%x, value=%d / 0x%x\n",
 985                                reg, val, val);
 986                         if (!(lm4550_regfile[reg / 2].flag &
 987                               LM4550_REG_NOSHADOW) &&
 988                             !(lm4550_regfile[reg / 2].flag &
 989                               LM4550_REG_NOSAVE))
 990                                 lm4550_regfile[reg / 2].value = val;
 991                         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 992                         spin_unlock(&ml403_ac97cr->reg_lock);
 993                         mutex_unlock(&ml403_ac97cr->cdc_mutex);
 994                         return;
 995                 }
 996                 spin_unlock(&ml403_ac97cr->reg_lock);
 997                 schedule_timeout_uninterruptible(1);
 998         } while (time_after(end_time, jiffies));
 999 #ifdef CODEC_STAT
1000         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1001                    "timeout while codec write "
1002                    "(reg=0x%x, val=0x%x / %d, last STATUS=0x%x, %d) "
1003                    "(cw=%d, cr=%d)\n",
1004                    reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write,
1005                    ml403_ac97cr->ac97_read);
1006 #else
1007         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1008                    "timeout while codec write (reg=0x%x, val=0x%x / %d)\n",
1009                    reg, val, val);
1010 #endif
1011 #else /* CODEC_WRITE_CHECK_RAF */
1012 #if CODEC_WAIT_AFTER_WRITE > 0
1013         /* officially, in AC97 spec there is no possibility for a AC97
1014          * controller to determine, if write access is done or not - so: How
1015          * is Xilinx able to provide a RAF bit for write access?
1016          * => very strange, thus just don't check RAF bit (compare with
1017          * Xilinx's example app in EDK 8.1i) and wait
1018          */
1019         schedule_timeout_uninterruptible(HZ / CODEC_WAIT_AFTER_WRITE);
1020 #endif
1021         PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
1022                "reg=0x%x, value=%d / 0x%x (no RAF check)\n",
1023                reg, val, val);
1024 #endif
1025         mutex_unlock(&ml403_ac97cr->cdc_mutex);
1026         return;
1027 }
1028
1029 static int
1030 snd_ml403_ac97cr_chip_init(struct snd_ml403_ac97cr *ml403_ac97cr)
1031 {
1032         unsigned long end_time;
1033         PDEBUG(INIT_INFO, "chip_init():\n");
1034         end_time = jiffies + HZ / CODEC_TIMEOUT_ON_INIT;
1035         do {
1036                 if (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_CODECREADY) {
1037                         /* clear both hardware FIFOs */
1038                         out_be32(CR_REG(ml403_ac97cr, RESETFIFO),
1039                                  CR_RECRESET | CR_PLAYRESET);
1040                         PDEBUG(INIT_INFO, "chip_init(): (done)\n");
1041                         return 0;
1042                 }
1043                 schedule_timeout_uninterruptible(1);
1044         } while (time_after(end_time, jiffies));
1045         snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1046                    "timeout while waiting for codec, "
1047                    "not ready!\n");
1048         return -EBUSY;
1049 }
1050
1051 static int snd_ml403_ac97cr_free(struct snd_ml403_ac97cr *ml403_ac97cr)
1052 {
1053         PDEBUG(INIT_INFO, "free():\n");
1054         /* irq release */
1055         if (ml403_ac97cr->irq >= 0)
1056                 free_irq(ml403_ac97cr->irq, ml403_ac97cr);
1057         if (ml403_ac97cr->capture_irq >= 0)
1058                 free_irq(ml403_ac97cr->capture_irq, ml403_ac97cr);
1059         /* give back "port" */
1060         iounmap(ml403_ac97cr->port);
1061         kfree(ml403_ac97cr);
1062         PDEBUG(INIT_INFO, "free(): (done)\n");
1063         return 0;
1064 }
1065
1066 static int snd_ml403_ac97cr_dev_free(struct snd_device *snddev)
1067 {
1068         struct snd_ml403_ac97cr *ml403_ac97cr = snddev->device_data;
1069         PDEBUG(INIT_INFO, "dev_free():\n");
1070         return snd_ml403_ac97cr_free(ml403_ac97cr);
1071 }
1072
1073 static int
1074 snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev,
1075                         struct snd_ml403_ac97cr **rml403_ac97cr)
1076 {
1077         struct snd_ml403_ac97cr *ml403_ac97cr;
1078         int err;
1079         static const struct snd_device_ops ops = {
1080                 .dev_free = snd_ml403_ac97cr_dev_free,
1081         };
1082         struct resource *resource;
1083         int irq;
1084
1085         *rml403_ac97cr = NULL;
1086         ml403_ac97cr = kzalloc(sizeof(*ml403_ac97cr), GFP_KERNEL);
1087         if (ml403_ac97cr == NULL)
1088                 return -ENOMEM;
1089         spin_lock_init(&ml403_ac97cr->reg_lock);
1090         mutex_init(&ml403_ac97cr->cdc_mutex);
1091         ml403_ac97cr->card = card;
1092         ml403_ac97cr->pfdev = pfdev;
1093         ml403_ac97cr->irq = -1;
1094         ml403_ac97cr->enable_irq = 0;
1095         ml403_ac97cr->capture_irq = -1;
1096         ml403_ac97cr->enable_capture_irq = 0;
1097         ml403_ac97cr->port = NULL;
1098         ml403_ac97cr->res_port = NULL;
1099
1100         PDEBUG(INIT_INFO, "Trying to reserve resources now ...\n");
1101         resource = platform_get_resource(pfdev, IORESOURCE_MEM, 0);
1102         /* get "port" */
1103         ml403_ac97cr->port = ioremap(resource->start,
1104                                              (resource->end) -
1105                                              (resource->start) + 1);
1106         if (ml403_ac97cr->port == NULL) {
1107                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1108                            "unable to remap memory region (%pR)\n",
1109                            resource);
1110                 snd_ml403_ac97cr_free(ml403_ac97cr);
1111                 return -EBUSY;
1112         }
1113         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1114                    "remap controller memory region to "
1115                    "0x%x done\n", (unsigned int)ml403_ac97cr->port);
1116         /* get irq */
1117         irq = platform_get_irq(pfdev, 0);
1118         if (request_irq(irq, snd_ml403_ac97cr_irq, 0,
1119                         dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1120                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1121                            "unable to grab IRQ %d\n",
1122                            irq);
1123                 snd_ml403_ac97cr_free(ml403_ac97cr);
1124                 return -EBUSY;
1125         }
1126         ml403_ac97cr->irq = irq;
1127         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1128                    "request (playback) irq %d done\n",
1129                    ml403_ac97cr->irq);
1130         irq = platform_get_irq(pfdev, 1);
1131         if (request_irq(irq, snd_ml403_ac97cr_irq, 0,
1132                         dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1133                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1134                            "unable to grab IRQ %d\n",
1135                            irq);
1136                 snd_ml403_ac97cr_free(ml403_ac97cr);
1137                 return -EBUSY;
1138         }
1139         ml403_ac97cr->capture_irq = irq;
1140         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1141                    "request (capture) irq %d done\n",
1142                    ml403_ac97cr->capture_irq);
1143
1144         err = snd_ml403_ac97cr_chip_init(ml403_ac97cr);
1145         if (err < 0) {
1146                 snd_ml403_ac97cr_free(ml403_ac97cr);
1147                 return err;
1148         }
1149
1150         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ml403_ac97cr, &ops);
1151         if (err < 0) {
1152                 PDEBUG(INIT_FAILURE, "probe(): snd_device_new() failed!\n");
1153                 snd_ml403_ac97cr_free(ml403_ac97cr);
1154                 return err;
1155         }
1156
1157         *rml403_ac97cr = ml403_ac97cr;
1158         return 0;
1159 }
1160
1161 static void snd_ml403_ac97cr_mixer_free(struct snd_ac97 *ac97)
1162 {
1163         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
1164         PDEBUG(INIT_INFO, "mixer_free():\n");
1165         ml403_ac97cr->ac97 = NULL;
1166         PDEBUG(INIT_INFO, "mixer_free(): (done)\n");
1167 }
1168
1169 static int
1170 snd_ml403_ac97cr_mixer(struct snd_ml403_ac97cr *ml403_ac97cr)
1171 {
1172         struct snd_ac97_bus *bus;
1173         struct snd_ac97_template ac97;
1174         int err;
1175         static const struct snd_ac97_bus_ops ops = {
1176                 .write = snd_ml403_ac97cr_codec_write,
1177                 .read = snd_ml403_ac97cr_codec_read,
1178         };
1179         PDEBUG(INIT_INFO, "mixer():\n");
1180         err = snd_ac97_bus(ml403_ac97cr->card, 0, &ops, NULL, &bus);
1181         if (err < 0)
1182                 return err;
1183
1184         memset(&ac97, 0, sizeof(ac97));
1185         ml403_ac97cr->ac97_fake = 1;
1186         lm4550_regfile_init();
1187 #ifdef CODEC_STAT
1188         ml403_ac97cr->ac97_read = 0;
1189         ml403_ac97cr->ac97_write = 0;
1190 #endif
1191         ac97.private_data = ml403_ac97cr;
1192         ac97.private_free = snd_ml403_ac97cr_mixer_free;
1193         ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM |
1194             AC97_SCAP_NO_SPDIF;
1195         err = snd_ac97_mixer(bus, &ac97, &ml403_ac97cr->ac97);
1196         ml403_ac97cr->ac97_fake = 0;
1197         lm4550_regfile_write_values_after_init(ml403_ac97cr->ac97);
1198         PDEBUG(INIT_INFO, "mixer(): (done) snd_ac97_mixer()=%d\n", err);
1199         return err;
1200 }
1201
1202 static int
1203 snd_ml403_ac97cr_pcm(struct snd_ml403_ac97cr *ml403_ac97cr, int device)
1204 {
1205         struct snd_pcm *pcm;
1206         int err;
1207
1208         err = snd_pcm_new(ml403_ac97cr->card, "ML403AC97CR/1", device, 1, 1,
1209                           &pcm);
1210         if (err < 0)
1211                 return err;
1212         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1213                         &snd_ml403_ac97cr_playback_ops);
1214         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1215                         &snd_ml403_ac97cr_capture_ops);
1216         pcm->private_data = ml403_ac97cr;
1217         pcm->info_flags = 0;
1218         strcpy(pcm->name, "ML403AC97CR DAC/ADC");
1219         ml403_ac97cr->pcm = pcm;
1220
1221         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1222                                        NULL,
1223                                        64 * 1024,
1224                                        128 * 1024);
1225         return 0;
1226 }
1227
1228 static int snd_ml403_ac97cr_probe(struct platform_device *pfdev)
1229 {
1230         struct snd_card *card;
1231         struct snd_ml403_ac97cr *ml403_ac97cr = NULL;
1232         int err;
1233         int dev = pfdev->id;
1234
1235         if (dev >= SNDRV_CARDS)
1236                 return -ENODEV;
1237         if (!enable[dev])
1238                 return -ENOENT;
1239
1240         err = snd_card_new(&pfdev->dev, index[dev], id[dev], THIS_MODULE,
1241                            0, &card);
1242         if (err < 0)
1243                 return err;
1244         err = snd_ml403_ac97cr_create(card, pfdev, &ml403_ac97cr);
1245         if (err < 0) {
1246                 PDEBUG(INIT_FAILURE, "probe(): create failed!\n");
1247                 snd_card_free(card);
1248                 return err;
1249         }
1250         PDEBUG(INIT_INFO, "probe(): create done\n");
1251         card->private_data = ml403_ac97cr;
1252         err = snd_ml403_ac97cr_mixer(ml403_ac97cr);
1253         if (err < 0) {
1254                 snd_card_free(card);
1255                 return err;
1256         }
1257         PDEBUG(INIT_INFO, "probe(): mixer done\n");
1258         err = snd_ml403_ac97cr_pcm(ml403_ac97cr, 0);
1259         if (err < 0) {
1260                 snd_card_free(card);
1261                 return err;
1262         }
1263         PDEBUG(INIT_INFO, "probe(): PCM done\n");
1264         strcpy(card->driver, SND_ML403_AC97CR_DRIVER);
1265         strcpy(card->shortname, "ML403 AC97 Controller Reference");
1266         sprintf(card->longname, "%s %s at 0x%lx, irq %i & %i, device %i",
1267                 card->shortname, card->driver,
1268                 (unsigned long)ml403_ac97cr->port, ml403_ac97cr->irq,
1269                 ml403_ac97cr->capture_irq, dev + 1);
1270
1271         err = snd_card_register(card);
1272         if (err < 0) {
1273                 snd_card_free(card);
1274                 return err;
1275         }
1276         platform_set_drvdata(pfdev, card);
1277         PDEBUG(INIT_INFO, "probe(): (done)\n");
1278         return 0;
1279 }
1280
1281 static int snd_ml403_ac97cr_remove(struct platform_device *pfdev)
1282 {
1283         snd_card_free(platform_get_drvdata(pfdev));
1284         return 0;
1285 }
1286
1287 /* work with hotplug and coldplug */
1288 MODULE_ALIAS("platform:" SND_ML403_AC97CR_DRIVER);
1289
1290 static struct platform_driver snd_ml403_ac97cr_driver = {
1291         .probe = snd_ml403_ac97cr_probe,
1292         .remove = snd_ml403_ac97cr_remove,
1293         .driver = {
1294                 .name = SND_ML403_AC97CR_DRIVER,
1295         },
1296 };
1297
1298 module_platform_driver(snd_ml403_ac97cr_driver);