sound/hda/hdac_controller.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * HD-audio controller helpers
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/export.h>
   9 #include <sound/core.h>
  10 #include <sound/hdaudio.h>
  11 #include <sound/hda_register.h>
  12
  13 /* clear CORB read pointer properly */
  14 static void azx_clear_corbrp(struct hdac_bus *bus)
  15 {
  16         int timeout;
  17
  18         for (timeout = 1000; timeout > 0; timeout--) {
  19                 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
  20                         break;
  21                 udelay(1);
  22         }
  23         if (timeout <= 0)
  24                 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
  25                         snd_hdac_chip_readw(bus, CORBRP));
  26
  27         snd_hdac_chip_writew(bus, CORBRP, 0);
  28         for (timeout = 1000; timeout > 0; timeout--) {
  29                 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
  30                         break;
  31                 udelay(1);
  32         }
  33         if (timeout <= 0)
  34                 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
  35                         snd_hdac_chip_readw(bus, CORBRP));
  36 }
  37
  38 /**
  39  * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
  40  * @bus: HD-audio core bus
  41  */
  42 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
  43 {
  44         WARN_ON_ONCE(!bus->rb.area);
  45
  46         spin_lock_irq(&bus->reg_lock);
  47         /* CORB set up */
  48         bus->corb.addr = bus->rb.addr;
  49         bus->corb.buf = (__le32 *)bus->rb.area;
  50         snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
  51         snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
  52
  53         /* set the corb size to 256 entries (ULI requires explicitly) */
  54         snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
  55         /* set the corb write pointer to 0 */
  56         snd_hdac_chip_writew(bus, CORBWP, 0);
  57
  58         /* reset the corb hw read pointer */
  59         snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
  60         if (!bus->corbrp_self_clear)
  61                 azx_clear_corbrp(bus);
  62
  63         /* enable corb dma */
  64         snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
  65
  66         /* RIRB set up */
  67         bus->rirb.addr = bus->rb.addr + 2048;
  68         bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
  69         bus->rirb.wp = bus->rirb.rp = 0;
  70         memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
  71         snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
  72         snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
  73
  74         /* set the rirb size to 256 entries (ULI requires explicitly) */
  75         snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
  76         /* reset the rirb hw write pointer */
  77         snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
  78         /* set N=1, get RIRB response interrupt for new entry */
  79         snd_hdac_chip_writew(bus, RINTCNT, 1);
  80         /* enable rirb dma and response irq */
  81         snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
  82         /* Accept unsolicited responses */
  83         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
  84         spin_unlock_irq(&bus->reg_lock);
  85 }
  86 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
  87
  88 /* wait for cmd dmas till they are stopped */
  89 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
  90 {
  91         unsigned long timeout;
  92
  93         timeout = jiffies + msecs_to_jiffies(100);
  94         while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
  95                 && time_before(jiffies, timeout))
  96                 udelay(10);
  97
  98         timeout = jiffies + msecs_to_jiffies(100);
  99         while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
 100                 && time_before(jiffies, timeout))
 101                 udelay(10);
 102 }
 103
 104 /**
 105  * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
 106  * @bus: HD-audio core bus
 107  */
 108 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
 109 {
 110         spin_lock_irq(&bus->reg_lock);
 111         /* disable ringbuffer DMAs */
 112         snd_hdac_chip_writeb(bus, RIRBCTL, 0);
 113         snd_hdac_chip_writeb(bus, CORBCTL, 0);
 114         spin_unlock_irq(&bus->reg_lock);
 115
 116         hdac_wait_for_cmd_dmas(bus);
 117
 118         spin_lock_irq(&bus->reg_lock);
 119         /* disable unsolicited responses */
 120         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
 121         spin_unlock_irq(&bus->reg_lock);
 122 }
 123 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
 124
 125 static unsigned int azx_command_addr(u32 cmd)
 126 {
 127         unsigned int addr = cmd >> 28;
 128
 129         if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
 130                 addr = 0;
 131         return addr;
 132 }
 133
 134 /**
 135  * snd_hdac_bus_send_cmd - send a command verb via CORB
 136  * @bus: HD-audio core bus
 137  * @val: encoded verb value to send
 138  *
 139  * Returns zero for success or a negative error code.
 140  */
 141 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
 142 {
 143         unsigned int addr = azx_command_addr(val);
 144         unsigned int wp, rp;
 145
 146         spin_lock_irq(&bus->reg_lock);
 147
 148         bus->last_cmd[azx_command_addr(val)] = val;
 149
 150         /* add command to corb */
 151         wp = snd_hdac_chip_readw(bus, CORBWP);
 152         if (wp == 0xffff) {
 153                 /* something wrong, controller likely turned to D3 */
 154                 spin_unlock_irq(&bus->reg_lock);
 155                 return -EIO;
 156         }
 157         wp++;
 158         wp %= AZX_MAX_CORB_ENTRIES;
 159
 160         rp = snd_hdac_chip_readw(bus, CORBRP);
 161         if (wp == rp) {
 162                 /* oops, it's full */
 163                 spin_unlock_irq(&bus->reg_lock);
 164                 return -EAGAIN;
 165         }
 166
 167         bus->rirb.cmds[addr]++;
 168         bus->corb.buf[wp] = cpu_to_le32(val);
 169         snd_hdac_chip_writew(bus, CORBWP, wp);
 170
 171         spin_unlock_irq(&bus->reg_lock);
 172
 173         return 0;
 174 }
 175 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
 176
 177 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
 178
 179 /**
 180  * snd_hdac_bus_update_rirb - retrieve RIRB entries
 181  * @bus: HD-audio core bus
 182  *
 183  * Usually called from interrupt handler.
 184  */
 185 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
 186 {
 187         unsigned int rp, wp;
 188         unsigned int addr;
 189         u32 res, res_ex;
 190
 191         wp = snd_hdac_chip_readw(bus, RIRBWP);
 192         if (wp == 0xffff) {
 193                 /* something wrong, controller likely turned to D3 */
 194                 return;
 195         }
 196
 197         if (wp == bus->rirb.wp)
 198                 return;
 199         bus->rirb.wp = wp;
 200
 201         while (bus->rirb.rp != wp) {
 202                 bus->rirb.rp++;
 203                 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
 204
 205                 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 206                 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
 207                 res = le32_to_cpu(bus->rirb.buf[rp]);
 208                 addr = res_ex & 0xf;
 209                 if (addr >= HDA_MAX_CODECS) {
 210                         dev_err(bus->dev,
 211                                 "spurious response %#x:%#x, rp = %d, wp = %d",
 212                                 res, res_ex, bus->rirb.rp, wp);
 213                         snd_BUG();
 214                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
 215                         snd_hdac_bus_queue_event(bus, res, res_ex);
 216                 else if (bus->rirb.cmds[addr]) {
 217                         bus->rirb.res[addr] = res;
 218                         bus->rirb.cmds[addr]--;
 219                         if (!bus->rirb.cmds[addr] &&
 220                             waitqueue_active(&bus->rirb_wq))
 221                                 wake_up(&bus->rirb_wq);
 222                 } else {
 223                         dev_err_ratelimited(bus->dev,
 224                                 "spurious response %#x:%#x, last cmd=%#08x\n",
 225                                 res, res_ex, bus->last_cmd[addr]);
 226                 }
 227         }
 228 }
 229 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
 230
 231 /**
 232  * snd_hdac_bus_get_response - receive a response via RIRB
 233  * @bus: HD-audio core bus
 234  * @addr: codec address
 235  * @res: pointer to store the value, NULL when not needed
 236  *
 237  * Returns zero if a value is read, or a negative error code.
 238  */
 239 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
 240                               unsigned int *res)
 241 {
 242         unsigned long timeout;
 243         unsigned long loopcounter;
 244         wait_queue_entry_t wait;
 245         bool warned = false;
 246
 247         init_wait_entry(&wait, 0);
 248         timeout = jiffies + msecs_to_jiffies(1000);
 249
 250         for (loopcounter = 0;; loopcounter++) {
 251                 spin_lock_irq(&bus->reg_lock);
 252                 if (!bus->polling_mode)
 253                         prepare_to_wait(&bus->rirb_wq, &wait,
 254                                         TASK_UNINTERRUPTIBLE);
 255                 if (bus->polling_mode)
 256                         snd_hdac_bus_update_rirb(bus);
 257                 if (!bus->rirb.cmds[addr]) {
 258                         if (res)
 259                                 *res = bus->rirb.res[addr]; /* the last value */
 260                         if (!bus->polling_mode)
 261                                 finish_wait(&bus->rirb_wq, &wait);
 262                         spin_unlock_irq(&bus->reg_lock);
 263                         return 0;
 264                 }
 265                 spin_unlock_irq(&bus->reg_lock);
 266                 if (time_after(jiffies, timeout))
 267                         break;
 268 #define LOOP_COUNT_MAX  3000
 269                 if (!bus->polling_mode) {
 270                         schedule_timeout(msecs_to_jiffies(2));
 271                 } else if (bus->needs_damn_long_delay ||
 272                            loopcounter > LOOP_COUNT_MAX) {
 273                         if (loopcounter > LOOP_COUNT_MAX && !warned) {
 274                                 dev_dbg_ratelimited(bus->dev,
 275                                                     "too slow response, last cmd=%#08x\n",
 276                                                     bus->last_cmd[addr]);
 277                                 warned = true;
 278                         }
 279                         msleep(2); /* temporary workaround */
 280                 } else {
 281                         udelay(10);
 282                         cond_resched();
 283                 }
 284         }
 285
 286         if (!bus->polling_mode)
 287                 finish_wait(&bus->rirb_wq, &wait);
 288
 289         return -EIO;
 290 }
 291 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
 292
 293 #define HDAC_MAX_CAPS 10
 294 /**
 295  * snd_hdac_bus_parse_capabilities - parse capability structure
 296  * @bus: the pointer to bus object
 297  *
 298  * Returns 0 if successful, or a negative error code.
 299  */
 300 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
 301 {
 302         unsigned int cur_cap;
 303         unsigned int offset;
 304         unsigned int counter = 0;
 305
 306         offset = snd_hdac_chip_readw(bus, LLCH);
 307
 308         /* Lets walk the linked capabilities list */
 309         do {
 310                 cur_cap = _snd_hdac_chip_readl(bus, offset);
 311
 312                 dev_dbg(bus->dev, "Capability version: 0x%x\n",
 313                         (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
 314
 315                 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
 316                         (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
 317
 318                 if (cur_cap == -1) {
 319                         dev_dbg(bus->dev, "Invalid capability reg read\n");
 320                         break;
 321                 }
 322
 323                 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
 324                 case AZX_ML_CAP_ID:
 325                         dev_dbg(bus->dev, "Found ML capability\n");
 326                         bus->mlcap = bus->remap_addr + offset;
 327                         break;
 328
 329                 case AZX_GTS_CAP_ID:
 330                         dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
 331                         bus->gtscap = bus->remap_addr + offset;
 332                         break;
 333
 334                 case AZX_PP_CAP_ID:
 335                         /* PP capability found, the Audio DSP is present */
 336                         dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
 337                         bus->ppcap = bus->remap_addr + offset;
 338                         break;
 339
 340                 case AZX_SPB_CAP_ID:
 341                         /* SPIB capability found, handler function */
 342                         dev_dbg(bus->dev, "Found SPB capability\n");
 343                         bus->spbcap = bus->remap_addr + offset;
 344                         break;
 345
 346                 case AZX_DRSM_CAP_ID:
 347                         /* DMA resume  capability found, handler function */
 348                         dev_dbg(bus->dev, "Found DRSM capability\n");
 349                         bus->drsmcap = bus->remap_addr + offset;
 350                         break;
 351
 352                 default:
 353                         dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
 354                         cur_cap = 0;
 355                         break;
 356                 }
 357
 358                 counter++;
 359
 360                 if (counter > HDAC_MAX_CAPS) {
 361                         dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
 362                         break;
 363                 }
 364
 365                 /* read the offset of next capability */
 366                 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
 367
 368         } while (offset);
 369
 370         return 0;
 371 }
 372 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
 373
 374 /*
 375  * Lowlevel interface
 376  */
 377
 378 /**
 379  * snd_hdac_bus_enter_link_reset - enter link reset
 380  * @bus: HD-audio core bus
 381  *
 382  * Enter to the link reset state.
 383  */
 384 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
 385 {
 386         unsigned long timeout;
 387
 388         /* reset controller */
 389         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
 390
 391         timeout = jiffies + msecs_to_jiffies(100);
 392         while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
 393                time_before(jiffies, timeout))
 394                 usleep_range(500, 1000);
 395 }
 396 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
 397
 398 /**
 399  * snd_hdac_bus_exit_link_reset - exit link reset
 400  * @bus: HD-audio core bus
 401  *
 402  * Exit from the link reset state.
 403  */
 404 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
 405 {
 406         unsigned long timeout;
 407
 408         snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
 409
 410         timeout = jiffies + msecs_to_jiffies(100);
 411         while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
 412                 usleep_range(500, 1000);
 413 }
 414 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
 415
 416 /* reset codec link */
 417 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
 418 {
 419         if (!full_reset)
 420                 goto skip_reset;
 421
 422         /* clear STATESTS */
 423         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 424
 425         /* reset controller */
 426         snd_hdac_bus_enter_link_reset(bus);
 427
 428         /* delay for >= 100us for codec PLL to settle per spec
 429          * Rev 0.9 section 5.5.1
 430          */
 431         usleep_range(500, 1000);
 432
 433         /* Bring controller out of reset */
 434         snd_hdac_bus_exit_link_reset(bus);
 435
 436         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 437         usleep_range(1000, 1200);
 438
 439  skip_reset:
 440         /* check to see if controller is ready */
 441         if (!snd_hdac_chip_readb(bus, GCTL)) {
 442                 dev_dbg(bus->dev, "controller not ready!\n");
 443                 return -EBUSY;
 444         }
 445
 446         /* detect codecs */
 447         if (!bus->codec_mask) {
 448                 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
 449                 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
 450         }
 451
 452         return 0;
 453 }
 454 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
 455
 456 /* enable interrupts */
 457 static void azx_int_enable(struct hdac_bus *bus)
 458 {
 459         /* enable controller CIE and GIE */
 460         snd_hdac_chip_updatel(bus, INTCTL,
 461                               AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
 462                               AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
 463 }
 464
 465 /* disable interrupts */
 466 static void azx_int_disable(struct hdac_bus *bus)
 467 {
 468         struct hdac_stream *azx_dev;
 469
 470         /* disable interrupts in stream descriptor */
 471         list_for_each_entry(azx_dev, &bus->stream_list, list)
 472                 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
 473
 474         /* disable SIE for all streams */
 475         snd_hdac_chip_writeb(bus, INTCTL, 0);
 476
 477         /* disable controller CIE and GIE */
 478         snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
 479 }
 480
 481 /* clear interrupts */
 482 static void azx_int_clear(struct hdac_bus *bus)
 483 {
 484         struct hdac_stream *azx_dev;
 485
 486         /* clear stream status */
 487         list_for_each_entry(azx_dev, &bus->stream_list, list)
 488                 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 489
 490         /* clear STATESTS */
 491         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 492
 493         /* clear rirb status */
 494         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
 495
 496         /* clear int status */
 497         snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
 498 }
 499
 500 /**
 501  * snd_hdac_bus_init_chip - reset and start the controller registers
 502  * @bus: HD-audio core bus
 503  * @full_reset: Do full reset
 504  */
 505 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 506 {
 507         if (bus->chip_init)
 508                 return false;
 509
 510         /* reset controller */
 511         snd_hdac_bus_reset_link(bus, full_reset);
 512
 513         /* clear interrupts */
 514         azx_int_clear(bus);
 515
 516         /* initialize the codec command I/O */
 517         snd_hdac_bus_init_cmd_io(bus);
 518
 519         /* enable interrupts after CORB/RIRB buffers are initialized above */
 520         azx_int_enable(bus);
 521
 522         /* program the position buffer */
 523         if (bus->use_posbuf && bus->posbuf.addr) {
 524                 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
 525                 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
 526         }
 527
 528         bus->chip_init = true;
 529         return true;
 530 }
 531 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
 532
 533 /**
 534  * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
 535  * @bus: HD-audio core bus
 536  */
 537 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
 538 {
 539         if (!bus->chip_init)
 540                 return;
 541
 542         /* disable interrupts */
 543         azx_int_disable(bus);
 544         azx_int_clear(bus);
 545
 546         /* disable CORB/RIRB */
 547         snd_hdac_bus_stop_cmd_io(bus);
 548
 549         /* disable position buffer */
 550         if (bus->posbuf.addr) {
 551                 snd_hdac_chip_writel(bus, DPLBASE, 0);
 552                 snd_hdac_chip_writel(bus, DPUBASE, 0);
 553         }
 554
 555         bus->chip_init = false;
 556 }
 557 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
 558
 559 /**
 560  * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
 561  * @bus: HD-audio core bus
 562  * @status: INTSTS register value
 563  * @ask: callback to be called for woken streams
 564  *
 565  * Returns the bits of handled streams, or zero if no stream is handled.
 566  */
 567 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
 568                                     void (*ack)(struct hdac_bus *,
 569                                                 struct hdac_stream *))
 570 {
 571         struct hdac_stream *azx_dev;
 572         u8 sd_status;
 573         int handled = 0;
 574
 575         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 576                 if (status & azx_dev->sd_int_sta_mask) {
 577                         sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
 578                         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 579                         handled |= 1 << azx_dev->index;
 580                         if (!azx_dev->substream || !azx_dev->running ||
 581                             !(sd_status & SD_INT_COMPLETE))
 582                                 continue;
 583                         if (ack)
 584                                 ack(bus, azx_dev);
 585                 }
 586         }
 587         return handled;
 588 }
 589 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
 590
 591 /**
 592  * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
 593  * @bus: HD-audio core bus
 594  *
 595  * Call this after assigning the all streams.
 596  * Returns zero for success, or a negative error code.
 597  */
 598 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
 599 {
 600         struct hdac_stream *s;
 601         int num_streams = 0;
 602         int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
 603         int err;
 604
 605         list_for_each_entry(s, &bus->stream_list, list) {
 606                 /* allocate memory for the BDL for each stream */
 607                 err = snd_dma_alloc_pages(dma_type, bus->dev,
 608                                           BDL_SIZE, &s->bdl);
 609                 num_streams++;
 610                 if (err < 0)
 611                         return -ENOMEM;
 612         }
 613
 614         if (WARN_ON(!num_streams))
 615                 return -EINVAL;
 616         /* allocate memory for the position buffer */
 617         err = snd_dma_alloc_pages(dma_type, bus->dev,
 618                                   num_streams * 8, &bus->posbuf);
 619         if (err < 0)
 620                 return -ENOMEM;
 621         list_for_each_entry(s, &bus->stream_list, list)
 622                 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
 623
 624         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 625         return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
 626 }
 627 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
 628
 629 /**
 630  * snd_hdac_bus_free_stream_pages - release BDL and other buffers
 631  * @bus: HD-audio core bus
 632  */
 633 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
 634 {
 635         struct hdac_stream *s;
 636
 637         list_for_each_entry(s, &bus->stream_list, list) {
 638                 if (s->bdl.area)
 639                         snd_dma_free_pages(&s->bdl);
 640         }
 641
 642         if (bus->rb.area)
 643                 snd_dma_free_pages(&bus->rb);
 644         if (bus->posbuf.area)
 645                 snd_dma_free_pages(&bus->posbuf);
 646 }
 647 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);