1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
6 * Routines for control of Cirrus Logic CS461x chips
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
55 #include "cs46xx_lib.h"
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short result,tmp;
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
86 chip->active_ctrl(chip, 1);
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 * Wait for the read to occur.
143 for (count = 0; count < 1000; count++) {
145 * First, we want to wait for a short time.
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
163 * Wait for the valid status bit to go active.
165 for (count = 0; count < 100; count++) {
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
204 struct snd_cs46xx *chip = ac97->private_data;
206 int codec_index = ac97->num;
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
229 chip->active_ctrl(chip, 1);
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
265 for (count = 0; count < 4000; count++) {
267 * First, we want to wait for a short time.
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
282 chip->active_ctrl(chip, -1);
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
306 unsigned long offset,
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
315 dst = chip->region.idx[bank+1].remap_addr + offset;
318 /* writel already converts 32-bit value to right endianess */
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
332 const __le32 *_src = src;
335 *_dst++ = le32_to_cpu(*_src++);
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
345 MODULE_FIRMWARE("cs46xx/cwc4630");
346 MODULE_FIRMWARE("cs46xx/cwcasync");
347 MODULE_FIRMWARE("cs46xx/cwcsnoop");
348 MODULE_FIRMWARE("cs46xx/cwcbinhack");
349 MODULE_FIRMWARE("cs46xx/cwcdma");
351 static void free_module_desc(struct dsp_module_desc *module)
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
366 /* firmware binary format:
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
372 * } symbols[nsymbols];
379 * } segments[nsegments];
382 static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
387 unsigned int nums, fwlen, fwsize;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
397 fwsize = fw->size / 4;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
456 *module_ret = module;
457 release_firmware(fw);
463 free_module_desc(module);
464 release_firmware(fw);
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
478 dst = chip->region.idx[bank+1].remap_addr + offset;
481 /* writel already converts 32-bit value to right endianess */
489 #else /* old DSP image */
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
499 MODULE_FIRMWARE("cs46xx/ba1");
501 static int load_firmware(struct snd_cs46xx *chip)
503 const struct firmware *fw;
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
509 if (fw->size != sizeof(*chip->ba1)) {
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
530 release_firmware(fw);
534 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
547 offset += ba1->memory[idx].size >> 2;
551 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
562 * Write the reset bit of the SP control register.
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
567 * Write the control register.
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
572 * Clear the trap registers.
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
581 * Set the frame timer to reflect the number of cycles per frame.
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
590 * Make sure the previous FIFO write operation has completed.
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
595 if( !(status & SERBST_WBSY) )
598 mdelay(retry_timeout);
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
612 int idx, powerdown = 0;
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
633 * Fill all 256 sample FIFO locations.
635 for (idx = 0; idx < 0xFF; idx++) {
637 * Make sure the previous FIFO write operation has completed.
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
650 * Write the serial port FIFO index.
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
654 * Tell the serial port to load the new value into the FIFO location.
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
671 * Set the frame timer to reflect the number of cycles per frame.
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
680 * Wait until the run at frame bit resets itself in the SP control
683 for (cnt = 0; cnt < 25; cnt++) {
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
703 * Sample rate routines
706 #define GOF_PER_SEC 200
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
745 * Fill in the SampleRateConverter control block.
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
765 if ((rate * 9) < 48000)
769 * We can not capture at at rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = ((48000 * 24) + rate - 1) / rate;
819 * Fill in the VariDecimate control block.
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
849 * Fill in the WriteBack control block.
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
864 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
872 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
880 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
889 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
896 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
902 if (snd_BUG_ON(!cpcm->pcm_channel))
905 #ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
914 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
931 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
938 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
945 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
952 #ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961 #ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
980 spin_unlock(&chip->reg_lock);
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
993 spin_lock(&chip->reg_lock);
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
999 spin_unlock(&chip->reg_lock);
1010 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1017 spin_lock(&chip->reg_lock);
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1035 spin_unlock(&chip->reg_lock);
1040 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1061 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1063 cpcm->pcm_channel_id)) == NULL) {
1064 dev_err(chip->card->dev,
1065 "failed to re-create virtual PCM channel\n");
1069 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1070 cpcm->pcm_channel->sample_rate = sample_rate;
1078 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1079 struct snd_pcm_hw_params *hw_params)
1081 struct snd_pcm_runtime *runtime = substream->runtime;
1082 struct snd_cs46xx_pcm *cpcm;
1084 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1085 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1086 int sample_rate = params_rate(hw_params);
1087 int period_size = params_period_bytes(hw_params);
1089 cpcm = runtime->private_data;
1091 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1092 if (snd_BUG_ON(!sample_rate))
1095 mutex_lock(&chip->spos_mutex);
1097 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1098 mutex_unlock(&chip->spos_mutex);
1102 snd_BUG_ON(!cpcm->pcm_channel);
1103 if (!cpcm->pcm_channel) {
1104 mutex_unlock(&chip->spos_mutex);
1109 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1110 mutex_unlock(&chip->spos_mutex);
1114 dev_dbg(chip->card->dev,
1115 "period_size (%d), periods (%d) buffer_size(%d)\n",
1116 period_size, params_periods(hw_params),
1117 params_buffer_bytes(hw_params));
1120 if (params_periods(hw_params) == CS46XX_FRAGS) {
1121 if (runtime->dma_area != cpcm->hw_buf.area)
1122 snd_pcm_lib_free_pages(substream);
1123 runtime->dma_area = cpcm->hw_buf.area;
1124 runtime->dma_addr = cpcm->hw_buf.addr;
1125 runtime->dma_bytes = cpcm->hw_buf.bytes;
1128 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1129 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_rear_ops;
1133 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1134 substream->ops = &snd_cs46xx_playback_clfe_ops;
1135 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1136 substream->ops = &snd_cs46xx_playback_iec958_ops;
1141 substream->ops = &snd_cs46xx_playback_ops;
1145 if (runtime->dma_area == cpcm->hw_buf.area) {
1146 runtime->dma_area = NULL;
1147 runtime->dma_addr = 0;
1148 runtime->dma_bytes = 0;
1150 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1151 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1152 mutex_unlock(&chip->spos_mutex);
1157 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1158 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1162 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1163 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1164 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1165 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1170 substream->ops = &snd_cs46xx_playback_indirect_ops;
1175 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1176 mutex_unlock(&chip->spos_mutex);
1182 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1184 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 struct snd_cs46xx_pcm *cpcm;
1188 cpcm = runtime->private_data;
1190 /* if play_back open fails, then this function
1191 is called and cpcm can actually be NULL here */
1192 if (!cpcm) return -ENXIO;
1194 if (runtime->dma_area != cpcm->hw_buf.area)
1195 snd_pcm_lib_free_pages(substream);
1197 runtime->dma_area = NULL;
1198 runtime->dma_addr = 0;
1199 runtime->dma_bytes = 0;
1204 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1208 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct snd_cs46xx_pcm *cpcm;
1212 cpcm = runtime->private_data;
1214 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1215 if (snd_BUG_ON(!cpcm->pcm_channel))
1218 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1219 pfie &= ~0x0000f03f;
1222 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1223 pfie &= ~0x0000f03f;
1227 /* if to convert from stereo to mono */
1228 if (runtime->channels == 1) {
1232 /* if to convert from 8 bit to 16 bit */
1233 if (snd_pcm_format_width(runtime->format) == 8) {
1237 /* if to convert to unsigned */
1238 if (snd_pcm_format_unsigned(runtime->format))
1241 /* Never convert byte order when sample stream is 8 bit */
1242 if (snd_pcm_format_width(runtime->format) != 8) {
1243 /* convert from big endian to little endian */
1244 if (snd_pcm_format_big_endian(runtime->format))
1248 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1249 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1250 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1252 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1254 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1256 tmp |= (4 << cpcm->shift) - 1;
1257 /* playback transaction count register */
1258 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1260 /* playback format && interrupt enable */
1261 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1263 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1264 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1266 tmp |= (4 << cpcm->shift) - 1;
1267 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1268 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1269 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1275 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *hw_params)
1278 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1279 struct snd_pcm_runtime *runtime = substream->runtime;
1282 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1283 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1285 if (runtime->periods == CS46XX_FRAGS) {
1286 if (runtime->dma_area != chip->capt.hw_buf.area)
1287 snd_pcm_lib_free_pages(substream);
1288 runtime->dma_area = chip->capt.hw_buf.area;
1289 runtime->dma_addr = chip->capt.hw_buf.addr;
1290 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1291 substream->ops = &snd_cs46xx_capture_ops;
1293 if (runtime->dma_area == chip->capt.hw_buf.area) {
1294 runtime->dma_area = NULL;
1295 runtime->dma_addr = 0;
1296 runtime->dma_bytes = 0;
1298 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1300 substream->ops = &snd_cs46xx_capture_indirect_ops;
1306 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1308 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1309 struct snd_pcm_runtime *runtime = substream->runtime;
1311 if (runtime->dma_area != chip->capt.hw_buf.area)
1312 snd_pcm_lib_free_pages(substream);
1313 runtime->dma_area = NULL;
1314 runtime->dma_addr = 0;
1315 runtime->dma_bytes = 0;
1320 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1322 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1325 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1326 chip->capt.shift = 2;
1327 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1328 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1329 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1330 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1335 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1337 struct snd_cs46xx *chip = dev_id;
1339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1340 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1343 struct snd_cs46xx_pcm *cpcm = NULL;
1347 * Read the Interrupt Status Register to clear the interrupt
1349 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1350 if ((status1 & 0x7fffffff) == 0) {
1351 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1355 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1356 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1358 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1360 if ( status1 & (1 << i) ) {
1361 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1362 if (chip->capt.substream)
1363 snd_pcm_period_elapsed(chip->capt.substream);
1365 if (ins->pcm_channels[i].active &&
1366 ins->pcm_channels[i].private_data &&
1367 !ins->pcm_channels[i].unlinked) {
1368 cpcm = ins->pcm_channels[i].private_data;
1369 snd_pcm_period_elapsed(cpcm->substream);
1374 if ( status2 & (1 << (i - 16))) {
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1387 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1388 if (chip->playback_pcm->substream)
1389 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1391 if ((status1 & HISR_VC1) && chip->pcm) {
1392 if (chip->capt.substream)
1393 snd_pcm_period_elapsed(chip->capt.substream);
1397 if ((status1 & HISR_MIDI) && chip->rmidi) {
1400 spin_lock(&chip->reg_lock);
1401 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1402 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1403 if ((chip->midcr & MIDCR_RIE) == 0)
1405 snd_rawmidi_receive(chip->midi_input, &c, 1);
1407 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1408 if ((chip->midcr & MIDCR_TIE) == 0)
1410 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1411 chip->midcr &= ~MIDCR_TIE;
1412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1415 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1417 spin_unlock(&chip->reg_lock);
1420 * EOI to the PCI part....reenables interrupts
1422 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1427 static const struct snd_pcm_hardware snd_cs46xx_playback =
1429 .info = (SNDRV_PCM_INFO_MMAP |
1430 SNDRV_PCM_INFO_INTERLEAVED |
1431 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1432 /*SNDRV_PCM_INFO_RESUME*/ |
1433 SNDRV_PCM_INFO_SYNC_APPLPTR),
1434 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1435 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1436 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1437 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1442 .buffer_bytes_max = (256 * 1024),
1443 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1444 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1445 .periods_min = CS46XX_FRAGS,
1446 .periods_max = 1024,
1450 static const struct snd_pcm_hardware snd_cs46xx_capture =
1452 .info = (SNDRV_PCM_INFO_MMAP |
1453 SNDRV_PCM_INFO_INTERLEAVED |
1454 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1455 /*SNDRV_PCM_INFO_RESUME*/ |
1456 SNDRV_PCM_INFO_SYNC_APPLPTR),
1457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1463 .buffer_bytes_max = (256 * 1024),
1464 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1465 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1466 .periods_min = CS46XX_FRAGS,
1467 .periods_max = 1024,
1471 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1473 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1475 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1476 .count = ARRAY_SIZE(period_sizes),
1477 .list = period_sizes,
1483 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1485 kfree(runtime->private_data);
1488 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1490 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1491 struct snd_cs46xx_pcm * cpcm;
1492 struct snd_pcm_runtime *runtime = substream->runtime;
1494 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1497 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1498 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1503 runtime->hw = snd_cs46xx_playback;
1504 runtime->private_data = cpcm;
1505 runtime->private_free = snd_cs46xx_pcm_free_substream;
1507 cpcm->substream = substream;
1508 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1509 mutex_lock(&chip->spos_mutex);
1510 cpcm->pcm_channel = NULL;
1511 cpcm->pcm_channel_id = pcm_channel_id;
1514 snd_pcm_hw_constraint_list(runtime, 0,
1515 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1516 &hw_constraints_period_sizes);
1518 mutex_unlock(&chip->spos_mutex);
1520 chip->playback_pcm = cpcm; /* HACK */
1523 if (chip->accept_valid)
1524 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1525 chip->active_ctrl(chip, 1);
1530 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1532 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1536 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1537 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1539 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1540 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1543 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1545 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1549 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1551 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1553 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1555 mutex_lock(&chip->spos_mutex);
1556 cs46xx_iec958_pre_open (chip);
1557 mutex_unlock(&chip->spos_mutex);
1559 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1562 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1564 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1569 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1571 err = snd_cs46xx_playback_close(substream);
1573 mutex_lock(&chip->spos_mutex);
1574 cs46xx_iec958_post_close (chip);
1575 mutex_unlock(&chip->spos_mutex);
1581 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1583 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1585 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1586 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1588 chip->capt.substream = substream;
1589 substream->runtime->hw = snd_cs46xx_capture;
1591 if (chip->accept_valid)
1592 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1594 chip->active_ctrl(chip, 1);
1596 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1597 snd_pcm_hw_constraint_list(substream->runtime, 0,
1598 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1599 &hw_constraints_period_sizes);
1604 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1606 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct snd_cs46xx_pcm * cpcm;
1610 cpcm = runtime->private_data;
1612 /* when playback_open fails, then cpcm can be NULL */
1613 if (!cpcm) return -ENXIO;
1615 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1616 mutex_lock(&chip->spos_mutex);
1617 if (cpcm->pcm_channel) {
1618 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1619 cpcm->pcm_channel = NULL;
1621 mutex_unlock(&chip->spos_mutex);
1623 chip->playback_pcm = NULL;
1626 cpcm->substream = NULL;
1627 snd_dma_free_pages(&cpcm->hw_buf);
1628 chip->active_ctrl(chip, -1);
1633 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1635 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1637 chip->capt.substream = NULL;
1638 snd_dma_free_pages(&chip->capt.hw_buf);
1639 chip->active_ctrl(chip, -1);
1644 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1645 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1646 .open = snd_cs46xx_playback_open_rear,
1647 .close = snd_cs46xx_playback_close,
1648 .hw_params = snd_cs46xx_playback_hw_params,
1649 .hw_free = snd_cs46xx_playback_hw_free,
1650 .prepare = snd_cs46xx_playback_prepare,
1651 .trigger = snd_cs46xx_playback_trigger,
1652 .pointer = snd_cs46xx_playback_direct_pointer,
1655 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1656 .open = snd_cs46xx_playback_open_rear,
1657 .close = snd_cs46xx_playback_close,
1658 .hw_params = snd_cs46xx_playback_hw_params,
1659 .hw_free = snd_cs46xx_playback_hw_free,
1660 .prepare = snd_cs46xx_playback_prepare,
1661 .trigger = snd_cs46xx_playback_trigger,
1662 .pointer = snd_cs46xx_playback_indirect_pointer,
1663 .ack = snd_cs46xx_playback_transfer,
1666 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1667 .open = snd_cs46xx_playback_open_clfe,
1668 .close = snd_cs46xx_playback_close,
1669 .hw_params = snd_cs46xx_playback_hw_params,
1670 .hw_free = snd_cs46xx_playback_hw_free,
1671 .prepare = snd_cs46xx_playback_prepare,
1672 .trigger = snd_cs46xx_playback_trigger,
1673 .pointer = snd_cs46xx_playback_direct_pointer,
1676 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1677 .open = snd_cs46xx_playback_open_clfe,
1678 .close = snd_cs46xx_playback_close,
1679 .hw_params = snd_cs46xx_playback_hw_params,
1680 .hw_free = snd_cs46xx_playback_hw_free,
1681 .prepare = snd_cs46xx_playback_prepare,
1682 .trigger = snd_cs46xx_playback_trigger,
1683 .pointer = snd_cs46xx_playback_indirect_pointer,
1684 .ack = snd_cs46xx_playback_transfer,
1687 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1688 .open = snd_cs46xx_playback_open_iec958,
1689 .close = snd_cs46xx_playback_close_iec958,
1690 .hw_params = snd_cs46xx_playback_hw_params,
1691 .hw_free = snd_cs46xx_playback_hw_free,
1692 .prepare = snd_cs46xx_playback_prepare,
1693 .trigger = snd_cs46xx_playback_trigger,
1694 .pointer = snd_cs46xx_playback_direct_pointer,
1697 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1698 .open = snd_cs46xx_playback_open_iec958,
1699 .close = snd_cs46xx_playback_close_iec958,
1700 .hw_params = snd_cs46xx_playback_hw_params,
1701 .hw_free = snd_cs46xx_playback_hw_free,
1702 .prepare = snd_cs46xx_playback_prepare,
1703 .trigger = snd_cs46xx_playback_trigger,
1704 .pointer = snd_cs46xx_playback_indirect_pointer,
1705 .ack = snd_cs46xx_playback_transfer,
1710 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1711 .open = snd_cs46xx_playback_open,
1712 .close = snd_cs46xx_playback_close,
1713 .hw_params = snd_cs46xx_playback_hw_params,
1714 .hw_free = snd_cs46xx_playback_hw_free,
1715 .prepare = snd_cs46xx_playback_prepare,
1716 .trigger = snd_cs46xx_playback_trigger,
1717 .pointer = snd_cs46xx_playback_direct_pointer,
1720 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1721 .open = snd_cs46xx_playback_open,
1722 .close = snd_cs46xx_playback_close,
1723 .hw_params = snd_cs46xx_playback_hw_params,
1724 .hw_free = snd_cs46xx_playback_hw_free,
1725 .prepare = snd_cs46xx_playback_prepare,
1726 .trigger = snd_cs46xx_playback_trigger,
1727 .pointer = snd_cs46xx_playback_indirect_pointer,
1728 .ack = snd_cs46xx_playback_transfer,
1731 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1732 .open = snd_cs46xx_capture_open,
1733 .close = snd_cs46xx_capture_close,
1734 .hw_params = snd_cs46xx_capture_hw_params,
1735 .hw_free = snd_cs46xx_capture_hw_free,
1736 .prepare = snd_cs46xx_capture_prepare,
1737 .trigger = snd_cs46xx_capture_trigger,
1738 .pointer = snd_cs46xx_capture_direct_pointer,
1741 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1742 .open = snd_cs46xx_capture_open,
1743 .close = snd_cs46xx_capture_close,
1744 .hw_params = snd_cs46xx_capture_hw_params,
1745 .hw_free = snd_cs46xx_capture_hw_free,
1746 .prepare = snd_cs46xx_capture_prepare,
1747 .trigger = snd_cs46xx_capture_trigger,
1748 .pointer = snd_cs46xx_capture_indirect_pointer,
1749 .ack = snd_cs46xx_capture_transfer,
1752 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1753 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1755 #define MAX_PLAYBACK_CHANNELS 1
1758 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1760 struct snd_pcm *pcm;
1763 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1766 pcm->private_data = chip;
1768 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1769 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1772 pcm->info_flags = 0;
1773 strcpy(pcm->name, "CS46xx");
1776 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1784 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1785 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1787 struct snd_pcm *pcm;
1790 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1793 pcm->private_data = chip;
1795 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1798 pcm->info_flags = 0;
1799 strcpy(pcm->name, "CS46xx - Rear");
1800 chip->pcm_rear = pcm;
1802 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1809 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1811 struct snd_pcm *pcm;
1814 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1817 pcm->private_data = chip;
1819 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1822 pcm->info_flags = 0;
1823 strcpy(pcm->name, "CS46xx - Center LFE");
1824 chip->pcm_center_lfe = pcm;
1826 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1833 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1835 struct snd_pcm *pcm;
1838 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1841 pcm->private_data = chip;
1843 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1846 pcm->info_flags = 0;
1847 strcpy(pcm->name, "CS46xx - IEC958");
1848 chip->pcm_iec958 = pcm;
1850 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1861 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1863 struct snd_cs46xx *chip = bus->private_data;
1865 chip->ac97_bus = NULL;
1868 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1870 struct snd_cs46xx *chip = ac97->private_data;
1872 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1873 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1876 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1877 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1878 chip->eapd_switch = NULL;
1881 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1884 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1885 struct snd_ctl_elem_info *uinfo)
1887 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1889 uinfo->value.integer.min = 0;
1890 uinfo->value.integer.max = 0x7fff;
1894 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1896 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1897 int reg = kcontrol->private_value;
1898 unsigned int val = snd_cs46xx_peek(chip, reg);
1899 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1900 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1904 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1907 int reg = kcontrol->private_value;
1908 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1909 (0xffff - ucontrol->value.integer.value[1]));
1910 unsigned int old = snd_cs46xx_peek(chip, reg);
1911 int change = (old != val);
1914 snd_cs46xx_poke(chip, reg, val);
1920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1922 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1924 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1926 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1927 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1932 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1937 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1938 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1939 cs46xx_dsp_set_dac_volume(chip,
1940 ucontrol->value.integer.value[0],
1941 ucontrol->value.integer.value[1]);
1949 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1951 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1953 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1954 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1958 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1960 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1963 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1964 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1965 cs46xx_dsp_set_iec958_volume (chip,
1966 ucontrol->value.integer.value[0],
1967 ucontrol->value.integer.value[1]);
1975 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1977 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1978 struct snd_ctl_elem_value *ucontrol)
1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1981 int reg = kcontrol->private_value;
1983 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1984 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1986 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1991 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1992 struct snd_ctl_elem_value *ucontrol)
1994 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1997 switch (kcontrol->private_value) {
1998 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1999 mutex_lock(&chip->spos_mutex);
2000 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2001 if (ucontrol->value.integer.value[0] && !change)
2002 cs46xx_dsp_enable_spdif_out(chip);
2003 else if (change && !ucontrol->value.integer.value[0])
2004 cs46xx_dsp_disable_spdif_out(chip);
2006 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2007 mutex_unlock(&chip->spos_mutex);
2009 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2010 change = chip->dsp_spos_instance->spdif_status_in;
2011 if (ucontrol->value.integer.value[0] && !change) {
2012 cs46xx_dsp_enable_spdif_in(chip);
2013 /* restore volume */
2015 else if (change && !ucontrol->value.integer.value[0])
2016 cs46xx_dsp_disable_spdif_in(chip);
2018 res = (change != chip->dsp_spos_instance->spdif_status_in);
2022 snd_BUG(); /* should never happen ... */
2028 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2034 if (ins->adc_input != NULL)
2035 ucontrol->value.integer.value[0] = 1;
2037 ucontrol->value.integer.value[0] = 0;
2042 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2043 struct snd_ctl_elem_value *ucontrol)
2045 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2046 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2049 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2050 cs46xx_dsp_enable_adc_capture(chip);
2052 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2053 cs46xx_dsp_disable_adc_capture(chip);
2059 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2060 struct snd_ctl_elem_value *ucontrol)
2062 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2063 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2065 if (ins->pcm_input != NULL)
2066 ucontrol->value.integer.value[0] = 1;
2068 ucontrol->value.integer.value[0] = 0;
2074 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2075 struct snd_ctl_elem_value *ucontrol)
2077 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2078 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2081 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2082 cs46xx_dsp_enable_pcm_capture(chip);
2084 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2085 cs46xx_dsp_disable_pcm_capture(chip);
2092 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2093 struct snd_ctl_elem_value *ucontrol)
2095 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2097 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2099 if (val1 & EGPIODR_GPOE0)
2100 ucontrol->value.integer.value[0] = 1;
2102 ucontrol->value.integer.value[0] = 0;
2108 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2110 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2111 struct snd_ctl_elem_value *ucontrol)
2113 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2114 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2115 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2117 if (ucontrol->value.integer.value[0]) {
2118 /* optical is default */
2119 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2120 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2121 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2122 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2125 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2126 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2129 /* checking diff from the EGPIO direction register
2131 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2135 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2137 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2142 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2143 struct snd_ctl_elem_value *ucontrol)
2145 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2146 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2148 mutex_lock(&chip->spos_mutex);
2149 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2150 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2151 ucontrol->value.iec958.status[2] = 0;
2152 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2153 mutex_unlock(&chip->spos_mutex);
2158 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2159 struct snd_ctl_elem_value *ucontrol)
2161 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2162 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2166 mutex_lock(&chip->spos_mutex);
2167 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2168 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2169 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2170 /* left and right validity bit */
2171 (1 << 13) | (1 << 12);
2174 change = (unsigned int)ins->spdif_csuv_default != val;
2175 ins->spdif_csuv_default = val;
2177 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2178 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2180 mutex_unlock(&chip->spos_mutex);
2185 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2186 struct snd_ctl_elem_value *ucontrol)
2188 ucontrol->value.iec958.status[0] = 0xff;
2189 ucontrol->value.iec958.status[1] = 0xff;
2190 ucontrol->value.iec958.status[2] = 0x00;
2191 ucontrol->value.iec958.status[3] = 0xff;
2195 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2196 struct snd_ctl_elem_value *ucontrol)
2198 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2199 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2201 mutex_lock(&chip->spos_mutex);
2202 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2203 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2204 ucontrol->value.iec958.status[2] = 0;
2205 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2206 mutex_unlock(&chip->spos_mutex);
2211 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2212 struct snd_ctl_elem_value *ucontrol)
2214 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2215 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2219 mutex_lock(&chip->spos_mutex);
2220 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2221 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2222 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2223 /* left and right validity bit */
2224 (1 << 13) | (1 << 12);
2227 change = ins->spdif_csuv_stream != val;
2228 ins->spdif_csuv_stream = val;
2230 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2231 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2233 mutex_unlock(&chip->spos_mutex);
2238 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2241 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2244 .name = "DAC Volume",
2245 .info = snd_cs46xx_vol_info,
2246 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2247 .get = snd_cs46xx_vol_get,
2248 .put = snd_cs46xx_vol_put,
2249 .private_value = BA1_PVOL,
2251 .get = snd_cs46xx_vol_dac_get,
2252 .put = snd_cs46xx_vol_dac_put,
2257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2258 .name = "ADC Volume",
2259 .info = snd_cs46xx_vol_info,
2260 .get = snd_cs46xx_vol_get,
2261 .put = snd_cs46xx_vol_put,
2262 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2263 .private_value = BA1_CVOL,
2265 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2268 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = "ADC Capture Switch",
2272 .info = snd_mixer_boolean_info,
2273 .get = snd_cs46xx_adc_capture_get,
2274 .put = snd_cs46xx_adc_capture_put
2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278 .name = "DAC Capture Switch",
2279 .info = snd_mixer_boolean_info,
2280 .get = snd_cs46xx_pcm_capture_get,
2281 .put = snd_cs46xx_pcm_capture_put
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2286 .info = snd_mixer_boolean_info,
2287 .get = snd_cs46xx_iec958_get,
2288 .put = snd_cs46xx_iec958_put,
2289 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2294 .info = snd_mixer_boolean_info,
2295 .get = snd_cs46xx_iec958_get,
2296 .put = snd_cs46xx_iec958_put,
2297 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2300 /* Input IEC958 volume does not work for the moment. (Benny) */
2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2303 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2304 .info = snd_cs46xx_vol_info,
2305 .get = snd_cs46xx_vol_iec958_get,
2306 .put = snd_cs46xx_vol_iec958_put,
2307 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2311 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2312 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2313 .info = snd_cs46xx_spdif_info,
2314 .get = snd_cs46xx_spdif_default_get,
2315 .put = snd_cs46xx_spdif_default_put,
2318 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2319 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2320 .info = snd_cs46xx_spdif_info,
2321 .get = snd_cs46xx_spdif_mask_get,
2322 .access = SNDRV_CTL_ELEM_ACCESS_READ
2325 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2326 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2327 .info = snd_cs46xx_spdif_info,
2328 .get = snd_cs46xx_spdif_stream_get,
2329 .put = snd_cs46xx_spdif_stream_put
2335 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2336 /* set primary cs4294 codec into Extended Audio Mode */
2337 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2338 struct snd_ctl_elem_value *ucontrol)
2340 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2342 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2343 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2347 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol)
2350 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2351 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2352 AC97_CSR_ACMODE, 0x200,
2353 ucontrol->value.integer.value[0] ? 0 : 0x200);
2356 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2357 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2358 .name = "Duplicate Front",
2359 .info = snd_mixer_boolean_info,
2360 .get = snd_cs46xx_front_dup_get,
2361 .put = snd_cs46xx_front_dup_put,
2365 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2366 /* Only available on the Hercules Game Theater XP soundcard */
2367 static struct snd_kcontrol_new snd_hercules_controls[] = {
2369 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2370 .name = "Optical/Coaxial SPDIF Input Switch",
2371 .info = snd_mixer_boolean_info,
2372 .get = snd_herc_spdif_select_get,
2373 .put = snd_herc_spdif_select_put,
2378 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2380 unsigned long end_time;
2383 /* reset to defaults */
2384 snd_ac97_write(ac97, AC97_RESET, 0);
2386 /* set the desired CODEC mode */
2387 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2388 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2389 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2390 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2391 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2392 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2394 snd_BUG(); /* should never happen ... */
2399 /* it's necessary to wait awhile until registers are accessible after RESET */
2400 /* because the PCM or MASTER volume registers can be modified, */
2401 /* the REC_GAIN register is used for tests */
2402 end_time = jiffies + HZ;
2404 unsigned short ext_mid;
2406 /* use preliminary reads to settle the communication */
2407 snd_ac97_read(ac97, AC97_RESET);
2408 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2409 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2411 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2412 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2415 /* test if we can write to the record gain volume register */
2416 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2417 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2421 } while (time_after_eq(end_time, jiffies));
2423 dev_err(ac97->bus->card->dev,
2424 "CS46xx secondary codec doesn't respond!\n");
2428 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2431 struct snd_ac97_template ac97;
2433 memset(&ac97, 0, sizeof(ac97));
2434 ac97.private_data = chip;
2435 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2437 if (chip->amplifier_ctrl == amp_voyetra)
2438 ac97.scaps = AC97_SCAP_INV_EAPD;
2440 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2441 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2443 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2444 dev_dbg(chip->card->dev,
2445 "secondary codec not present\n");
2450 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2451 for (idx = 0; idx < 100; ++idx) {
2452 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2453 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2458 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2462 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2464 struct snd_card *card = chip->card;
2465 struct snd_ctl_elem_id id;
2468 static const struct snd_ac97_bus_ops ops = {
2469 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2470 .reset = snd_cs46xx_codec_reset,
2472 .write = snd_cs46xx_ac97_write,
2473 .read = snd_cs46xx_ac97_read,
2476 /* detect primary codec */
2477 chip->nr_ac97_codecs = 0;
2478 dev_dbg(chip->card->dev, "detecting primary codec\n");
2479 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2481 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2483 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2485 chip->nr_ac97_codecs = 1;
2487 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2488 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2489 /* try detect a secondary codec */
2490 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2491 chip->nr_ac97_codecs = 2;
2492 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2494 /* add cs4630 mixer controls */
2495 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2496 struct snd_kcontrol *kctl;
2497 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2498 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2499 kctl->id.device = spdif_device;
2500 if ((err = snd_ctl_add(card, kctl)) < 0)
2504 /* get EAPD mixer switch (for voyetra hack) */
2505 memset(&id, 0, sizeof(id));
2506 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2507 strcpy(id.name, "External Amplifier");
2508 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2510 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2511 if (chip->nr_ac97_codecs == 1) {
2512 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2513 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2514 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2517 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2518 AC97_CSR_ACMODE, 0x200);
2521 /* do soundcard specific mixer setup */
2522 if (chip->mixer_init) {
2523 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2524 chip->mixer_init(chip);
2528 /* turn on amplifier */
2529 chip->amplifier_ctrl(chip, 1);
2538 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2540 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2545 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2547 struct snd_cs46xx *chip = substream->rmidi->private_data;
2549 chip->active_ctrl(chip, 1);
2550 spin_lock_irq(&chip->reg_lock);
2551 chip->uartm |= CS46XX_MODE_INPUT;
2552 chip->midcr |= MIDCR_RXE;
2553 chip->midi_input = substream;
2554 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2555 snd_cs46xx_midi_reset(chip);
2557 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2559 spin_unlock_irq(&chip->reg_lock);
2563 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2565 struct snd_cs46xx *chip = substream->rmidi->private_data;
2567 spin_lock_irq(&chip->reg_lock);
2568 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2569 chip->midi_input = NULL;
2570 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2571 snd_cs46xx_midi_reset(chip);
2573 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2575 chip->uartm &= ~CS46XX_MODE_INPUT;
2576 spin_unlock_irq(&chip->reg_lock);
2577 chip->active_ctrl(chip, -1);
2581 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2583 struct snd_cs46xx *chip = substream->rmidi->private_data;
2585 chip->active_ctrl(chip, 1);
2587 spin_lock_irq(&chip->reg_lock);
2588 chip->uartm |= CS46XX_MODE_OUTPUT;
2589 chip->midcr |= MIDCR_TXE;
2590 chip->midi_output = substream;
2591 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2592 snd_cs46xx_midi_reset(chip);
2594 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2596 spin_unlock_irq(&chip->reg_lock);
2600 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2602 struct snd_cs46xx *chip = substream->rmidi->private_data;
2604 spin_lock_irq(&chip->reg_lock);
2605 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2606 chip->midi_output = NULL;
2607 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2608 snd_cs46xx_midi_reset(chip);
2610 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2612 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2613 spin_unlock_irq(&chip->reg_lock);
2614 chip->active_ctrl(chip, -1);
2618 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2620 unsigned long flags;
2621 struct snd_cs46xx *chip = substream->rmidi->private_data;
2623 spin_lock_irqsave(&chip->reg_lock, flags);
2625 if ((chip->midcr & MIDCR_RIE) == 0) {
2626 chip->midcr |= MIDCR_RIE;
2627 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2630 if (chip->midcr & MIDCR_RIE) {
2631 chip->midcr &= ~MIDCR_RIE;
2632 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2635 spin_unlock_irqrestore(&chip->reg_lock, flags);
2638 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2640 unsigned long flags;
2641 struct snd_cs46xx *chip = substream->rmidi->private_data;
2644 spin_lock_irqsave(&chip->reg_lock, flags);
2646 if ((chip->midcr & MIDCR_TIE) == 0) {
2647 chip->midcr |= MIDCR_TIE;
2648 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2649 while ((chip->midcr & MIDCR_TIE) &&
2650 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2651 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2652 chip->midcr &= ~MIDCR_TIE;
2654 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2657 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2660 if (chip->midcr & MIDCR_TIE) {
2661 chip->midcr &= ~MIDCR_TIE;
2662 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2665 spin_unlock_irqrestore(&chip->reg_lock, flags);
2668 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2670 .open = snd_cs46xx_midi_output_open,
2671 .close = snd_cs46xx_midi_output_close,
2672 .trigger = snd_cs46xx_midi_output_trigger,
2675 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2677 .open = snd_cs46xx_midi_input_open,
2678 .close = snd_cs46xx_midi_input_close,
2679 .trigger = snd_cs46xx_midi_input_trigger,
2682 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2684 struct snd_rawmidi *rmidi;
2687 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2689 strcpy(rmidi->name, "CS46XX");
2690 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2691 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2692 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2693 rmidi->private_data = chip;
2694 chip->rmidi = rmidi;
2700 * gameport interface
2703 #if IS_REACHABLE(CONFIG_GAMEPORT)
2705 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2707 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2709 if (snd_BUG_ON(!chip))
2711 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2714 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2716 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2718 if (snd_BUG_ON(!chip))
2720 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2723 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2725 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2726 unsigned js1, js2, jst;
2728 if (snd_BUG_ON(!chip))
2731 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2732 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2733 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2735 *buttons = (~jst >> 4) & 0x0F;
2737 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2738 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2739 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2740 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2742 for(jst=0;jst<4;++jst)
2743 if(axes[jst]==0xFFFF) axes[jst] = -1;
2747 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2750 case GAMEPORT_MODE_COOKED:
2752 case GAMEPORT_MODE_RAW:
2760 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2762 struct gameport *gp;
2764 chip->gameport = gp = gameport_allocate_port();
2766 dev_err(chip->card->dev,
2767 "cannot allocate memory for gameport\n");
2771 gameport_set_name(gp, "CS46xx Gameport");
2772 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2773 gameport_set_dev_parent(gp, &chip->pci->dev);
2774 gameport_set_port_data(gp, chip);
2776 gp->open = snd_cs46xx_gameport_open;
2777 gp->read = snd_cs46xx_gameport_read;
2778 gp->trigger = snd_cs46xx_gameport_trigger;
2779 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2781 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2782 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2784 gameport_register_port(gp);
2789 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2791 if (chip->gameport) {
2792 gameport_unregister_port(chip->gameport);
2793 chip->gameport = NULL;
2797 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2798 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2799 #endif /* CONFIG_GAMEPORT */
2801 #ifdef CONFIG_SND_PROC_FS
2806 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2807 void *file_private_data,
2808 struct file *file, char __user *buf,
2809 size_t count, loff_t pos)
2811 struct snd_cs46xx_region *region = entry->private_data;
2813 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2818 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2819 .read = snd_cs46xx_io_read,
2822 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2824 struct snd_info_entry *entry;
2827 for (idx = 0; idx < 5; idx++) {
2828 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2829 if (! snd_card_proc_new(card, region->name, &entry)) {
2830 entry->content = SNDRV_INFO_CONTENT_DATA;
2831 entry->private_data = chip;
2832 entry->c.ops = &snd_cs46xx_proc_io_ops;
2833 entry->size = region->size;
2834 entry->mode = S_IFREG | 0400;
2837 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2838 cs46xx_dsp_proc_init(card, chip);
2843 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2845 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2846 cs46xx_dsp_proc_done(chip);
2850 #else /* !CONFIG_SND_PROC_FS */
2851 #define snd_cs46xx_proc_init(card, chip)
2852 #define snd_cs46xx_proc_done(chip)
2858 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2862 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2865 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2867 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2870 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2873 * Stop playback DMA.
2875 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2876 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2881 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2882 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2885 * Reset the processor.
2887 snd_cs46xx_reset(chip);
2889 snd_cs46xx_proc_stop(chip);
2892 * Power down the PLL.
2894 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2897 * Turn off the Processor by turning off the software clock enable flag in
2898 * the clock control register.
2900 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2901 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2905 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2909 if (snd_BUG_ON(!chip))
2912 if (chip->active_ctrl)
2913 chip->active_ctrl(chip, 1);
2915 snd_cs46xx_remove_gameport(chip);
2917 if (chip->amplifier_ctrl)
2918 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2920 snd_cs46xx_proc_done(chip);
2922 if (chip->region.idx[0].resource)
2923 snd_cs46xx_hw_stop(chip);
2926 free_irq(chip->irq, chip);
2928 if (chip->active_ctrl)
2929 chip->active_ctrl(chip, -chip->amplifier);
2931 for (idx = 0; idx < 5; idx++) {
2932 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2934 iounmap(region->remap_addr);
2935 release_and_free_resource(region->resource);
2938 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2939 if (chip->dsp_spos_instance) {
2940 cs46xx_dsp_spos_destroy(chip);
2941 chip->dsp_spos_instance = NULL;
2943 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2944 free_module_desc(chip->modules[idx]);
2949 #ifdef CONFIG_PM_SLEEP
2950 kfree(chip->saved_regs);
2953 pci_disable_device(chip->pci);
2958 static int snd_cs46xx_dev_free(struct snd_device *device)
2960 struct snd_cs46xx *chip = device->device_data;
2961 return snd_cs46xx_free(chip);
2967 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2972 * First, blast the clock control register to zero so that the PLL starts
2973 * out in a known state, and blast the master serial port control register
2974 * to zero so that the serial ports also start out in a known state.
2976 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2977 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2980 * If we are in AC97 mode, then we must set the part to a host controlled
2981 * AC-link. Otherwise, we won't be able to bring up the link.
2983 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2984 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2985 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2986 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2988 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2992 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2993 * spec) and then drive it high. This is done for non AC97 modes since
2994 * there might be logic external to the CS461x that uses the ARST# line
2997 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2998 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2999 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3002 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3003 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3004 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3008 * The first thing we do here is to enable sync generation. As soon
3009 * as we start receiving bit clock, we'll start producing the SYNC
3012 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3013 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3014 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3018 * Now wait for a short while to allow the AC97 part to start
3019 * generating bit clock (so we don't try to start the PLL without an
3025 * Set the serial port timing configuration, so that
3026 * the clock control circuit gets its clock from the correct place.
3028 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3031 * Write the selected clock control setup to the hardware. Do not turn on
3032 * SWCE yet (if requested), so that the devices clocked by the output of
3033 * PLL are not clocked until the PLL is stable.
3035 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3036 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3037 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3042 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3045 * Wait until the PLL has stabilized.
3050 * Turn on clocking of the core so that we can setup the serial ports.
3052 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3055 * Enable FIFO Host Bypass
3057 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3060 * Fill the serial port FIFOs with silence.
3062 snd_cs46xx_clear_serial_FIFOs(chip);
3065 * Set the serial port FIFO pointer to the first sample in the FIFO.
3067 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3070 * Write the serial port configuration to the part. The master
3071 * enable bit is not set until all other values have been written.
3073 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3074 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3075 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3078 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3079 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3080 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3081 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3082 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3083 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3090 * Wait for the codec ready signal from the AC97 codec.
3093 while (timeout-- > 0) {
3095 * Read the AC97 status register to see if we've seen a CODEC READY
3096 * signal from the AC97 codec.
3098 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3104 dev_err(chip->card->dev,
3105 "create - never read codec ready from AC'97\n");
3106 dev_err(chip->card->dev,
3107 "it is not probably bug, try to use CS4236 driver\n");
3110 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3113 for (count = 0; count < 150; count++) {
3114 /* First, we want to wait for a short time. */
3117 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3122 * Make sure CODEC is READY.
3124 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3125 dev_dbg(chip->card->dev,
3126 "never read card ready from secondary AC'97\n");
3131 * Assert the vaid frame signal so that we can start sending commands
3132 * to the AC97 codec.
3134 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3135 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3136 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3141 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3142 * the codec is pumping ADC data across the AC-link.
3145 while (timeout-- > 0) {
3147 * Read the input slot valid register and see if input slots 3 and
3150 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3155 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3156 dev_err(chip->card->dev,
3157 "create - never read ISV3 & ISV4 from AC'97\n");
3160 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3161 Reloading the driver may help, if there's other soundcards
3162 with the same problem I would like to know. (Benny) */
3164 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3165 dev_err(chip->card->dev,
3166 "Try reloading the ALSA driver, if you find something\n");
3167 dev_err(chip->card->dev,
3168 "broken or not working on your soundcard upon\n");
3169 dev_err(chip->card->dev,
3170 "this message please report to alsa-devel@alsa-project.org\n");
3177 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3178 * commense the transfer of digital audio data to the AC97 codec.
3181 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3185 * Power down the DAC and ADC. We will power them up (if) when we need
3188 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3191 * Turn off the Processor by turning off the software clock enable flag in
3192 * the clock control register.
3194 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3195 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3201 * start and load DSP
3204 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3208 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3210 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3212 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3214 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3217 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3220 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3223 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3229 * Reset the processor.
3231 snd_cs46xx_reset(chip);
3233 * Download the image to the processor.
3235 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3236 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3237 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3239 dev_err(chip->card->dev, "firmware load error [%s]\n",
3243 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3245 dev_err(chip->card->dev, "image download error [%s]\n",
3251 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3254 err = load_firmware(chip);
3259 err = snd_cs46xx_download_image(chip);
3261 dev_err(chip->card->dev, "image download error\n");
3266 * Stop playback DMA.
3268 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3269 chip->play_ctl = tmp & 0xffff0000;
3270 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3276 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3277 chip->capt.ctl = tmp & 0x0000ffff;
3278 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3282 snd_cs46xx_set_play_sample_rate(chip, 8000);
3283 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3285 snd_cs46xx_proc_start(chip);
3287 cs46xx_enable_stream_irqs(chip);
3289 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3290 /* set the attenuation to 0dB */
3291 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3292 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3300 * AMP control - null AMP
3303 static void amp_none(struct snd_cs46xx *chip, int change)
3307 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3308 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3311 u32 idx, valid_slots,tmp,powerdown = 0;
3312 u16 modem_power,pin_config,logic_type;
3314 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3317 * See if the devices are powered down. If so, we must power them up first
3318 * or they will not respond.
3320 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3322 if (!(tmp & CLKCR1_SWCE)) {
3323 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3328 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3331 if(chip->nr_ac97_codecs != 2) {
3332 dev_err(chip->card->dev,
3333 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3337 modem_power = snd_cs46xx_codec_read (chip,
3338 AC97_EXTENDED_MSTATUS,
3339 CS46XX_SECONDARY_CODEC_INDEX);
3340 modem_power &=0xFEFF;
3342 snd_cs46xx_codec_write(chip,
3343 AC97_EXTENDED_MSTATUS, modem_power,
3344 CS46XX_SECONDARY_CODEC_INDEX);
3347 * Set GPIO pin's 7 and 8 so that they are configured for output.
3349 pin_config = snd_cs46xx_codec_read (chip,
3351 CS46XX_SECONDARY_CODEC_INDEX);
3354 snd_cs46xx_codec_write(chip,
3355 AC97_GPIO_CFG, pin_config,
3356 CS46XX_SECONDARY_CODEC_INDEX);
3359 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3362 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3363 CS46XX_SECONDARY_CODEC_INDEX);
3366 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3367 CS46XX_SECONDARY_CODEC_INDEX);
3369 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3370 valid_slots |= 0x200;
3371 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3373 if ( cs46xx_wait_for_fifo(chip,1) ) {
3374 dev_dbg(chip->card->dev, "FIFO is busy\n");
3380 * Fill slots 12 with the correct value for the GPIO pins.
3382 for(idx = 0x90; idx <= 0x9F; idx++) {
3384 * Initialize the fifo so that bits 7 and 8 are on.
3386 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3387 * the left. 0x1800 corresponds to bits 7 and 8.
3389 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3392 * Wait for command to complete
3394 if ( cs46xx_wait_for_fifo(chip,200) ) {
3395 dev_dbg(chip->card->dev,
3396 "failed waiting for FIFO at addr (%02X)\n",
3403 * Write the serial port FIFO index.
3405 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3408 * Tell the serial port to load the new value into the FIFO location.
3410 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3413 /* wait for last command to complete */
3414 cs46xx_wait_for_fifo(chip,200);
3417 * Now, if we powered up the devices, then power them back down again.
3418 * This is kinda ugly, but should never happen.
3421 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3431 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3433 /* Manage the EAPD bit on the Crystal 4297
3434 and the Analog AD1885 */
3436 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3437 int old = chip->amplifier;
3441 chip->amplifier += change;
3442 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3443 CS46XX_PRIMARY_CODEC_INDEX);
3445 if (chip->amplifier) {
3446 /* Turn the EAPD amp on */
3449 /* Turn the EAPD amp off */
3453 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3454 CS46XX_PRIMARY_CODEC_INDEX);
3455 if (chip->eapd_switch)
3456 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3457 &chip->eapd_switch->id);
3460 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3461 if (chip->amplifier && !old) {
3462 voyetra_setup_eapd_slot(chip);
3467 static void hercules_init(struct snd_cs46xx *chip)
3469 /* default: AMP off, and SPDIF input optical */
3470 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3471 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3476 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3478 static void amp_hercules(struct snd_cs46xx *chip, int change)
3480 int old = chip->amplifier;
3481 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3482 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3484 chip->amplifier += change;
3485 if (chip->amplifier && !old) {
3486 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3488 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3489 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3490 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3491 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3492 } else if (old && !chip->amplifier) {
3493 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3494 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3495 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3499 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3501 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3503 /* Enable SPDIF out */
3504 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3505 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3508 static void hercules_mixer_init (struct snd_cs46xx *chip)
3510 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3513 struct snd_card *card = chip->card;
3516 /* set EGPIO to default */
3517 hercules_init(chip);
3519 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3521 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3522 if (chip->in_suspend)
3525 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3526 struct snd_kcontrol *kctl;
3528 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3529 if ((err = snd_ctl_add(card, kctl)) < 0) {
3531 "failed to initialize Hercules mixer (%d)\n",
3545 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3547 chip->amplifier += change;
3549 if (chip->amplifier) {
3550 /* Switch the GPIO pins 7 and 8 to open drain */
3551 snd_cs46xx_codec_write(chip, 0x4C,
3552 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3553 snd_cs46xx_codec_write(chip, 0x4E,
3554 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3555 /* Now wake the AMP (this might be backwards) */
3556 snd_cs46xx_codec_write(chip, 0x54,
3557 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3559 snd_cs46xx_codec_write(chip, 0x54,
3560 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3567 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3568 * whenever we need to beat on the chip.
3570 * The original idea and code for this hack comes from David Kaiser at
3571 * Linuxcare. Perhaps one day Crystal will document their chips well
3572 * enough to make them useful.
3575 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3579 if (!chip->acpi_port)
3582 chip->amplifier += change;
3584 /* Read ACPI port */
3585 nval = control = inw(chip->acpi_port + 0x10);
3587 /* Flip CLKRUN off while running */
3588 if (! chip->amplifier)
3592 if (nval != control)
3593 outw(nval, chip->acpi_port + 0x10);
3598 * detect intel piix4
3600 static void clkrun_init(struct snd_cs46xx *chip)
3602 struct pci_dev *pdev;
3605 chip->acpi_port = 0;
3607 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3608 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3610 return; /* Not a thinkpad thats for sure */
3612 /* Find the control port */
3613 pci_read_config_byte(pdev, 0x41, &pp);
3614 chip->acpi_port = pp << 8;
3628 void (*init)(struct snd_cs46xx *);
3629 void (*amp)(struct snd_cs46xx *, int);
3630 void (*active)(struct snd_cs46xx *, int);
3631 void (*mixer_init)(struct snd_cs46xx *);
3634 static struct cs_card_type cards[] = {
3638 .name = "Genius Soundmaker 128 value",
3639 /* nothing special */
3646 .mixer_init = voyetra_mixer_init,
3651 .name = "Mitac MI6020/21",
3654 /* Hercules Game Theatre XP */
3656 .vendor = 0x14af, /* Guillemot Corporation */
3658 .name = "Hercules Game Theatre XP",
3659 .amp = amp_hercules,
3660 .mixer_init = hercules_mixer_init,
3665 .name = "Hercules Game Theatre XP",
3666 .amp = amp_hercules,
3667 .mixer_init = hercules_mixer_init,
3672 .name = "Hercules Game Theatre XP",
3673 .amp = amp_hercules,
3674 .mixer_init = hercules_mixer_init,
3680 .name = "Hercules Game Theatre XP",
3681 .amp = amp_hercules,
3682 .mixer_init = hercules_mixer_init,
3687 .name = "Hercules Game Theatre XP",
3688 .amp = amp_hercules,
3689 .mixer_init = hercules_mixer_init,
3694 .name = "Hercules Game Theatre XP",
3695 .amp = amp_hercules,
3696 .mixer_init = hercules_mixer_init,
3698 /* Herculess Fortissimo */
3702 .name = "Hercules Gamesurround Fortissimo II",
3707 .name = "Hercules Gamesurround Fortissimo III 7.1",
3713 .name = "Terratec DMX XFire 1024",
3718 .name = "Terratec SiXPack 5.1",
3720 /* Not sure if the 570 needs the clkrun hack */
3722 .vendor = PCI_VENDOR_ID_IBM,
3724 .name = "Thinkpad 570",
3725 .init = clkrun_init,
3726 .active = clkrun_hack,
3729 .vendor = PCI_VENDOR_ID_IBM,
3731 .name = "Thinkpad 600X/A20/T20",
3732 .init = clkrun_init,
3733 .active = clkrun_hack,
3736 .vendor = PCI_VENDOR_ID_IBM,
3738 .name = "Thinkpad 600E (unsupported)",
3747 #ifdef CONFIG_PM_SLEEP
3748 static unsigned int saved_regs[] = {
3756 static int snd_cs46xx_suspend(struct device *dev)
3758 struct snd_card *card = dev_get_drvdata(dev);
3759 struct snd_cs46xx *chip = card->private_data;
3762 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3763 chip->in_suspend = 1;
3764 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3765 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3767 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3768 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3770 /* save some registers */
3771 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3772 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3774 amp_saved = chip->amplifier;
3776 chip->amplifier_ctrl(chip, -chip->amplifier);
3777 snd_cs46xx_hw_stop(chip);
3778 /* disable CLKRUN */
3779 chip->active_ctrl(chip, -chip->amplifier);
3780 chip->amplifier = amp_saved; /* restore the status */
3784 static int snd_cs46xx_resume(struct device *dev)
3786 struct snd_card *card = dev_get_drvdata(dev);
3787 struct snd_cs46xx *chip = card->private_data;
3789 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3794 amp_saved = chip->amplifier;
3795 chip->amplifier = 0;
3796 chip->active_ctrl(chip, 1); /* force to on */
3798 snd_cs46xx_chip_init(chip);
3800 snd_cs46xx_reset(chip);
3801 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3802 cs46xx_dsp_resume(chip);
3803 /* restore some registers */
3804 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3805 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3807 snd_cs46xx_download_image(chip);
3811 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3812 chip->ac97_general_purpose);
3813 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3814 chip->ac97_powerdown);
3816 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3817 chip->ac97_powerdown);
3821 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3822 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3827 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3828 chip->capt.ctl = tmp & 0x0000ffff;
3829 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3833 /* reset playback/capture */
3834 snd_cs46xx_set_play_sample_rate(chip, 8000);
3835 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3836 snd_cs46xx_proc_start(chip);
3838 cs46xx_enable_stream_irqs(chip);
3841 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3843 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3844 chip->amplifier = amp_saved;
3845 chip->in_suspend = 0;
3846 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3850 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3851 #endif /* CONFIG_PM_SLEEP */
3857 int snd_cs46xx_create(struct snd_card *card,
3858 struct pci_dev *pci,
3859 int external_amp, int thinkpad,
3860 struct snd_cs46xx **rchip)
3862 struct snd_cs46xx *chip;
3864 struct snd_cs46xx_region *region;
3865 struct cs_card_type *cp;
3866 u16 ss_card, ss_vendor;
3867 static const struct snd_device_ops ops = {
3868 .dev_free = snd_cs46xx_dev_free,
3873 /* enable PCI device */
3874 if ((err = pci_enable_device(pci)) < 0)
3877 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3879 pci_disable_device(pci);
3882 spin_lock_init(&chip->reg_lock);
3883 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3884 mutex_init(&chip->spos_mutex);
3889 chip->ba0_addr = pci_resource_start(pci, 0);
3890 chip->ba1_addr = pci_resource_start(pci, 1);
3891 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3892 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3893 dev_err(chip->card->dev,
3894 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3895 chip->ba0_addr, chip->ba1_addr);
3896 snd_cs46xx_free(chip);
3900 region = &chip->region.name.ba0;
3901 strcpy(region->name, "CS46xx_BA0");
3902 region->base = chip->ba0_addr;
3903 region->size = CS46XX_BA0_SIZE;
3905 region = &chip->region.name.data0;
3906 strcpy(region->name, "CS46xx_BA1_data0");
3907 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3908 region->size = CS46XX_BA1_DATA0_SIZE;
3910 region = &chip->region.name.data1;
3911 strcpy(region->name, "CS46xx_BA1_data1");
3912 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3913 region->size = CS46XX_BA1_DATA1_SIZE;
3915 region = &chip->region.name.pmem;
3916 strcpy(region->name, "CS46xx_BA1_pmem");
3917 region->base = chip->ba1_addr + BA1_SP_PMEM;
3918 region->size = CS46XX_BA1_PRG_SIZE;
3920 region = &chip->region.name.reg;
3921 strcpy(region->name, "CS46xx_BA1_reg");
3922 region->base = chip->ba1_addr + BA1_SP_REG;
3923 region->size = CS46XX_BA1_REG_SIZE;
3925 /* set up amp and clkrun hack */
3926 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3927 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3929 for (cp = &cards[0]; cp->name; cp++) {
3930 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3931 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3934 chip->amplifier_ctrl = cp->amp;
3935 chip->active_ctrl = cp->active;
3936 chip->mixer_init = cp->mixer_init;
3945 dev_info(chip->card->dev,
3946 "Crystal EAPD support forced on.\n");
3947 chip->amplifier_ctrl = amp_voyetra;
3951 dev_info(chip->card->dev,
3952 "Activating CLKRUN hack for Thinkpad.\n");
3953 chip->active_ctrl = clkrun_hack;
3957 if (chip->amplifier_ctrl == NULL)
3958 chip->amplifier_ctrl = amp_none;
3959 if (chip->active_ctrl == NULL)
3960 chip->active_ctrl = amp_none;
3962 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3964 pci_set_master(pci);
3966 for (idx = 0; idx < 5; idx++) {
3967 region = &chip->region.idx[idx];
3968 if ((region->resource = request_mem_region(region->base, region->size,
3969 region->name)) == NULL) {
3970 dev_err(chip->card->dev,
3971 "unable to request memory region 0x%lx-0x%lx\n",
3972 region->base, region->base + region->size - 1);
3973 snd_cs46xx_free(chip);
3976 region->remap_addr = ioremap_nocache(region->base, region->size);
3977 if (region->remap_addr == NULL) {
3978 dev_err(chip->card->dev,
3979 "%s ioremap problem\n", region->name);
3980 snd_cs46xx_free(chip);
3985 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3986 KBUILD_MODNAME, chip)) {
3987 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3988 snd_cs46xx_free(chip);
3991 chip->irq = pci->irq;
3992 card->sync_irq = chip->irq;
3994 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3995 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3996 if (chip->dsp_spos_instance == NULL) {
3997 snd_cs46xx_free(chip);
4002 err = snd_cs46xx_chip_init(chip);
4004 snd_cs46xx_free(chip);
4008 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4009 snd_cs46xx_free(chip);
4013 snd_cs46xx_proc_init(card, chip);
4015 #ifdef CONFIG_PM_SLEEP
4016 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4017 sizeof(*chip->saved_regs),
4019 if (!chip->saved_regs) {
4020 snd_cs46xx_free(chip);
4025 chip->active_ctrl(chip, -1); /* disable CLKRUN */