sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer control.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <linux/delay.h>
  49 #include <linux/pci.h>
  50 #include <linux/pm.h>
  51 #include <linux/init.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/slab.h>
  54 #include <linux/gameport.h>
  55 #include <linux/mutex.h>
  56 #include <linux/export.h>
  57 #include <linux/module.h>
  58 #include <linux/firmware.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include <sound/core.h>
  62 #include <sound/control.h>
  63 #include <sound/info.h>
  64 #include <sound/pcm.h>
  65 #include <sound/pcm_params.h>
  66 #include "cs46xx.h"
  67
  68 #include <asm/io.h>
  69
  70 #include "cs46xx_lib.h"
  71 #include "dsp_spos.h"
  72
  73 static void amp_voyetra(struct snd_cs46xx *chip, int change);
  74
  75 #ifdef CONFIG_SND_CS46XX_NEW_DSP
  76 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  78 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  80 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  81 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  82 #endif
  83
  84 static struct snd_pcm_ops snd_cs46xx_playback_ops;
  85 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  86 static struct snd_pcm_ops snd_cs46xx_capture_ops;
  87 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  88
  89 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  90                                             unsigned short reg,
  91                                             int codec_index)
  92 {
  93         int count;
  94         unsigned short result,tmp;
  95         u32 offset = 0;
  96
  97         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
  98                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
  99                 return 0xffff;
 100
 101         chip->active_ctrl(chip, 1);
 102
 103         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
 104                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
 105
 106         /*
 107          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 108          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 109          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
 110          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 111          *  5. if DCV not cleared, break and return error
 112          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 113          */
 114
 115         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 116
 117         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 118         if ((tmp & ACCTL_VFRM) == 0) {
 119                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
 120                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 121                 msleep(50);
 122                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 123                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 124
 125         }
 126
 127         /*
 128          *  Setup the AC97 control registers on the CS461x to send the
 129          *  appropriate command to the AC97 to perform the read.
 130          *  ACCAD = Command Address Register = 46Ch
 131          *  ACCDA = Command Data Register = 470h
 132          *  ACCTL = Control Register = 460h
 133          *  set DCV - will clear when process completed
 134          *  set CRW - Read command
 135          *  set VFRM - valid frame enabled
 136          *  set ESYN - ASYNC generation enabled
 137          *  set RSTN - ARST# inactive, AC97 codec not reset
 138          */
 139
 140         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 141         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 142         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 143                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 144                                    ACCTL_VFRM | ACCTL_ESYN |
 145                                    ACCTL_RSTN);
 146                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 147                                    ACCTL_VFRM | ACCTL_ESYN |
 148                                    ACCTL_RSTN);
 149         } else {
 150                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 151                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 152                                    ACCTL_RSTN);
 153         }
 154
 155         /*
 156          *  Wait for the read to occur.
 157          */
 158         for (count = 0; count < 1000; count++) {
 159                 /*
 160                  *  First, we want to wait for a short time.
 161                  */
 162                 udelay(10);
 163                 /*
 164                  *  Now, check to see if the read has completed.
 165                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 166                  */
 167                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 168                         goto ok1;
 169         }
 170
 171         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 172         result = 0xffff;
 173         goto end;
 174
 175  ok1:
 176         /*
 177          *  Wait for the valid status bit to go active.
 178          */
 179         for (count = 0; count < 100; count++) {
 180                 /*
 181                  *  Read the AC97 status register.
 182                  *  ACSTS = Status Register = 464h
 183                  *  VSTS - Valid Status
 184                  */
 185                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 186                         goto ok2;
 187                 udelay(10);
 188         }
 189
 190         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 191         result = 0xffff;
 192         goto end;
 193
 194  ok2:
 195         /*
 196          *  Read the data returned from the AC97 register.
 197          *  ACSDA = Status Data Register = 474h
 198          */
 199 #if 0
 200         printk(KERN_DEBUG "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 201                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 202                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 203 #endif
 204
 205         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 206         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 207  end:
 208         chip->active_ctrl(chip, -1);
 209         return result;
 210 }
 211
 212 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
 213                                             unsigned short reg)
 214 {
 215         struct snd_cs46xx *chip = ac97->private_data;
 216         unsigned short val;
 217         int codec_index = ac97->num;
 218
 219         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 220                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 221                 return 0xffff;
 222
 223         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 224
 225         return val;
 226 }
 227
 228
 229 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
 230                                    unsigned short reg,
 231                                    unsigned short val,
 232                                    int codec_index)
 233 {
 234         int count;
 235
 236         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 237                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 238                 return;
 239
 240         chip->active_ctrl(chip, 1);
 241
 242         /*
 243          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 244          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 245          *  3. Write ACCTL = Control Register = 460h for initiating the write
 246          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 247          *  5. if DCV not cleared, break and return error
 248          */
 249
 250         /*
 251          *  Setup the AC97 control registers on the CS461x to send the
 252          *  appropriate command to the AC97 to perform the read.
 253          *  ACCAD = Command Address Register = 46Ch
 254          *  ACCDA = Command Data Register = 470h
 255          *  ACCTL = Control Register = 460h
 256          *  set DCV - will clear when process completed
 257          *  reset CRW - Write command
 258          *  set VFRM - valid frame enabled
 259          *  set ESYN - ASYNC generation enabled
 260          *  set RSTN - ARST# inactive, AC97 codec not reset
 261          */
 262         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 263         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 264         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 265
 266         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 267                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 268                                    ACCTL_ESYN | ACCTL_RSTN);
 269                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 270                                    ACCTL_ESYN | ACCTL_RSTN);
 271         } else {
 272                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 273                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 274         }
 275
 276         for (count = 0; count < 4000; count++) {
 277                 /*
 278                  *  First, we want to wait for a short time.
 279                  */
 280                 udelay(10);
 281                 /*
 282                  *  Now, check to see if the write has completed.
 283                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 284                  */
 285                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 286                         goto end;
 287                 }
 288         }
 289         snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 290  end:
 291         chip->active_ctrl(chip, -1);
 292 }
 293
 294 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
 295                                    unsigned short reg,
 296                                    unsigned short val)
 297 {
 298         struct snd_cs46xx *chip = ac97->private_data;
 299         int codec_index = ac97->num;
 300
 301         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 302                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 303                 return;
 304
 305         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 306 }
 307
 308
 309 /*
 310  *  Chip initialization
 311  */
 312
 313 int snd_cs46xx_download(struct snd_cs46xx *chip,
 314                         u32 *src,
 315                         unsigned long offset,
 316                         unsigned long len)
 317 {
 318         void __iomem *dst;
 319         unsigned int bank = offset >> 16;
 320         offset = offset & 0xffff;
 321
 322         if (snd_BUG_ON((offset & 3) || (len & 3)))
 323                 return -EINVAL;
 324         dst = chip->region.idx[bank+1].remap_addr + offset;
 325         len /= sizeof(u32);
 326
 327         /* writel already converts 32-bit value to right endianess */
 328         while (len-- > 0) {
 329                 writel(*src++, dst);
 330                 dst += sizeof(u32);
 331         }
 332         return 0;
 333 }
 334
 335 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
 336 {
 337 #ifdef __LITTLE_ENDIAN
 338         memcpy(dst, src, len);
 339 #else
 340         u32 *_dst = dst;
 341         const __le32 *_src = src;
 342         len /= 4;
 343         while (len-- > 0)
 344                 *_dst++ = le32_to_cpu(*_src++);
 345 #endif
 346 }
 347
 348 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 349
 350 static const char *module_names[CS46XX_DSP_MODULES] = {
 351         "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
 352 };
 353
 354 MODULE_FIRMWARE("cs46xx/cwc4630");
 355 MODULE_FIRMWARE("cs46xx/cwcasync");
 356 MODULE_FIRMWARE("cs46xx/cwcsnoop");
 357 MODULE_FIRMWARE("cs46xx/cwcbinhack");
 358 MODULE_FIRMWARE("cs46xx/cwcdma");
 359
 360 static void free_module_desc(struct dsp_module_desc *module)
 361 {
 362         if (!module)
 363                 return;
 364         kfree(module->module_name);
 365         kfree(module->symbol_table.symbols);
 366         if (module->segments) {
 367                 int i;
 368                 for (i = 0; i < module->nsegments; i++)
 369                         kfree(module->segments[i].data);
 370                 kfree(module->segments);
 371         }
 372 }
 373
 374 /* firmware binary format:
 375  * le32 nsymbols;
 376  * struct {
 377  *      le32 address;
 378  *      char symbol_name[DSP_MAX_SYMBOL_NAME];
 379  *      le32 symbol_type;
 380  * } symbols[nsymbols];
 381  * le32 nsegments;
 382  * struct {
 383  *      le32 segment_type;
 384  *      le32 offset;
 385  *      le32 size;
 386  *      le32 data[size];
 387  * } segments[nsegments];
 388  */
 389
 390 static int load_firmware(struct snd_cs46xx *chip,
 391                          struct dsp_module_desc **module_ret,
 392                          const char *fw_name)
 393 {
 394         int i, err;
 395         unsigned int nums, fwlen, fwsize;
 396         const __le32 *fwdat;
 397         struct dsp_module_desc *module = NULL;
 398         const struct firmware *fw;
 399         char fw_path[32];
 400
 401         sprintf(fw_path, "cs46xx/%s", fw_name);
 402         err = request_firmware(&fw, fw_path, &chip->pci->dev);
 403         if (err < 0)
 404                 return err;
 405         fwsize = fw->size / 4;
 406         if (fwsize < 2) {
 407                 err = -EINVAL;
 408                 goto error;
 409         }
 410
 411         err = -ENOMEM;
 412         module = kzalloc(sizeof(*module), GFP_KERNEL);
 413         if (!module)
 414                 goto error;
 415         module->module_name = kstrdup(fw_name, GFP_KERNEL);
 416         if (!module->module_name)
 417                 goto error;
 418
 419         fwlen = 0;
 420         fwdat = (const __le32 *)fw->data;
 421         nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
 422         if (nums >= 40)
 423                 goto error_inval;
 424         module->symbol_table.symbols =
 425                 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
 426         if (!module->symbol_table.symbols)
 427                 goto error;
 428         for (i = 0; i < nums; i++) {
 429                 struct dsp_symbol_entry *entry =
 430                         &module->symbol_table.symbols[i];
 431                 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
 432                         goto error_inval;
 433                 entry->address = le32_to_cpu(fwdat[fwlen++]);
 434                 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
 435                 fwlen += DSP_MAX_SYMBOL_NAME / 4;
 436                 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
 437         }
 438
 439         if (fwlen >= fwsize)
 440                 goto error_inval;
 441         nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
 442         if (nums > 10)
 443                 goto error_inval;
 444         module->segments =
 445                 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
 446         if (!module->segments)
 447                 goto error;
 448         for (i = 0; i < nums; i++) {
 449                 struct dsp_segment_desc *entry = &module->segments[i];
 450                 if (fwlen + 3 > fwsize)
 451                         goto error_inval;
 452                 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
 453                 entry->offset = le32_to_cpu(fwdat[fwlen++]);
 454                 entry->size = le32_to_cpu(fwdat[fwlen++]);
 455                 if (fwlen + entry->size > fwsize)
 456                         goto error_inval;
 457                 entry->data = kmalloc(entry->size * 4, GFP_KERNEL);
 458                 if (!entry->data)
 459                         goto error;
 460                 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
 461                 fwlen += entry->size;
 462         }
 463
 464         *module_ret = module;
 465         release_firmware(fw);
 466         return 0;
 467
 468  error_inval:
 469         err = -EINVAL;
 470  error:
 471         free_module_desc(module);
 472         release_firmware(fw);
 473         return err;
 474 }
 475
 476 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
 477                          unsigned long offset,
 478                          unsigned long len)
 479 {
 480         void __iomem *dst;
 481         unsigned int bank = offset >> 16;
 482         offset = offset & 0xffff;
 483
 484         if (snd_BUG_ON((offset & 3) || (len & 3)))
 485                 return -EINVAL;
 486         dst = chip->region.idx[bank+1].remap_addr + offset;
 487         len /= sizeof(u32);
 488
 489         /* writel already converts 32-bit value to right endianess */
 490         while (len-- > 0) {
 491                 writel(0, dst);
 492                 dst += sizeof(u32);
 493         }
 494         return 0;
 495 }
 496
 497 #else /* old DSP image */
 498
 499 struct ba1_struct {
 500         struct {
 501                 u32 offset;
 502                 u32 size;
 503         } memory[BA1_MEMORY_COUNT];
 504         u32 map[BA1_DWORD_SIZE];
 505 };
 506
 507 MODULE_FIRMWARE("cs46xx/ba1");
 508
 509 static int load_firmware(struct snd_cs46xx *chip)
 510 {
 511         const struct firmware *fw;
 512         int i, size, err;
 513
 514         err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
 515         if (err < 0)
 516                 return err;
 517         if (fw->size != sizeof(*chip->ba1)) {
 518                 err = -EINVAL;
 519                 goto error;
 520         }
 521
 522         chip->ba1 = vmalloc(sizeof(*chip->ba1));
 523         if (!chip->ba1) {
 524                 err = -ENOMEM;
 525                 goto error;
 526         }
 527
 528         memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
 529
 530         /* sanity check */
 531         size = 0;
 532         for (i = 0; i < BA1_MEMORY_COUNT; i++)
 533                 size += chip->ba1->memory[i].size;
 534         if (size > BA1_DWORD_SIZE * 4)
 535                 err = -EINVAL;
 536
 537  error:
 538         release_firmware(fw);
 539         return err;
 540 }
 541
 542 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
 543 {
 544         int idx, err;
 545         unsigned int offset = 0;
 546         struct ba1_struct *ba1 = chip->ba1;
 547
 548         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 549                 err = snd_cs46xx_download(chip,
 550                                           &ba1->map[offset],
 551                                           ba1->memory[idx].offset,
 552                                           ba1->memory[idx].size);
 553                 if (err < 0)
 554                         return err;
 555                 offset += ba1->memory[idx].size >> 2;
 556         }
 557         return 0;
 558 }
 559 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 560
 561 /*
 562  *  Chip reset
 563  */
 564
 565 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
 566 {
 567         int idx;
 568
 569         /*
 570          *  Write the reset bit of the SP control register.
 571          */
 572         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 573
 574         /*
 575          *  Write the control register.
 576          */
 577         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 578
 579         /*
 580          *  Clear the trap registers.
 581          */
 582         for (idx = 0; idx < 8; idx++) {
 583                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 584                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 585         }
 586         snd_cs46xx_poke(chip, BA1_DREG, 0);
 587
 588         /*
 589          *  Set the frame timer to reflect the number of cycles per frame.
 590          */
 591         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 592 }
 593
 594 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
 595 {
 596         u32 i, status = 0;
 597         /*
 598          * Make sure the previous FIFO write operation has completed.
 599          */
 600         for(i = 0; i < 50; i++){
 601                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 602
 603                 if( !(status & SERBST_WBSY) )
 604                         break;
 605
 606                 mdelay(retry_timeout);
 607         }
 608
 609         if(status & SERBST_WBSY) {
 610                 snd_printk(KERN_ERR "cs46xx: failure waiting for "
 611                            "FIFO command to complete\n");
 612                 return -EINVAL;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
 619 {
 620         int idx, powerdown = 0;
 621         unsigned int tmp;
 622
 623         /*
 624          *  See if the devices are powered down.  If so, we must power them up first
 625          *  or they will not respond.
 626          */
 627         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 628         if (!(tmp & CLKCR1_SWCE)) {
 629                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 630                 powerdown = 1;
 631         }
 632
 633         /*
 634          *  We want to clear out the serial port FIFOs so we don't end up playing
 635          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 636          *  with zero (silence).
 637          */
 638         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 639
 640         /*
 641          *  Fill all 256 sample FIFO locations.
 642          */
 643         for (idx = 0; idx < 0xFF; idx++) {
 644                 /*
 645                  *  Make sure the previous FIFO write operation has completed.
 646                  */
 647                 if (cs46xx_wait_for_fifo(chip,1)) {
 648                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 649
 650                         if (powerdown)
 651                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 652
 653                         break;
 654                 }
 655                 /*
 656                  *  Write the serial port FIFO index.
 657                  */
 658                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 659                 /*
 660                  *  Tell the serial port to load the new value into the FIFO location.
 661                  */
 662                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 663         }
 664         /*
 665          *  Now, if we powered up the devices, then power them back down again.
 666          *  This is kinda ugly, but should never happen.
 667          */
 668         if (powerdown)
 669                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 670 }
 671
 672 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
 673 {
 674         int cnt;
 675
 676         /*
 677          *  Set the frame timer to reflect the number of cycles per frame.
 678          */
 679         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 680         /*
 681          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 682          *  the SP control register.
 683          */
 684         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 685         /*
 686          *  Wait until the run at frame bit resets itself in the SP control
 687          *  register.
 688          */
 689         for (cnt = 0; cnt < 25; cnt++) {
 690                 udelay(50);
 691                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 692                         break;
 693         }
 694
 695         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 696                 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
 697 }
 698
 699 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
 700 {
 701         /*
 702          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 703          *  the SP control register.
 704          */
 705         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 706 }
 707
 708 /*
 709  *  Sample rate routines
 710  */
 711
 712 #define GOF_PER_SEC 200
 713
 714 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 715 {
 716         unsigned long flags;
 717         unsigned int tmp1, tmp2;
 718         unsigned int phiIncr;
 719         unsigned int correctionPerGOF, correctionPerSec;
 720
 721         /*
 722          *  Compute the values used to drive the actual sample rate conversion.
 723          *  The following formulas are being computed, using inline assembly
 724          *  since we need to use 64 bit arithmetic to compute the values:
 725          *
 726          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 727          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 728          *                                   GOF_PER_SEC)
 729          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 730          *                       GOF_PER_SEC * correctionPerGOF
 731          *
 732          *  i.e.
 733          *
 734          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 735          *  correctionPerGOF:correctionPerSec =
 736          *      dividend:remainder(ulOther / GOF_PER_SEC)
 737          */
 738         tmp1 = rate << 16;
 739         phiIncr = tmp1 / 48000;
 740         tmp1 -= phiIncr * 48000;
 741         tmp1 <<= 10;
 742         phiIncr <<= 10;
 743         tmp2 = tmp1 / 48000;
 744         phiIncr += tmp2;
 745         tmp1 -= tmp2 * 48000;
 746         correctionPerGOF = tmp1 / GOF_PER_SEC;
 747         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 748         correctionPerSec = tmp1;
 749
 750         /*
 751          *  Fill in the SampleRateConverter control block.
 752          */
 753         spin_lock_irqsave(&chip->reg_lock, flags);
 754         snd_cs46xx_poke(chip, BA1_PSRC,
 755           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 756         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 757         spin_unlock_irqrestore(&chip->reg_lock, flags);
 758 }
 759
 760 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 761 {
 762         unsigned long flags;
 763         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 764         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 765         unsigned int frameGroupLength, cnt;
 766
 767         /*
 768          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 769          *  Correct the value if an attempt is made to stray outside that limit.
 770          */
 771         if ((rate * 9) < 48000)
 772                 rate = 48000 / 9;
 773
 774         /*
 775          *  We can not capture at at rate greater than the Input Rate (48000).
 776          *  Return an error if an attempt is made to stray outside that limit.
 777          */
 778         if (rate > 48000)
 779                 rate = 48000;
 780
 781         /*
 782          *  Compute the values used to drive the actual sample rate conversion.
 783          *  The following formulas are being computed, using inline assembly
 784          *  since we need to use 64 bit arithmetic to compute the values:
 785          *
 786          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 787          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 788          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 789          *                                GOF_PER_SEC)
 790          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 791          *                          GOF_PER_SEC * correctionPerGOF
 792          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 793          *
 794          * i.e.
 795          *
 796          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 797          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 798          *     correctionPerGOF:correctionPerSec =
 799          *          dividend:remainder(ulOther / GOF_PER_SEC)
 800          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 801          */
 802
 803         tmp1 = rate << 16;
 804         coeffIncr = tmp1 / 48000;
 805         tmp1 -= coeffIncr * 48000;
 806         tmp1 <<= 7;
 807         coeffIncr <<= 7;
 808         coeffIncr += tmp1 / 48000;
 809         coeffIncr ^= 0xFFFFFFFF;
 810         coeffIncr++;
 811         tmp1 = 48000 << 16;
 812         phiIncr = tmp1 / rate;
 813         tmp1 -= phiIncr * rate;
 814         tmp1 <<= 10;
 815         phiIncr <<= 10;
 816         tmp2 = tmp1 / rate;
 817         phiIncr += tmp2;
 818         tmp1 -= tmp2 * rate;
 819         correctionPerGOF = tmp1 / GOF_PER_SEC;
 820         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 821         correctionPerSec = tmp1;
 822         initialDelay = ((48000 * 24) + rate - 1) / rate;
 823
 824         /*
 825          *  Fill in the VariDecimate control block.
 826          */
 827         spin_lock_irqsave(&chip->reg_lock, flags);
 828         snd_cs46xx_poke(chip, BA1_CSRC,
 829                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 830         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 831         snd_cs46xx_poke(chip, BA1_CD,
 832                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 833         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 834         spin_unlock_irqrestore(&chip->reg_lock, flags);
 835
 836         /*
 837          *  Figure out the frame group length for the write back task.  Basically,
 838          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 839          *  the output sample rate.
 840          */
 841         frameGroupLength = 1;
 842         for (cnt = 2; cnt <= 64; cnt *= 2) {
 843                 if (((rate / cnt) * cnt) != rate)
 844                         frameGroupLength *= 2;
 845         }
 846         if (((rate / 3) * 3) != rate) {
 847                 frameGroupLength *= 3;
 848         }
 849         for (cnt = 5; cnt <= 125; cnt *= 5) {
 850                 if (((rate / cnt) * cnt) != rate)
 851                         frameGroupLength *= 5;
 852         }
 853
 854         /*
 855          * Fill in the WriteBack control block.
 856          */
 857         spin_lock_irqsave(&chip->reg_lock, flags);
 858         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 859         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 860         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 861         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 862         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 863         spin_unlock_irqrestore(&chip->reg_lock, flags);
 864 }
 865
 866 /*
 867  *  PCM part
 868  */
 869
 870 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
 871                                      struct snd_pcm_indirect *rec, size_t bytes)
 872 {
 873         struct snd_pcm_runtime *runtime = substream->runtime;
 874         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 875         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 876 }
 877
 878 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
 879 {
 880         struct snd_pcm_runtime *runtime = substream->runtime;
 881         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 882         snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
 883         return 0;
 884 }
 885
 886 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
 887                                      struct snd_pcm_indirect *rec, size_t bytes)
 888 {
 889         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 890         struct snd_pcm_runtime *runtime = substream->runtime;
 891         memcpy(runtime->dma_area + rec->sw_data,
 892                chip->capt.hw_buf.area + rec->hw_data, bytes);
 893 }
 894
 895 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
 896 {
 897         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 898         snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
 899         return 0;
 900 }
 901
 902 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
 903 {
 904         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 905         size_t ptr;
 906         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 907
 908         if (snd_BUG_ON(!cpcm->pcm_channel))
 909                 return -ENXIO;
 910
 911 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 912         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 913 #else
 914         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 915 #endif
 916         ptr -= cpcm->hw_buf.addr;
 917         return ptr >> cpcm->shift;
 918 }
 919
 920 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
 921 {
 922         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 923         size_t ptr;
 924         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 925
 926 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 927         if (snd_BUG_ON(!cpcm->pcm_channel))
 928                 return -ENXIO;
 929         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 930 #else
 931         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 932 #endif
 933         ptr -= cpcm->hw_buf.addr;
 934         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 935 }
 936
 937 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
 938 {
 939         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 940         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 941         return ptr >> chip->capt.shift;
 942 }
 943
 944 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
 945 {
 946         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 947         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 948         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 949 }
 950
 951 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
 952                                        int cmd)
 953 {
 954         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 955         /*struct snd_pcm_runtime *runtime = substream->runtime;*/
 956         int result = 0;
 957
 958 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 959         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 960         if (! cpcm->pcm_channel) {
 961                 return -ENXIO;
 962         }
 963 #endif
 964         switch (cmd) {
 965         case SNDRV_PCM_TRIGGER_START:
 966         case SNDRV_PCM_TRIGGER_RESUME:
 967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 968                 /* magic value to unmute PCM stream  playback volume */
 969                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 970                                        SCBVolumeCtrl) << 2, 0x80008000);
 971
 972                 if (cpcm->pcm_channel->unlinked)
 973                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 974
 975                 if (substream->runtime->periods != CS46XX_FRAGS)
 976                         snd_cs46xx_playback_transfer(substream);
 977 #else
 978                 spin_lock(&chip->reg_lock);
 979                 if (substream->runtime->periods != CS46XX_FRAGS)
 980                         snd_cs46xx_playback_transfer(substream);
 981                 { unsigned int tmp;
 982                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 983                 tmp &= 0x0000ffff;
 984                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 985                 }
 986                 spin_unlock(&chip->reg_lock);
 987 #endif
 988                 break;
 989         case SNDRV_PCM_TRIGGER_STOP:
 990         case SNDRV_PCM_TRIGGER_SUSPEND:
 991 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 992                 /* magic mute channel */
 993                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 994                                        SCBVolumeCtrl) << 2, 0xffffffff);
 995
 996                 if (!cpcm->pcm_channel->unlinked)
 997                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 998 #else
 999                 spin_lock(&chip->reg_lock);
1000                 { unsigned int tmp;
1001                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
1002                 tmp &= 0x0000ffff;
1003                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1004                 }
1005                 spin_unlock(&chip->reg_lock);
1006 #endif
1007                 break;
1008         default:
1009                 result = -EINVAL;
1010                 break;
1011         }
1012
1013         return result;
1014 }
1015
1016 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1017                                       int cmd)
1018 {
1019         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1020         unsigned int tmp;
1021         int result = 0;
1022
1023         spin_lock(&chip->reg_lock);
1024         switch (cmd) {
1025         case SNDRV_PCM_TRIGGER_START:
1026         case SNDRV_PCM_TRIGGER_RESUME:
1027                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028                 tmp &= 0xffff0000;
1029                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1030                 break;
1031         case SNDRV_PCM_TRIGGER_STOP:
1032         case SNDRV_PCM_TRIGGER_SUSPEND:
1033                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1034                 tmp &= 0xffff0000;
1035                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1036                 break;
1037         default:
1038                 result = -EINVAL;
1039                 break;
1040         }
1041         spin_unlock(&chip->reg_lock);
1042
1043         return result;
1044 }
1045
1046 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1047 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1048                                        int sample_rate)
1049 {
1050
1051         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1052         if ( cpcm->pcm_channel == NULL) {
1053                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1054                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1055                 if (cpcm->pcm_channel == NULL) {
1056                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
1057                         return -ENOMEM;
1058                 }
1059                 cpcm->pcm_channel->sample_rate = sample_rate;
1060         } else
1061         /* if sample rate is changed */
1062         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1063                 int unlinked = cpcm->pcm_channel->unlinked;
1064                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1065
1066                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1067                                                                          cpcm->hw_buf.addr,
1068                                                                          cpcm->pcm_channel_id)) == NULL) {
1069                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
1070                         return -ENOMEM;
1071                 }
1072
1073                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1074                 cpcm->pcm_channel->sample_rate = sample_rate;
1075         }
1076
1077         return 0;
1078 }
1079 #endif
1080
1081
1082 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1083                                          struct snd_pcm_hw_params *hw_params)
1084 {
1085         struct snd_pcm_runtime *runtime = substream->runtime;
1086         struct snd_cs46xx_pcm *cpcm;
1087         int err;
1088 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1089         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1090         int sample_rate = params_rate(hw_params);
1091         int period_size = params_period_bytes(hw_params);
1092 #endif
1093         cpcm = runtime->private_data;
1094
1095 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1096         if (snd_BUG_ON(!sample_rate))
1097                 return -ENXIO;
1098
1099         mutex_lock(&chip->spos_mutex);
1100
1101         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1102                 mutex_unlock(&chip->spos_mutex);
1103                 return -ENXIO;
1104         }
1105
1106         snd_BUG_ON(!cpcm->pcm_channel);
1107         if (!cpcm->pcm_channel) {
1108                 mutex_unlock(&chip->spos_mutex);
1109                 return -ENXIO;
1110         }
1111
1112
1113         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1114                  mutex_unlock(&chip->spos_mutex);
1115                  return -EINVAL;
1116          }
1117
1118         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
1119                      period_size, params_periods(hw_params),
1120                      params_buffer_bytes(hw_params));
1121 #endif
1122
1123         if (params_periods(hw_params) == CS46XX_FRAGS) {
1124                 if (runtime->dma_area != cpcm->hw_buf.area)
1125                         snd_pcm_lib_free_pages(substream);
1126                 runtime->dma_area = cpcm->hw_buf.area;
1127                 runtime->dma_addr = cpcm->hw_buf.addr;
1128                 runtime->dma_bytes = cpcm->hw_buf.bytes;
1129
1130
1131 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1132                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1133                         substream->ops = &snd_cs46xx_playback_ops;
1134                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1135                         substream->ops = &snd_cs46xx_playback_rear_ops;
1136                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1137                         substream->ops = &snd_cs46xx_playback_clfe_ops;
1138                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1139                         substream->ops = &snd_cs46xx_playback_iec958_ops;
1140                 } else {
1141                         snd_BUG();
1142                 }
1143 #else
1144                 substream->ops = &snd_cs46xx_playback_ops;
1145 #endif
1146
1147         } else {
1148                 if (runtime->dma_area == cpcm->hw_buf.area) {
1149                         runtime->dma_area = NULL;
1150                         runtime->dma_addr = 0;
1151                         runtime->dma_bytes = 0;
1152                 }
1153                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155                         mutex_unlock(&chip->spos_mutex);
1156 #endif
1157                         return err;
1158                 }
1159
1160 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1161                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1162                         substream->ops = &snd_cs46xx_playback_indirect_ops;
1163                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1164                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1165                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1166                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1167                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1168                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1169                 } else {
1170                         snd_BUG();
1171                 }
1172 #else
1173                 substream->ops = &snd_cs46xx_playback_indirect_ops;
1174 #endif
1175
1176         }
1177
1178 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1179         mutex_unlock(&chip->spos_mutex);
1180 #endif
1181
1182         return 0;
1183 }
1184
1185 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1186 {
1187         /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1188         struct snd_pcm_runtime *runtime = substream->runtime;
1189         struct snd_cs46xx_pcm *cpcm;
1190
1191         cpcm = runtime->private_data;
1192
1193         /* if play_back open fails, then this function
1194            is called and cpcm can actually be NULL here */
1195         if (!cpcm) return -ENXIO;
1196
1197         if (runtime->dma_area != cpcm->hw_buf.area)
1198                 snd_pcm_lib_free_pages(substream);
1199
1200         runtime->dma_area = NULL;
1201         runtime->dma_addr = 0;
1202         runtime->dma_bytes = 0;
1203
1204         return 0;
1205 }
1206
1207 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1208 {
1209         unsigned int tmp;
1210         unsigned int pfie;
1211         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1212         struct snd_pcm_runtime *runtime = substream->runtime;
1213         struct snd_cs46xx_pcm *cpcm;
1214
1215         cpcm = runtime->private_data;
1216
1217 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1218         if (snd_BUG_ON(!cpcm->pcm_channel))
1219                 return -ENXIO;
1220
1221         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1222         pfie &= ~0x0000f03f;
1223 #else
1224         /* old dsp */
1225         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1226         pfie &= ~0x0000f03f;
1227 #endif
1228
1229         cpcm->shift = 2;
1230         /* if to convert from stereo to mono */
1231         if (runtime->channels == 1) {
1232                 cpcm->shift--;
1233                 pfie |= 0x00002000;
1234         }
1235         /* if to convert from 8 bit to 16 bit */
1236         if (snd_pcm_format_width(runtime->format) == 8) {
1237                 cpcm->shift--;
1238                 pfie |= 0x00001000;
1239         }
1240         /* if to convert to unsigned */
1241         if (snd_pcm_format_unsigned(runtime->format))
1242                 pfie |= 0x00008000;
1243
1244         /* Never convert byte order when sample stream is 8 bit */
1245         if (snd_pcm_format_width(runtime->format) != 8) {
1246                 /* convert from big endian to little endian */
1247                 if (snd_pcm_format_big_endian(runtime->format))
1248                         pfie |= 0x00004000;
1249         }
1250
1251         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1252         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1253         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1254
1255 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1256
1257         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1258         tmp &= ~0x000003ff;
1259         tmp |= (4 << cpcm->shift) - 1;
1260         /* playback transaction count register */
1261         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1262
1263         /* playback format && interrupt enable */
1264         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1265 #else
1266         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1267         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1268         tmp &= ~0x000003ff;
1269         tmp |= (4 << cpcm->shift) - 1;
1270         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1271         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1272         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1273 #endif
1274
1275         return 0;
1276 }
1277
1278 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1279                                         struct snd_pcm_hw_params *hw_params)
1280 {
1281         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1282         struct snd_pcm_runtime *runtime = substream->runtime;
1283         int err;
1284
1285 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1286         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1287 #endif
1288         if (runtime->periods == CS46XX_FRAGS) {
1289                 if (runtime->dma_area != chip->capt.hw_buf.area)
1290                         snd_pcm_lib_free_pages(substream);
1291                 runtime->dma_area = chip->capt.hw_buf.area;
1292                 runtime->dma_addr = chip->capt.hw_buf.addr;
1293                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1294                 substream->ops = &snd_cs46xx_capture_ops;
1295         } else {
1296                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1297                         runtime->dma_area = NULL;
1298                         runtime->dma_addr = 0;
1299                         runtime->dma_bytes = 0;
1300                 }
1301                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1302                         return err;
1303                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1304         }
1305
1306         return 0;
1307 }
1308
1309 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1310 {
1311         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1312         struct snd_pcm_runtime *runtime = substream->runtime;
1313
1314         if (runtime->dma_area != chip->capt.hw_buf.area)
1315                 snd_pcm_lib_free_pages(substream);
1316         runtime->dma_area = NULL;
1317         runtime->dma_addr = 0;
1318         runtime->dma_bytes = 0;
1319
1320         return 0;
1321 }
1322
1323 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1324 {
1325         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1326         struct snd_pcm_runtime *runtime = substream->runtime;
1327
1328         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1329         chip->capt.shift = 2;
1330         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1331         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1332         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1333         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1334
1335         return 0;
1336 }
1337
1338 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1339 {
1340         struct snd_cs46xx *chip = dev_id;
1341         u32 status1;
1342 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1343         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1344         u32 status2;
1345         int i;
1346         struct snd_cs46xx_pcm *cpcm = NULL;
1347 #endif
1348
1349         /*
1350          *  Read the Interrupt Status Register to clear the interrupt
1351          */
1352         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1353         if ((status1 & 0x7fffffff) == 0) {
1354                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1355                 return IRQ_NONE;
1356         }
1357
1358 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1359         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1360
1361         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1362                 if (i <= 15) {
1363                         if ( status1 & (1 << i) ) {
1364                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1365                                         if (chip->capt.substream)
1366                                                 snd_pcm_period_elapsed(chip->capt.substream);
1367                                 } else {
1368                                         if (ins->pcm_channels[i].active &&
1369                                             ins->pcm_channels[i].private_data &&
1370                                             !ins->pcm_channels[i].unlinked) {
1371                                                 cpcm = ins->pcm_channels[i].private_data;
1372                                                 snd_pcm_period_elapsed(cpcm->substream);
1373                                         }
1374                                 }
1375                         }
1376                 } else {
1377                         if ( status2 & (1 << (i - 16))) {
1378                                 if (ins->pcm_channels[i].active &&
1379                                     ins->pcm_channels[i].private_data &&
1380                                     !ins->pcm_channels[i].unlinked) {
1381                                         cpcm = ins->pcm_channels[i].private_data;
1382                                         snd_pcm_period_elapsed(cpcm->substream);
1383                                 }
1384                         }
1385                 }
1386         }
1387
1388 #else
1389         /* old dsp */
1390         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1391                 if (chip->playback_pcm->substream)
1392                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1393         }
1394         if ((status1 & HISR_VC1) && chip->pcm) {
1395                 if (chip->capt.substream)
1396                         snd_pcm_period_elapsed(chip->capt.substream);
1397         }
1398 #endif
1399
1400         if ((status1 & HISR_MIDI) && chip->rmidi) {
1401                 unsigned char c;
1402
1403                 spin_lock(&chip->reg_lock);
1404                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1405                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1406                         if ((chip->midcr & MIDCR_RIE) == 0)
1407                                 continue;
1408                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1409                 }
1410                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1411                         if ((chip->midcr & MIDCR_TIE) == 0)
1412                                 break;
1413                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1414                                 chip->midcr &= ~MIDCR_TIE;
1415                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1416                                 break;
1417                         }
1418                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1419                 }
1420                 spin_unlock(&chip->reg_lock);
1421         }
1422         /*
1423          *  EOI to the PCI part....reenables interrupts
1424          */
1425         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1426
1427         return IRQ_HANDLED;
1428 }
1429
1430 static struct snd_pcm_hardware snd_cs46xx_playback =
1431 {
1432         .info =                 (SNDRV_PCM_INFO_MMAP |
1433                                  SNDRV_PCM_INFO_INTERLEAVED |
1434                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1435                                  /*SNDRV_PCM_INFO_RESUME*/),
1436         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1437                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1438                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1439         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1440         .rate_min =             5500,
1441         .rate_max =             48000,
1442         .channels_min =         1,
1443         .channels_max =         2,
1444         .buffer_bytes_max =     (256 * 1024),
1445         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1446         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1447         .periods_min =          CS46XX_FRAGS,
1448         .periods_max =          1024,
1449         .fifo_size =            0,
1450 };
1451
1452 static struct snd_pcm_hardware snd_cs46xx_capture =
1453 {
1454         .info =                 (SNDRV_PCM_INFO_MMAP |
1455                                  SNDRV_PCM_INFO_INTERLEAVED |
1456                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1457                                  /*SNDRV_PCM_INFO_RESUME*/),
1458         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1459         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1460         .rate_min =             5500,
1461         .rate_max =             48000,
1462         .channels_min =         2,
1463         .channels_max =         2,
1464         .buffer_bytes_max =     (256 * 1024),
1465         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1466         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1467         .periods_min =          CS46XX_FRAGS,
1468         .periods_max =          1024,
1469         .fifo_size =            0,
1470 };
1471
1472 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1473
1474 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1475
1476 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1477         .count = ARRAY_SIZE(period_sizes),
1478         .list = period_sizes,
1479         .mask = 0
1480 };
1481
1482 #endif
1483
1484 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1485 {
1486         kfree(runtime->private_data);
1487 }
1488
1489 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1490 {
1491         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1492         struct snd_cs46xx_pcm * cpcm;
1493         struct snd_pcm_runtime *runtime = substream->runtime;
1494
1495         cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1496         if (cpcm == NULL)
1497                 return -ENOMEM;
1498         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1499                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1500                 kfree(cpcm);
1501                 return -ENOMEM;
1502         }
1503
1504         runtime->hw = snd_cs46xx_playback;
1505         runtime->private_data = cpcm;
1506         runtime->private_free = snd_cs46xx_pcm_free_substream;
1507
1508         cpcm->substream = substream;
1509 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1510         mutex_lock(&chip->spos_mutex);
1511         cpcm->pcm_channel = NULL;
1512         cpcm->pcm_channel_id = pcm_channel_id;
1513
1514
1515         snd_pcm_hw_constraint_list(runtime, 0,
1516                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1517                                    &hw_constraints_period_sizes);
1518
1519         mutex_unlock(&chip->spos_mutex);
1520 #else
1521         chip->playback_pcm = cpcm; /* HACK */
1522 #endif
1523
1524         if (chip->accept_valid)
1525                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1526         chip->active_ctrl(chip, 1);
1527
1528         return 0;
1529 }
1530
1531 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1532 {
1533         snd_printdd("open front channel\n");
1534         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1535 }
1536
1537 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1538 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1539 {
1540         snd_printdd("open rear channel\n");
1541
1542         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1543 }
1544
1545 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1546 {
1547         snd_printdd("open center - LFE channel\n");
1548
1549         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1550 }
1551
1552 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1553 {
1554         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1555
1556         snd_printdd("open raw iec958 channel\n");
1557
1558         mutex_lock(&chip->spos_mutex);
1559         cs46xx_iec958_pre_open (chip);
1560         mutex_unlock(&chip->spos_mutex);
1561
1562         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1563 }
1564
1565 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1566
1567 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1568 {
1569         int err;
1570         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1571
1572         snd_printdd("close raw iec958 channel\n");
1573
1574         err = snd_cs46xx_playback_close(substream);
1575
1576         mutex_lock(&chip->spos_mutex);
1577         cs46xx_iec958_post_close (chip);
1578         mutex_unlock(&chip->spos_mutex);
1579
1580         return err;
1581 }
1582 #endif
1583
1584 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1585 {
1586         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1587
1588         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1589                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1590                 return -ENOMEM;
1591         chip->capt.substream = substream;
1592         substream->runtime->hw = snd_cs46xx_capture;
1593
1594         if (chip->accept_valid)
1595                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1596
1597         chip->active_ctrl(chip, 1);
1598
1599 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1600         snd_pcm_hw_constraint_list(substream->runtime, 0,
1601                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1602                                    &hw_constraints_period_sizes);
1603 #endif
1604         return 0;
1605 }
1606
1607 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1608 {
1609         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1610         struct snd_pcm_runtime *runtime = substream->runtime;
1611         struct snd_cs46xx_pcm * cpcm;
1612
1613         cpcm = runtime->private_data;
1614
1615         /* when playback_open fails, then cpcm can be NULL */
1616         if (!cpcm) return -ENXIO;
1617
1618 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1619         mutex_lock(&chip->spos_mutex);
1620         if (cpcm->pcm_channel) {
1621                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1622                 cpcm->pcm_channel = NULL;
1623         }
1624         mutex_unlock(&chip->spos_mutex);
1625 #else
1626         chip->playback_pcm = NULL;
1627 #endif
1628
1629         cpcm->substream = NULL;
1630         snd_dma_free_pages(&cpcm->hw_buf);
1631         chip->active_ctrl(chip, -1);
1632
1633         return 0;
1634 }
1635
1636 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1637 {
1638         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1639
1640         chip->capt.substream = NULL;
1641         snd_dma_free_pages(&chip->capt.hw_buf);
1642         chip->active_ctrl(chip, -1);
1643
1644         return 0;
1645 }
1646
1647 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1648 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1649         .open =                 snd_cs46xx_playback_open_rear,
1650         .close =                snd_cs46xx_playback_close,
1651         .ioctl =                snd_pcm_lib_ioctl,
1652         .hw_params =            snd_cs46xx_playback_hw_params,
1653         .hw_free =              snd_cs46xx_playback_hw_free,
1654         .prepare =              snd_cs46xx_playback_prepare,
1655         .trigger =              snd_cs46xx_playback_trigger,
1656         .pointer =              snd_cs46xx_playback_direct_pointer,
1657 };
1658
1659 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1660         .open =                 snd_cs46xx_playback_open_rear,
1661         .close =                snd_cs46xx_playback_close,
1662         .ioctl =                snd_pcm_lib_ioctl,
1663         .hw_params =            snd_cs46xx_playback_hw_params,
1664         .hw_free =              snd_cs46xx_playback_hw_free,
1665         .prepare =              snd_cs46xx_playback_prepare,
1666         .trigger =              snd_cs46xx_playback_trigger,
1667         .pointer =              snd_cs46xx_playback_indirect_pointer,
1668         .ack =                  snd_cs46xx_playback_transfer,
1669 };
1670
1671 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1672         .open =                 snd_cs46xx_playback_open_clfe,
1673         .close =                snd_cs46xx_playback_close,
1674         .ioctl =                snd_pcm_lib_ioctl,
1675         .hw_params =            snd_cs46xx_playback_hw_params,
1676         .hw_free =              snd_cs46xx_playback_hw_free,
1677         .prepare =              snd_cs46xx_playback_prepare,
1678         .trigger =              snd_cs46xx_playback_trigger,
1679         .pointer =              snd_cs46xx_playback_direct_pointer,
1680 };
1681
1682 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1683         .open =                 snd_cs46xx_playback_open_clfe,
1684         .close =                snd_cs46xx_playback_close,
1685         .ioctl =                snd_pcm_lib_ioctl,
1686         .hw_params =            snd_cs46xx_playback_hw_params,
1687         .hw_free =              snd_cs46xx_playback_hw_free,
1688         .prepare =              snd_cs46xx_playback_prepare,
1689         .trigger =              snd_cs46xx_playback_trigger,
1690         .pointer =              snd_cs46xx_playback_indirect_pointer,
1691         .ack =                  snd_cs46xx_playback_transfer,
1692 };
1693
1694 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1695         .open =                 snd_cs46xx_playback_open_iec958,
1696         .close =                snd_cs46xx_playback_close_iec958,
1697         .ioctl =                snd_pcm_lib_ioctl,
1698         .hw_params =            snd_cs46xx_playback_hw_params,
1699         .hw_free =              snd_cs46xx_playback_hw_free,
1700         .prepare =              snd_cs46xx_playback_prepare,
1701         .trigger =              snd_cs46xx_playback_trigger,
1702         .pointer =              snd_cs46xx_playback_direct_pointer,
1703 };
1704
1705 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1706         .open =                 snd_cs46xx_playback_open_iec958,
1707         .close =                snd_cs46xx_playback_close_iec958,
1708         .ioctl =                snd_pcm_lib_ioctl,
1709         .hw_params =            snd_cs46xx_playback_hw_params,
1710         .hw_free =              snd_cs46xx_playback_hw_free,
1711         .prepare =              snd_cs46xx_playback_prepare,
1712         .trigger =              snd_cs46xx_playback_trigger,
1713         .pointer =              snd_cs46xx_playback_indirect_pointer,
1714         .ack =                  snd_cs46xx_playback_transfer,
1715 };
1716
1717 #endif
1718
1719 static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1720         .open =                 snd_cs46xx_playback_open,
1721         .close =                snd_cs46xx_playback_close,
1722         .ioctl =                snd_pcm_lib_ioctl,
1723         .hw_params =            snd_cs46xx_playback_hw_params,
1724         .hw_free =              snd_cs46xx_playback_hw_free,
1725         .prepare =              snd_cs46xx_playback_prepare,
1726         .trigger =              snd_cs46xx_playback_trigger,
1727         .pointer =              snd_cs46xx_playback_direct_pointer,
1728 };
1729
1730 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1731         .open =                 snd_cs46xx_playback_open,
1732         .close =                snd_cs46xx_playback_close,
1733         .ioctl =                snd_pcm_lib_ioctl,
1734         .hw_params =            snd_cs46xx_playback_hw_params,
1735         .hw_free =              snd_cs46xx_playback_hw_free,
1736         .prepare =              snd_cs46xx_playback_prepare,
1737         .trigger =              snd_cs46xx_playback_trigger,
1738         .pointer =              snd_cs46xx_playback_indirect_pointer,
1739         .ack =                  snd_cs46xx_playback_transfer,
1740 };
1741
1742 static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1743         .open =                 snd_cs46xx_capture_open,
1744         .close =                snd_cs46xx_capture_close,
1745         .ioctl =                snd_pcm_lib_ioctl,
1746         .hw_params =            snd_cs46xx_capture_hw_params,
1747         .hw_free =              snd_cs46xx_capture_hw_free,
1748         .prepare =              snd_cs46xx_capture_prepare,
1749         .trigger =              snd_cs46xx_capture_trigger,
1750         .pointer =              snd_cs46xx_capture_direct_pointer,
1751 };
1752
1753 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1754         .open =                 snd_cs46xx_capture_open,
1755         .close =                snd_cs46xx_capture_close,
1756         .ioctl =                snd_pcm_lib_ioctl,
1757         .hw_params =            snd_cs46xx_capture_hw_params,
1758         .hw_free =              snd_cs46xx_capture_hw_free,
1759         .prepare =              snd_cs46xx_capture_prepare,
1760         .trigger =              snd_cs46xx_capture_trigger,
1761         .pointer =              snd_cs46xx_capture_indirect_pointer,
1762         .ack =                  snd_cs46xx_capture_transfer,
1763 };
1764
1765 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1766 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1767 #else
1768 #define MAX_PLAYBACK_CHANNELS   1
1769 #endif
1770
1771 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm)
1772 {
1773         struct snd_pcm *pcm;
1774         int err;
1775
1776         if (rpcm)
1777                 *rpcm = NULL;
1778         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1779                 return err;
1780
1781         pcm->private_data = chip;
1782
1783         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1784         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1785
1786         /* global setup */
1787         pcm->info_flags = 0;
1788         strcpy(pcm->name, "CS46xx");
1789         chip->pcm = pcm;
1790
1791         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1792                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1793
1794         if (rpcm)
1795                 *rpcm = pcm;
1796
1797         return 0;
1798 }
1799
1800
1801 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1802 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device,
1803                         struct snd_pcm **rpcm)
1804 {
1805         struct snd_pcm *pcm;
1806         int err;
1807
1808         if (rpcm)
1809                 *rpcm = NULL;
1810
1811         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1812                 return err;
1813
1814         pcm->private_data = chip;
1815
1816         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1817
1818         /* global setup */
1819         pcm->info_flags = 0;
1820         strcpy(pcm->name, "CS46xx - Rear");
1821         chip->pcm_rear = pcm;
1822
1823         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1824                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1825
1826         if (rpcm)
1827                 *rpcm = pcm;
1828
1829         return 0;
1830 }
1831
1832 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device,
1833                               struct snd_pcm **rpcm)
1834 {
1835         struct snd_pcm *pcm;
1836         int err;
1837
1838         if (rpcm)
1839                 *rpcm = NULL;
1840
1841         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1842                 return err;
1843
1844         pcm->private_data = chip;
1845
1846         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1847
1848         /* global setup */
1849         pcm->info_flags = 0;
1850         strcpy(pcm->name, "CS46xx - Center LFE");
1851         chip->pcm_center_lfe = pcm;
1852
1853         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1854                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1855
1856         if (rpcm)
1857                 *rpcm = pcm;
1858
1859         return 0;
1860 }
1861
1862 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device,
1863                           struct snd_pcm **rpcm)
1864 {
1865         struct snd_pcm *pcm;
1866         int err;
1867
1868         if (rpcm)
1869                 *rpcm = NULL;
1870
1871         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1872                 return err;
1873
1874         pcm->private_data = chip;
1875
1876         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1877
1878         /* global setup */
1879         pcm->info_flags = 0;
1880         strcpy(pcm->name, "CS46xx - IEC958");
1881         chip->pcm_rear = pcm;
1882
1883         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1884                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1885
1886         if (rpcm)
1887                 *rpcm = pcm;
1888
1889         return 0;
1890 }
1891 #endif
1892
1893 /*
1894  *  Mixer routines
1895  */
1896 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1897 {
1898         struct snd_cs46xx *chip = bus->private_data;
1899
1900         chip->ac97_bus = NULL;
1901 }
1902
1903 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1904 {
1905         struct snd_cs46xx *chip = ac97->private_data;
1906
1907         if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1908                        ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1909                 return;
1910
1911         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1912                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1913                 chip->eapd_switch = NULL;
1914         }
1915         else
1916                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1917 }
1918
1919 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1920                                struct snd_ctl_elem_info *uinfo)
1921 {
1922         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1923         uinfo->count = 2;
1924         uinfo->value.integer.min = 0;
1925         uinfo->value.integer.max = 0x7fff;
1926         return 0;
1927 }
1928
1929 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1930 {
1931         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1932         int reg = kcontrol->private_value;
1933         unsigned int val = snd_cs46xx_peek(chip, reg);
1934         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1935         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1936         return 0;
1937 }
1938
1939 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1940 {
1941         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1942         int reg = kcontrol->private_value;
1943         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1944                             (0xffff - ucontrol->value.integer.value[1]));
1945         unsigned int old = snd_cs46xx_peek(chip, reg);
1946         int change = (old != val);
1947
1948         if (change) {
1949                 snd_cs46xx_poke(chip, reg, val);
1950         }
1951
1952         return change;
1953 }
1954
1955 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1956
1957 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1958 {
1959         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1960
1961         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1962         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1963
1964         return 0;
1965 }
1966
1967 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1968 {
1969         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1970         int change = 0;
1971
1972         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1973             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1974                 cs46xx_dsp_set_dac_volume(chip,
1975                                           ucontrol->value.integer.value[0],
1976                                           ucontrol->value.integer.value[1]);
1977                 change = 1;
1978         }
1979
1980         return change;
1981 }
1982
1983 #if 0
1984 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1985 {
1986         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1987
1988         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1989         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1990         return 0;
1991 }
1992
1993 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1994 {
1995         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1996         int change = 0;
1997
1998         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1999             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
2000                 cs46xx_dsp_set_iec958_volume (chip,
2001                                               ucontrol->value.integer.value[0],
2002                                               ucontrol->value.integer.value[1]);
2003                 change = 1;
2004         }
2005
2006         return change;
2007 }
2008 #endif
2009
2010 #define snd_mixer_boolean_info          snd_ctl_boolean_mono_info
2011
2012 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
2013                                  struct snd_ctl_elem_value *ucontrol)
2014 {
2015         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2016         int reg = kcontrol->private_value;
2017
2018         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
2019                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2020         else
2021                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
2022
2023         return 0;
2024 }
2025
2026 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
2027                                   struct snd_ctl_elem_value *ucontrol)
2028 {
2029         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2030         int change, res;
2031
2032         switch (kcontrol->private_value) {
2033         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2034                 mutex_lock(&chip->spos_mutex);
2035                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2036                 if (ucontrol->value.integer.value[0] && !change)
2037                         cs46xx_dsp_enable_spdif_out(chip);
2038                 else if (change && !ucontrol->value.integer.value[0])
2039                         cs46xx_dsp_disable_spdif_out(chip);
2040
2041                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2042                 mutex_unlock(&chip->spos_mutex);
2043                 break;
2044         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2045                 change = chip->dsp_spos_instance->spdif_status_in;
2046                 if (ucontrol->value.integer.value[0] && !change) {
2047                         cs46xx_dsp_enable_spdif_in(chip);
2048                         /* restore volume */
2049                 }
2050                 else if (change && !ucontrol->value.integer.value[0])
2051                         cs46xx_dsp_disable_spdif_in(chip);
2052
2053                 res = (change != chip->dsp_spos_instance->spdif_status_in);
2054                 break;
2055         default:
2056                 res = -EINVAL;
2057                 snd_BUG(); /* should never happen ... */
2058         }
2059
2060         return res;
2061 }
2062
2063 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2064                                       struct snd_ctl_elem_value *ucontrol)
2065 {
2066         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2067         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2068
2069         if (ins->adc_input != NULL)
2070                 ucontrol->value.integer.value[0] = 1;
2071         else
2072                 ucontrol->value.integer.value[0] = 0;
2073
2074         return 0;
2075 }
2076
2077 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2078                                       struct snd_ctl_elem_value *ucontrol)
2079 {
2080         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2081         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2082         int change = 0;
2083
2084         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2085                 cs46xx_dsp_enable_adc_capture(chip);
2086                 change = 1;
2087         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2088                 cs46xx_dsp_disable_adc_capture(chip);
2089                 change = 1;
2090         }
2091         return change;
2092 }
2093
2094 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2095                                       struct snd_ctl_elem_value *ucontrol)
2096 {
2097         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2098         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2099
2100         if (ins->pcm_input != NULL)
2101                 ucontrol->value.integer.value[0] = 1;
2102         else
2103                 ucontrol->value.integer.value[0] = 0;
2104
2105         return 0;
2106 }
2107
2108
2109 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2110                                       struct snd_ctl_elem_value *ucontrol)
2111 {
2112         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2113         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2114         int change = 0;
2115
2116         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2117                 cs46xx_dsp_enable_pcm_capture(chip);
2118                 change = 1;
2119         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2120                 cs46xx_dsp_disable_pcm_capture(chip);
2121                 change = 1;
2122         }
2123
2124         return change;
2125 }
2126
2127 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2128                                      struct snd_ctl_elem_value *ucontrol)
2129 {
2130         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2131
2132         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2133
2134         if (val1 & EGPIODR_GPOE0)
2135                 ucontrol->value.integer.value[0] = 1;
2136         else
2137                 ucontrol->value.integer.value[0] = 0;
2138
2139         return 0;
2140 }
2141
2142 /*
2143  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2144  */
2145 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2146                                        struct snd_ctl_elem_value *ucontrol)
2147 {
2148         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2149         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2150         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2151
2152         if (ucontrol->value.integer.value[0]) {
2153                 /* optical is default */
2154                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2155                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2156                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2157                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2158         } else {
2159                 /* coaxial */
2160                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2161                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2162         }
2163
2164         /* checking diff from the EGPIO direction register
2165            should be enough */
2166         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2167 }
2168
2169
2170 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2171 {
2172         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2173         uinfo->count = 1;
2174         return 0;
2175 }
2176
2177 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2178                                         struct snd_ctl_elem_value *ucontrol)
2179 {
2180         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2181         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2182
2183         mutex_lock(&chip->spos_mutex);
2184         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2185         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2186         ucontrol->value.iec958.status[2] = 0;
2187         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2188         mutex_unlock(&chip->spos_mutex);
2189
2190         return 0;
2191 }
2192
2193 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2194                                         struct snd_ctl_elem_value *ucontrol)
2195 {
2196         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2197         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2198         unsigned int val;
2199         int change;
2200
2201         mutex_lock(&chip->spos_mutex);
2202         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2203                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2204                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2205                 /* left and right validity bit */
2206                 (1 << 13) | (1 << 12);
2207
2208
2209         change = (unsigned int)ins->spdif_csuv_default != val;
2210         ins->spdif_csuv_default = val;
2211
2212         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2213                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2214
2215         mutex_unlock(&chip->spos_mutex);
2216
2217         return change;
2218 }
2219
2220 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2221                                      struct snd_ctl_elem_value *ucontrol)
2222 {
2223         ucontrol->value.iec958.status[0] = 0xff;
2224         ucontrol->value.iec958.status[1] = 0xff;
2225         ucontrol->value.iec958.status[2] = 0x00;
2226         ucontrol->value.iec958.status[3] = 0xff;
2227         return 0;
2228 }
2229
2230 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2231                                          struct snd_ctl_elem_value *ucontrol)
2232 {
2233         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2234         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2235
2236         mutex_lock(&chip->spos_mutex);
2237         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2238         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2239         ucontrol->value.iec958.status[2] = 0;
2240         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2241         mutex_unlock(&chip->spos_mutex);
2242
2243         return 0;
2244 }
2245
2246 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2247                                         struct snd_ctl_elem_value *ucontrol)
2248 {
2249         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2250         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2251         unsigned int val;
2252         int change;
2253
2254         mutex_lock(&chip->spos_mutex);
2255         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2256                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2257                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2258                 /* left and right validity bit */
2259                 (1 << 13) | (1 << 12);
2260
2261
2262         change = ins->spdif_csuv_stream != val;
2263         ins->spdif_csuv_stream = val;
2264
2265         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2266                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2267
2268         mutex_unlock(&chip->spos_mutex);
2269
2270         return change;
2271 }
2272
2273 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2274
2275
2276 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2277 {
2278         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2279         .name = "DAC Volume",
2280         .info = snd_cs46xx_vol_info,
2281 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2282         .get = snd_cs46xx_vol_get,
2283         .put = snd_cs46xx_vol_put,
2284         .private_value = BA1_PVOL,
2285 #else
2286         .get = snd_cs46xx_vol_dac_get,
2287         .put = snd_cs46xx_vol_dac_put,
2288 #endif
2289 },
2290
2291 {
2292         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293         .name = "ADC Volume",
2294         .info = snd_cs46xx_vol_info,
2295         .get = snd_cs46xx_vol_get,
2296         .put = snd_cs46xx_vol_put,
2297 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2298         .private_value = BA1_CVOL,
2299 #else
2300         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2301 #endif
2302 },
2303 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2304 {
2305         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2306         .name = "ADC Capture Switch",
2307         .info = snd_mixer_boolean_info,
2308         .get = snd_cs46xx_adc_capture_get,
2309         .put = snd_cs46xx_adc_capture_put
2310 },
2311 {
2312         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2313         .name = "DAC Capture Switch",
2314         .info = snd_mixer_boolean_info,
2315         .get = snd_cs46xx_pcm_capture_get,
2316         .put = snd_cs46xx_pcm_capture_put
2317 },
2318 {
2319         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2320         .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2321         .info = snd_mixer_boolean_info,
2322         .get = snd_cs46xx_iec958_get,
2323         .put = snd_cs46xx_iec958_put,
2324         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2325 },
2326 {
2327         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2328         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2329         .info = snd_mixer_boolean_info,
2330         .get = snd_cs46xx_iec958_get,
2331         .put = snd_cs46xx_iec958_put,
2332         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2333 },
2334 #if 0
2335 /* Input IEC958 volume does not work for the moment. (Benny) */
2336 {
2337         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2338         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2339         .info = snd_cs46xx_vol_info,
2340         .get = snd_cs46xx_vol_iec958_get,
2341         .put = snd_cs46xx_vol_iec958_put,
2342         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2343 },
2344 #endif
2345 {
2346         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2347         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2348         .info =  snd_cs46xx_spdif_info,
2349         .get =   snd_cs46xx_spdif_default_get,
2350         .put =   snd_cs46xx_spdif_default_put,
2351 },
2352 {
2353         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2354         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2355         .info =  snd_cs46xx_spdif_info,
2356         .get =   snd_cs46xx_spdif_mask_get,
2357         .access = SNDRV_CTL_ELEM_ACCESS_READ
2358 },
2359 {
2360         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2361         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2362         .info =  snd_cs46xx_spdif_info,
2363         .get =   snd_cs46xx_spdif_stream_get,
2364         .put =   snd_cs46xx_spdif_stream_put
2365 },
2366
2367 #endif
2368 };
2369
2370 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2371 /* set primary cs4294 codec into Extended Audio Mode */
2372 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2373                                     struct snd_ctl_elem_value *ucontrol)
2374 {
2375         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2376         unsigned short val;
2377         val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2378         ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2379         return 0;
2380 }
2381
2382 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2383                                     struct snd_ctl_elem_value *ucontrol)
2384 {
2385         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2386         return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2387                                     AC97_CSR_ACMODE, 0x200,
2388                                     ucontrol->value.integer.value[0] ? 0 : 0x200);
2389 }
2390
2391 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2392         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2393         .name = "Duplicate Front",
2394         .info = snd_mixer_boolean_info,
2395         .get = snd_cs46xx_front_dup_get,
2396         .put = snd_cs46xx_front_dup_put,
2397 };
2398 #endif
2399
2400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2401 /* Only available on the Hercules Game Theater XP soundcard */
2402 static struct snd_kcontrol_new snd_hercules_controls[] = {
2403 {
2404         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2405         .name = "Optical/Coaxial SPDIF Input Switch",
2406         .info = snd_mixer_boolean_info,
2407         .get = snd_herc_spdif_select_get,
2408         .put = snd_herc_spdif_select_put,
2409 },
2410 };
2411
2412
2413 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2414 {
2415         unsigned long end_time;
2416         int err;
2417
2418         /* reset to defaults */
2419         snd_ac97_write(ac97, AC97_RESET, 0);
2420
2421         /* set the desired CODEC mode */
2422         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2423                 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0);
2424                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2425         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2426                 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3);
2427                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2428         } else {
2429                 snd_BUG(); /* should never happen ... */
2430         }
2431
2432         udelay(50);
2433
2434         /* it's necessary to wait awhile until registers are accessible after RESET */
2435         /* because the PCM or MASTER volume registers can be modified, */
2436         /* the REC_GAIN register is used for tests */
2437         end_time = jiffies + HZ;
2438         do {
2439                 unsigned short ext_mid;
2440
2441                 /* use preliminary reads to settle the communication */
2442                 snd_ac97_read(ac97, AC97_RESET);
2443                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2444                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2445                 /* modem? */
2446                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2447                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2448                         return;
2449
2450                 /* test if we can write to the record gain volume register */
2451                 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2452                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2453                         return;
2454
2455                 msleep(10);
2456         } while (time_after_eq(end_time, jiffies));
2457
2458         snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
2459 }
2460 #endif
2461
2462 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2463 {
2464         int idx, err;
2465         struct snd_ac97_template ac97;
2466
2467         memset(&ac97, 0, sizeof(ac97));
2468         ac97.private_data = chip;
2469         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2470         ac97.num = codec;
2471         if (chip->amplifier_ctrl == amp_voyetra)
2472                 ac97.scaps = AC97_SCAP_INV_EAPD;
2473
2474         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2475                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2476                 udelay(10);
2477                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2478                         snd_printdd("snd_cs46xx: seconadry codec not present\n");
2479                         return -ENXIO;
2480                 }
2481         }
2482
2483         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2484         for (idx = 0; idx < 100; ++idx) {
2485                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2486                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2487                         return err;
2488                 }
2489                 msleep(10);
2490         }
2491         snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2492         return -ENXIO;
2493 }
2494
2495 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2496 {
2497         struct snd_card *card = chip->card;
2498         struct snd_ctl_elem_id id;
2499         int err;
2500         unsigned int idx;
2501         static struct snd_ac97_bus_ops ops = {
2502 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2503                 .reset = snd_cs46xx_codec_reset,
2504 #endif
2505                 .write = snd_cs46xx_ac97_write,
2506                 .read = snd_cs46xx_ac97_read,
2507         };
2508
2509         /* detect primary codec */
2510         chip->nr_ac97_codecs = 0;
2511         snd_printdd("snd_cs46xx: detecting primary codec\n");
2512         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2513                 return err;
2514         chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2515
2516         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2517                 return -ENXIO;
2518         chip->nr_ac97_codecs = 1;
2519
2520 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2521         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2522         /* try detect a secondary codec */
2523         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2524                 chip->nr_ac97_codecs = 2;
2525 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2526
2527         /* add cs4630 mixer controls */
2528         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2529                 struct snd_kcontrol *kctl;
2530                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2531                 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2532                         kctl->id.device = spdif_device;
2533                 if ((err = snd_ctl_add(card, kctl)) < 0)
2534                         return err;
2535         }
2536
2537         /* get EAPD mixer switch (for voyetra hack) */
2538         memset(&id, 0, sizeof(id));
2539         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2540         strcpy(id.name, "External Amplifier");
2541         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2542
2543 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2544         if (chip->nr_ac97_codecs == 1) {
2545                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2546                 if (id2 == 0x592b || id2 == 0x592d) {
2547                         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2548                         if (err < 0)
2549                                 return err;
2550                         snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2551                                              AC97_CSR_ACMODE, 0x200);
2552                 }
2553         }
2554         /* do soundcard specific mixer setup */
2555         if (chip->mixer_init) {
2556                 snd_printdd ("calling chip->mixer_init(chip);\n");
2557                 chip->mixer_init(chip);
2558         }
2559 #endif
2560
2561         /* turn on amplifier */
2562         chip->amplifier_ctrl(chip, 1);
2563
2564         return 0;
2565 }
2566
2567 /*
2568  *  RawMIDI interface
2569  */
2570
2571 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2572 {
2573         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2574         udelay(100);
2575         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2576 }
2577
2578 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2579 {
2580         struct snd_cs46xx *chip = substream->rmidi->private_data;
2581
2582         chip->active_ctrl(chip, 1);
2583         spin_lock_irq(&chip->reg_lock);
2584         chip->uartm |= CS46XX_MODE_INPUT;
2585         chip->midcr |= MIDCR_RXE;
2586         chip->midi_input = substream;
2587         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2588                 snd_cs46xx_midi_reset(chip);
2589         } else {
2590                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2591         }
2592         spin_unlock_irq(&chip->reg_lock);
2593         return 0;
2594 }
2595
2596 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2597 {
2598         struct snd_cs46xx *chip = substream->rmidi->private_data;
2599
2600         spin_lock_irq(&chip->reg_lock);
2601         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2602         chip->midi_input = NULL;
2603         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2604                 snd_cs46xx_midi_reset(chip);
2605         } else {
2606                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2607         }
2608         chip->uartm &= ~CS46XX_MODE_INPUT;
2609         spin_unlock_irq(&chip->reg_lock);
2610         chip->active_ctrl(chip, -1);
2611         return 0;
2612 }
2613
2614 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2615 {
2616         struct snd_cs46xx *chip = substream->rmidi->private_data;
2617
2618         chip->active_ctrl(chip, 1);
2619
2620         spin_lock_irq(&chip->reg_lock);
2621         chip->uartm |= CS46XX_MODE_OUTPUT;
2622         chip->midcr |= MIDCR_TXE;
2623         chip->midi_output = substream;
2624         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2625                 snd_cs46xx_midi_reset(chip);
2626         } else {
2627                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2628         }
2629         spin_unlock_irq(&chip->reg_lock);
2630         return 0;
2631 }
2632
2633 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2634 {
2635         struct snd_cs46xx *chip = substream->rmidi->private_data;
2636
2637         spin_lock_irq(&chip->reg_lock);
2638         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2639         chip->midi_output = NULL;
2640         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2641                 snd_cs46xx_midi_reset(chip);
2642         } else {
2643                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2644         }
2645         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2646         spin_unlock_irq(&chip->reg_lock);
2647         chip->active_ctrl(chip, -1);
2648         return 0;
2649 }
2650
2651 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2652 {
2653         unsigned long flags;
2654         struct snd_cs46xx *chip = substream->rmidi->private_data;
2655
2656         spin_lock_irqsave(&chip->reg_lock, flags);
2657         if (up) {
2658                 if ((chip->midcr & MIDCR_RIE) == 0) {
2659                         chip->midcr |= MIDCR_RIE;
2660                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2661                 }
2662         } else {
2663                 if (chip->midcr & MIDCR_RIE) {
2664                         chip->midcr &= ~MIDCR_RIE;
2665                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2666                 }
2667         }
2668         spin_unlock_irqrestore(&chip->reg_lock, flags);
2669 }
2670
2671 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2672 {
2673         unsigned long flags;
2674         struct snd_cs46xx *chip = substream->rmidi->private_data;
2675         unsigned char byte;
2676
2677         spin_lock_irqsave(&chip->reg_lock, flags);
2678         if (up) {
2679                 if ((chip->midcr & MIDCR_TIE) == 0) {
2680                         chip->midcr |= MIDCR_TIE;
2681                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2682                         while ((chip->midcr & MIDCR_TIE) &&
2683                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2684                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2685                                         chip->midcr &= ~MIDCR_TIE;
2686                                 } else {
2687                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2688                                 }
2689                         }
2690                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2691                 }
2692         } else {
2693                 if (chip->midcr & MIDCR_TIE) {
2694                         chip->midcr &= ~MIDCR_TIE;
2695                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2696                 }
2697         }
2698         spin_unlock_irqrestore(&chip->reg_lock, flags);
2699 }
2700
2701 static struct snd_rawmidi_ops snd_cs46xx_midi_output =
2702 {
2703         .open =         snd_cs46xx_midi_output_open,
2704         .close =        snd_cs46xx_midi_output_close,
2705         .trigger =      snd_cs46xx_midi_output_trigger,
2706 };
2707
2708 static struct snd_rawmidi_ops snd_cs46xx_midi_input =
2709 {
2710         .open =         snd_cs46xx_midi_input_open,
2711         .close =        snd_cs46xx_midi_input_close,
2712         .trigger =      snd_cs46xx_midi_input_trigger,
2713 };
2714
2715 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
2716 {
2717         struct snd_rawmidi *rmidi;
2718         int err;
2719
2720         if (rrawmidi)
2721                 *rrawmidi = NULL;
2722         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2723                 return err;
2724         strcpy(rmidi->name, "CS46XX");
2725         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2726         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2727         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2728         rmidi->private_data = chip;
2729         chip->rmidi = rmidi;
2730         if (rrawmidi)
2731                 *rrawmidi = NULL;
2732         return 0;
2733 }
2734
2735
2736 /*
2737  * gameport interface
2738  */
2739
2740 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2741
2742 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2743 {
2744         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2745
2746         if (snd_BUG_ON(!chip))
2747                 return;
2748         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2749 }
2750
2751 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2752 {
2753         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2754
2755         if (snd_BUG_ON(!chip))
2756                 return 0;
2757         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2758 }
2759
2760 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2761 {
2762         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2763         unsigned js1, js2, jst;
2764
2765         if (snd_BUG_ON(!chip))
2766                 return 0;
2767
2768         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2769         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2770         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2771
2772         *buttons = (~jst >> 4) & 0x0F;
2773
2774         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2775         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2776         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2777         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2778
2779         for(jst=0;jst<4;++jst)
2780                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2781         return 0;
2782 }
2783
2784 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2785 {
2786         switch (mode) {
2787         case GAMEPORT_MODE_COOKED:
2788                 return 0;
2789         case GAMEPORT_MODE_RAW:
2790                 return 0;
2791         default:
2792                 return -1;
2793         }
2794         return 0;
2795 }
2796
2797 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2798 {
2799         struct gameport *gp;
2800
2801         chip->gameport = gp = gameport_allocate_port();
2802         if (!gp) {
2803                 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2804                 return -ENOMEM;
2805         }
2806
2807         gameport_set_name(gp, "CS46xx Gameport");
2808         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2809         gameport_set_dev_parent(gp, &chip->pci->dev);
2810         gameport_set_port_data(gp, chip);
2811
2812         gp->open = snd_cs46xx_gameport_open;
2813         gp->read = snd_cs46xx_gameport_read;
2814         gp->trigger = snd_cs46xx_gameport_trigger;
2815         gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2816
2817         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2818         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2819
2820         gameport_register_port(gp);
2821
2822         return 0;
2823 }
2824
2825 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2826 {
2827         if (chip->gameport) {
2828                 gameport_unregister_port(chip->gameport);
2829                 chip->gameport = NULL;
2830         }
2831 }
2832 #else
2833 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2834 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2835 #endif /* CONFIG_GAMEPORT */
2836
2837 #ifdef CONFIG_PROC_FS
2838 /*
2839  *  proc interface
2840  */
2841
2842 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2843                                   void *file_private_data,
2844                                   struct file *file, char __user *buf,
2845                                   size_t count, loff_t pos)
2846 {
2847         struct snd_cs46xx_region *region = entry->private_data;
2848
2849         if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2850                 return -EFAULT;
2851         return count;
2852 }
2853
2854 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2855         .read = snd_cs46xx_io_read,
2856 };
2857
2858 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2859 {
2860         struct snd_info_entry *entry;
2861         int idx;
2862
2863         for (idx = 0; idx < 5; idx++) {
2864                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2865                 if (! snd_card_proc_new(card, region->name, &entry)) {
2866                         entry->content = SNDRV_INFO_CONTENT_DATA;
2867                         entry->private_data = chip;
2868                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2869                         entry->size = region->size;
2870                         entry->mode = S_IFREG | S_IRUSR;
2871                 }
2872         }
2873 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2874         cs46xx_dsp_proc_init(card, chip);
2875 #endif
2876         return 0;
2877 }
2878
2879 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2880 {
2881 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2882         cs46xx_dsp_proc_done(chip);
2883 #endif
2884         return 0;
2885 }
2886 #else /* !CONFIG_PROC_FS */
2887 #define snd_cs46xx_proc_init(card, chip)
2888 #define snd_cs46xx_proc_done(chip)
2889 #endif
2890
2891 /*
2892  * stop the h/w
2893  */
2894 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2895 {
2896         unsigned int tmp;
2897
2898         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2899         tmp &= ~0x0000f03f;
2900         tmp |=  0x00000010;
2901         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2902
2903         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2904         tmp &= ~0x0000003f;
2905         tmp |=  0x00000011;
2906         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2907
2908         /*
2909          *  Stop playback DMA.
2910          */
2911         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2912         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2913
2914         /*
2915          *  Stop capture DMA.
2916          */
2917         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2918         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2919
2920         /*
2921          *  Reset the processor.
2922          */
2923         snd_cs46xx_reset(chip);
2924
2925         snd_cs46xx_proc_stop(chip);
2926
2927         /*
2928          *  Power down the PLL.
2929          */
2930         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2931
2932         /*
2933          *  Turn off the Processor by turning off the software clock enable flag in
2934          *  the clock control register.
2935          */
2936         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2937         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2938 }
2939
2940
2941 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2942 {
2943         int idx;
2944
2945         if (snd_BUG_ON(!chip))
2946                 return -EINVAL;
2947
2948         if (chip->active_ctrl)
2949                 chip->active_ctrl(chip, 1);
2950
2951         snd_cs46xx_remove_gameport(chip);
2952
2953         if (chip->amplifier_ctrl)
2954                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2955
2956         snd_cs46xx_proc_done(chip);
2957
2958         if (chip->region.idx[0].resource)
2959                 snd_cs46xx_hw_stop(chip);
2960
2961         if (chip->irq >= 0)
2962                 free_irq(chip->irq, chip);
2963
2964         if (chip->active_ctrl)
2965                 chip->active_ctrl(chip, -chip->amplifier);
2966
2967         for (idx = 0; idx < 5; idx++) {
2968                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2969                 if (region->remap_addr)
2970                         iounmap(region->remap_addr);
2971                 release_and_free_resource(region->resource);
2972         }
2973
2974 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2975         if (chip->dsp_spos_instance) {
2976                 cs46xx_dsp_spos_destroy(chip);
2977                 chip->dsp_spos_instance = NULL;
2978         }
2979         for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2980                 free_module_desc(chip->modules[idx]);
2981 #else
2982         vfree(chip->ba1);
2983 #endif
2984
2985 #ifdef CONFIG_PM_SLEEP
2986         kfree(chip->saved_regs);
2987 #endif
2988
2989         pci_disable_device(chip->pci);
2990         kfree(chip);
2991         return 0;
2992 }
2993
2994 static int snd_cs46xx_dev_free(struct snd_device *device)
2995 {
2996         struct snd_cs46xx *chip = device->device_data;
2997         return snd_cs46xx_free(chip);
2998 }
2999
3000 /*
3001  *  initialize chip
3002  */
3003 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
3004 {
3005         int timeout;
3006
3007         /*
3008          *  First, blast the clock control register to zero so that the PLL starts
3009          *  out in a known state, and blast the master serial port control register
3010          *  to zero so that the serial ports also start out in a known state.
3011          */
3012         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
3013         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
3014
3015         /*
3016          *  If we are in AC97 mode, then we must set the part to a host controlled
3017          *  AC-link.  Otherwise, we won't be able to bring up the link.
3018          */
3019 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3020         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
3021                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
3022         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3023 #else
3024         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3025 #endif
3026
3027         /*
3028          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3029          *  spec) and then drive it high.  This is done for non AC97 modes since
3030          *  there might be logic external to the CS461x that uses the ARST# line
3031          *  for a reset.
3032          */
3033         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3034 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3035         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3036 #endif
3037         udelay(50);
3038         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3039 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3040         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3041 #endif
3042
3043         /*
3044          *  The first thing we do here is to enable sync generation.  As soon
3045          *  as we start receiving bit clock, we'll start producing the SYNC
3046          *  signal.
3047          */
3048         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3049 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3050         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3051 #endif
3052
3053         /*
3054          *  Now wait for a short while to allow the AC97 part to start
3055          *  generating bit clock (so we don't try to start the PLL without an
3056          *  input clock).
3057          */
3058         mdelay(10);
3059
3060         /*
3061          *  Set the serial port timing configuration, so that
3062          *  the clock control circuit gets its clock from the correct place.
3063          */
3064         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3065
3066         /*
3067          *  Write the selected clock control setup to the hardware.  Do not turn on
3068          *  SWCE yet (if requested), so that the devices clocked by the output of
3069          *  PLL are not clocked until the PLL is stable.
3070          */
3071         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3072         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3073         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3074
3075         /*
3076          *  Power up the PLL.
3077          */
3078         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3079
3080         /*
3081          *  Wait until the PLL has stabilized.
3082          */
3083         msleep(100);
3084
3085         /*
3086          *  Turn on clocking of the core so that we can setup the serial ports.
3087          */
3088         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3089
3090         /*
3091          * Enable FIFO  Host Bypass
3092          */
3093         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3094
3095         /*
3096          *  Fill the serial port FIFOs with silence.
3097          */
3098         snd_cs46xx_clear_serial_FIFOs(chip);
3099
3100         /*
3101          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3102          */
3103         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3104
3105         /*
3106          *  Write the serial port configuration to the part.  The master
3107          *  enable bit is not set until all other values have been written.
3108          */
3109         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3110         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3111         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3112
3113
3114 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3115         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3116         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3117         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3118         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3119         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3120 #endif
3121
3122         mdelay(5);
3123
3124
3125         /*
3126          * Wait for the codec ready signal from the AC97 codec.
3127          */
3128         timeout = 150;
3129         while (timeout-- > 0) {
3130                 /*
3131                  *  Read the AC97 status register to see if we've seen a CODEC READY
3132                  *  signal from the AC97 codec.
3133                  */
3134                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3135                         goto ok1;
3136                 msleep(10);
3137         }
3138
3139
3140         snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
3141         snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
3142         return -EIO;
3143  ok1:
3144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3145         {
3146                 int count;
3147                 for (count = 0; count < 150; count++) {
3148                         /* First, we want to wait for a short time. */
3149                         udelay(25);
3150
3151                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3152                                 break;
3153                 }
3154
3155                 /*
3156                  *  Make sure CODEC is READY.
3157                  */
3158                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3159                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3160         }
3161 #endif
3162
3163         /*
3164          *  Assert the vaid frame signal so that we can start sending commands
3165          *  to the AC97 codec.
3166          */
3167         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3168 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3169         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3170 #endif
3171
3172
3173         /*
3174          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3175          *  the codec is pumping ADC data across the AC-link.
3176          */
3177         timeout = 150;
3178         while (timeout-- > 0) {
3179                 /*
3180                  *  Read the input slot valid register and see if input slots 3 and
3181                  *  4 are valid yet.
3182                  */
3183                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3184                         goto ok2;
3185                 msleep(10);
3186         }
3187
3188 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3189         snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
3190         return -EIO;
3191 #else
3192         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3193            Reloading the driver may help, if there's other soundcards
3194            with the same problem I would like to know. (Benny) */
3195
3196         snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3197         snd_printk(KERN_ERR "       Try reloading the ALSA driver, if you find something\n");
3198         snd_printk(KERN_ERR "       broken or not working on your soundcard upon\n");
3199         snd_printk(KERN_ERR "       this message please report to alsa-devel@alsa-project.org\n");
3200
3201         return -EIO;
3202 #endif
3203  ok2:
3204
3205         /*
3206          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3207          *  commense the transfer of digital audio data to the AC97 codec.
3208          */
3209
3210         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3211
3212
3213         /*
3214          *  Power down the DAC and ADC.  We will power them up (if) when we need
3215          *  them.
3216          */
3217         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3218
3219         /*
3220          *  Turn off the Processor by turning off the software clock enable flag in
3221          *  the clock control register.
3222          */
3223         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3224         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3225
3226         return 0;
3227 }
3228
3229 /*
3230  *  start and load DSP
3231  */
3232
3233 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3234 {
3235         unsigned int tmp;
3236
3237         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3238
3239         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3240         tmp &= ~0x0000f03f;
3241         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3242
3243         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3244         tmp &= ~0x0000003f;
3245         tmp |=  0x00000001;
3246         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3247 }
3248
3249 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3250 {
3251         unsigned int tmp;
3252 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3253         int i;
3254 #endif
3255         int err;
3256
3257         /*
3258          *  Reset the processor.
3259          */
3260         snd_cs46xx_reset(chip);
3261         /*
3262          *  Download the image to the processor.
3263          */
3264 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3265         for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3266                 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3267                 if (err < 0) {
3268                         snd_printk(KERN_ERR "firmware load error [%s]\n",
3269                                    module_names[i]);
3270                         return err;
3271                 }
3272                 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3273                 if (err < 0) {
3274                         snd_printk(KERN_ERR "image download error [%s]\n",
3275                                    module_names[i]);
3276                         return err;
3277                 }
3278         }
3279
3280         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3281                 return -EIO;
3282 #else
3283         err = load_firmware(chip);
3284         if (err < 0)
3285                 return err;
3286
3287         /* old image */
3288         err = snd_cs46xx_download_image(chip);
3289         if (err < 0) {
3290                 snd_printk(KERN_ERR "image download error\n");
3291                 return err;
3292         }
3293
3294         /*
3295          *  Stop playback DMA.
3296          */
3297         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3298         chip->play_ctl = tmp & 0xffff0000;
3299         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3300 #endif
3301
3302         /*
3303          *  Stop capture DMA.
3304          */
3305         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3306         chip->capt.ctl = tmp & 0x0000ffff;
3307         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3308
3309         mdelay(5);
3310
3311         snd_cs46xx_set_play_sample_rate(chip, 8000);
3312         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3313
3314         snd_cs46xx_proc_start(chip);
3315
3316         cs46xx_enable_stream_irqs(chip);
3317
3318 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3319         /* set the attenuation to 0dB */
3320         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3321         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3322 #endif
3323
3324         return 0;
3325 }
3326
3327
3328 /*
3329  *      AMP control - null AMP
3330  */
3331
3332 static void amp_none(struct snd_cs46xx *chip, int change)
3333 {
3334 }
3335
3336 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3337 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3338 {
3339
3340         u32 idx, valid_slots,tmp,powerdown = 0;
3341         u16 modem_power,pin_config,logic_type;
3342
3343         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3344
3345         /*
3346          *  See if the devices are powered down.  If so, we must power them up first
3347          *  or they will not respond.
3348          */
3349         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3350
3351         if (!(tmp & CLKCR1_SWCE)) {
3352                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3353                 powerdown = 1;
3354         }
3355
3356         /*
3357          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3358          * stuff.
3359          */
3360         if(chip->nr_ac97_codecs != 2) {
3361                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3362                 return -EINVAL;
3363         }
3364
3365         modem_power = snd_cs46xx_codec_read (chip,
3366                                              AC97_EXTENDED_MSTATUS,
3367                                              CS46XX_SECONDARY_CODEC_INDEX);
3368         modem_power &=0xFEFF;
3369
3370         snd_cs46xx_codec_write(chip,
3371                                AC97_EXTENDED_MSTATUS, modem_power,
3372                                CS46XX_SECONDARY_CODEC_INDEX);
3373
3374         /*
3375          * Set GPIO pin's 7 and 8 so that they are configured for output.
3376          */
3377         pin_config = snd_cs46xx_codec_read (chip,
3378                                             AC97_GPIO_CFG,
3379                                             CS46XX_SECONDARY_CODEC_INDEX);
3380         pin_config &=0x27F;
3381
3382         snd_cs46xx_codec_write(chip,
3383                                AC97_GPIO_CFG, pin_config,
3384                                CS46XX_SECONDARY_CODEC_INDEX);
3385
3386         /*
3387          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3388          */
3389
3390         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3391                                            CS46XX_SECONDARY_CODEC_INDEX);
3392         logic_type &=0x27F;
3393
3394         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3395                                 CS46XX_SECONDARY_CODEC_INDEX);
3396
3397         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3398         valid_slots |= 0x200;
3399         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3400
3401         if ( cs46xx_wait_for_fifo(chip,1) ) {
3402           snd_printdd("FIFO is busy\n");
3403
3404           return -EINVAL;
3405         }
3406
3407         /*
3408          * Fill slots 12 with the correct value for the GPIO pins.
3409          */
3410         for(idx = 0x90; idx <= 0x9F; idx++) {
3411                 /*
3412                  * Initialize the fifo so that bits 7 and 8 are on.
3413                  *
3414                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3415                  * the left.  0x1800 corresponds to bits 7 and 8.
3416                  */
3417                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3418
3419                 /*
3420                  * Wait for command to complete
3421                  */
3422                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3423                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3424
3425                         return -EINVAL;
3426                 }
3427
3428                 /*
3429                  * Write the serial port FIFO index.
3430                  */
3431                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3432
3433                 /*
3434                  * Tell the serial port to load the new value into the FIFO location.
3435                  */
3436                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3437         }
3438
3439         /* wait for last command to complete */
3440         cs46xx_wait_for_fifo(chip,200);
3441
3442         /*
3443          *  Now, if we powered up the devices, then power them back down again.
3444          *  This is kinda ugly, but should never happen.
3445          */
3446         if (powerdown)
3447                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3448
3449         return 0;
3450 }
3451 #endif
3452
3453 /*
3454  *      Crystal EAPD mode
3455  */
3456
3457 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3458 {
3459         /* Manage the EAPD bit on the Crystal 4297
3460            and the Analog AD1885 */
3461
3462 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3463         int old = chip->amplifier;
3464 #endif
3465         int oval, val;
3466
3467         chip->amplifier += change;
3468         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3469                                      CS46XX_PRIMARY_CODEC_INDEX);
3470         val = oval;
3471         if (chip->amplifier) {
3472                 /* Turn the EAPD amp on */
3473                 val |= 0x8000;
3474         } else {
3475                 /* Turn the EAPD amp off */
3476                 val &= ~0x8000;
3477         }
3478         if (val != oval) {
3479                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3480                                        CS46XX_PRIMARY_CODEC_INDEX);
3481                 if (chip->eapd_switch)
3482                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3483                                        &chip->eapd_switch->id);
3484         }
3485
3486 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3487         if (chip->amplifier && !old) {
3488                 voyetra_setup_eapd_slot(chip);
3489         }
3490 #endif
3491 }
3492
3493 static void hercules_init(struct snd_cs46xx *chip)
3494 {
3495         /* default: AMP off, and SPDIF input optical */
3496         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3497         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3498 }
3499
3500
3501 /*
3502  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3503  */
3504 static void amp_hercules(struct snd_cs46xx *chip, int change)
3505 {
3506         int old = chip->amplifier;
3507         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3508         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3509
3510         chip->amplifier += change;
3511         if (chip->amplifier && !old) {
3512                 snd_printdd ("Hercules amplifier ON\n");
3513
3514                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3515                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3516                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3517                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3518         } else if (old && !chip->amplifier) {
3519                 snd_printdd ("Hercules amplifier OFF\n");
3520                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3521                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3522         }
3523 }
3524
3525 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3526 {
3527         snd_printdd ("initializing Voyetra mixer\n");
3528
3529         /* Enable SPDIF out */
3530         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3531         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3532 }
3533
3534 static void hercules_mixer_init (struct snd_cs46xx *chip)
3535 {
3536 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3537         unsigned int idx;
3538         int err;
3539         struct snd_card *card = chip->card;
3540 #endif
3541
3542         /* set EGPIO to default */
3543         hercules_init(chip);
3544
3545         snd_printdd ("initializing Hercules mixer\n");
3546
3547 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3548         if (chip->in_suspend)
3549                 return;
3550
3551         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3552                 struct snd_kcontrol *kctl;
3553
3554                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3555                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3556                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3557                         break;
3558                 }
3559         }
3560 #endif
3561 }
3562
3563
3564 #if 0
3565 /*
3566  *      Untested
3567  */
3568
3569 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3570 {
3571         chip->amplifier += change;
3572
3573         if (chip->amplifier) {
3574                 /* Switch the GPIO pins 7 and 8 to open drain */
3575                 snd_cs46xx_codec_write(chip, 0x4C,
3576                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3577                 snd_cs46xx_codec_write(chip, 0x4E,
3578                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3579                 /* Now wake the AMP (this might be backwards) */
3580                 snd_cs46xx_codec_write(chip, 0x54,
3581                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3582         } else {
3583                 snd_cs46xx_codec_write(chip, 0x54,
3584                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3585         }
3586 }
3587 #endif
3588
3589
3590 /*
3591  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3592  *      whenever we need to beat on the chip.
3593  *
3594  *      The original idea and code for this hack comes from David Kaiser at
3595  *      Linuxcare. Perhaps one day Crystal will document their chips well
3596  *      enough to make them useful.
3597  */
3598
3599 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3600 {
3601         u16 control, nval;
3602
3603         if (!chip->acpi_port)
3604                 return;
3605
3606         chip->amplifier += change;
3607
3608         /* Read ACPI port */
3609         nval = control = inw(chip->acpi_port + 0x10);
3610
3611         /* Flip CLKRUN off while running */
3612         if (! chip->amplifier)
3613                 nval |= 0x2000;
3614         else
3615                 nval &= ~0x2000;
3616         if (nval != control)
3617                 outw(nval, chip->acpi_port + 0x10);
3618 }
3619
3620
3621 /*
3622  * detect intel piix4
3623  */
3624 static void clkrun_init(struct snd_cs46xx *chip)
3625 {
3626         struct pci_dev *pdev;
3627         u8 pp;
3628
3629         chip->acpi_port = 0;
3630
3631         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3632                 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3633         if (pdev == NULL)
3634                 return;         /* Not a thinkpad thats for sure */
3635
3636         /* Find the control port */
3637         pci_read_config_byte(pdev, 0x41, &pp);
3638         chip->acpi_port = pp << 8;
3639         pci_dev_put(pdev);
3640 }
3641
3642
3643 /*
3644  * Card subid table
3645  */
3646
3647 struct cs_card_type
3648 {
3649         u16 vendor;
3650         u16 id;
3651         char *name;
3652         void (*init)(struct snd_cs46xx *);
3653         void (*amp)(struct snd_cs46xx *, int);
3654         void (*active)(struct snd_cs46xx *, int);
3655         void (*mixer_init)(struct snd_cs46xx *);
3656 };
3657
3658 static struct cs_card_type cards[] = {
3659         {
3660                 .vendor = 0x1489,
3661                 .id = 0x7001,
3662                 .name = "Genius Soundmaker 128 value",
3663                 /* nothing special */
3664         },
3665         {
3666                 .vendor = 0x5053,
3667                 .id = 0x3357,
3668                 .name = "Voyetra",
3669                 .amp = amp_voyetra,
3670                 .mixer_init = voyetra_mixer_init,
3671         },
3672         {
3673                 .vendor = 0x1071,
3674                 .id = 0x6003,
3675                 .name = "Mitac MI6020/21",
3676                 .amp = amp_voyetra,
3677         },
3678         /* Hercules Game Theatre XP */
3679         {
3680                 .vendor = 0x14af, /* Guillemot Corporation */
3681                 .id = 0x0050,
3682                 .name = "Hercules Game Theatre XP",
3683                 .amp = amp_hercules,
3684                 .mixer_init = hercules_mixer_init,
3685         },
3686         {
3687                 .vendor = 0x1681,
3688                 .id = 0x0050,
3689                 .name = "Hercules Game Theatre XP",
3690                 .amp = amp_hercules,
3691                 .mixer_init = hercules_mixer_init,
3692         },
3693         {
3694                 .vendor = 0x1681,
3695                 .id = 0x0051,
3696                 .name = "Hercules Game Theatre XP",
3697                 .amp = amp_hercules,
3698                 .mixer_init = hercules_mixer_init,
3699
3700         },
3701         {
3702                 .vendor = 0x1681,
3703                 .id = 0x0052,
3704                 .name = "Hercules Game Theatre XP",
3705                 .amp = amp_hercules,
3706                 .mixer_init = hercules_mixer_init,
3707         },
3708         {
3709                 .vendor = 0x1681,
3710                 .id = 0x0053,
3711                 .name = "Hercules Game Theatre XP",
3712                 .amp = amp_hercules,
3713                 .mixer_init = hercules_mixer_init,
3714         },
3715         {
3716                 .vendor = 0x1681,
3717                 .id = 0x0054,
3718                 .name = "Hercules Game Theatre XP",
3719                 .amp = amp_hercules,
3720                 .mixer_init = hercules_mixer_init,
3721         },
3722         /* Herculess Fortissimo */
3723         {
3724                 .vendor = 0x1681,
3725                 .id = 0xa010,
3726                 .name = "Hercules Gamesurround Fortissimo II",
3727         },
3728         {
3729                 .vendor = 0x1681,
3730                 .id = 0xa011,
3731                 .name = "Hercules Gamesurround Fortissimo III 7.1",
3732         },
3733         /* Teratec */
3734         {
3735                 .vendor = 0x153b,
3736                 .id = 0x112e,
3737                 .name = "Terratec DMX XFire 1024",
3738         },
3739         {
3740                 .vendor = 0x153b,
3741                 .id = 0x1136,
3742                 .name = "Terratec SiXPack 5.1",
3743         },
3744         /* Not sure if the 570 needs the clkrun hack */
3745         {
3746                 .vendor = PCI_VENDOR_ID_IBM,
3747                 .id = 0x0132,
3748                 .name = "Thinkpad 570",
3749                 .init = clkrun_init,
3750                 .active = clkrun_hack,
3751         },
3752         {
3753                 .vendor = PCI_VENDOR_ID_IBM,
3754                 .id = 0x0153,
3755                 .name = "Thinkpad 600X/A20/T20",
3756                 .init = clkrun_init,
3757                 .active = clkrun_hack,
3758         },
3759         {
3760                 .vendor = PCI_VENDOR_ID_IBM,
3761                 .id = 0x1010,
3762                 .name = "Thinkpad 600E (unsupported)",
3763         },
3764         {} /* terminator */
3765 };
3766
3767
3768 /*
3769  * APM support
3770  */
3771 #ifdef CONFIG_PM_SLEEP
3772 static unsigned int saved_regs[] = {
3773         BA0_ACOSV,
3774         /*BA0_ASER_FADDR,*/
3775         BA0_ASER_MASTER,
3776         BA1_PVOL,
3777         BA1_CVOL,
3778 };
3779
3780 static int snd_cs46xx_suspend(struct device *dev)
3781 {
3782         struct pci_dev *pci = to_pci_dev(dev);
3783         struct snd_card *card = dev_get_drvdata(dev);
3784         struct snd_cs46xx *chip = card->private_data;
3785         int i, amp_saved;
3786
3787         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3788         chip->in_suspend = 1;
3789         snd_pcm_suspend_all(chip->pcm);
3790         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3791         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3792
3793         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3794         snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3795
3796         /* save some registers */
3797         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3798                 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3799
3800         amp_saved = chip->amplifier;
3801         /* turn off amp */
3802         chip->amplifier_ctrl(chip, -chip->amplifier);
3803         snd_cs46xx_hw_stop(chip);
3804         /* disable CLKRUN */
3805         chip->active_ctrl(chip, -chip->amplifier);
3806         chip->amplifier = amp_saved; /* restore the status */
3807
3808         pci_disable_device(pci);
3809         pci_save_state(pci);
3810         pci_set_power_state(pci, PCI_D3hot);
3811         return 0;
3812 }
3813
3814 static int snd_cs46xx_resume(struct device *dev)
3815 {
3816         struct pci_dev *pci = to_pci_dev(dev);
3817         struct snd_card *card = dev_get_drvdata(dev);
3818         struct snd_cs46xx *chip = card->private_data;
3819         int amp_saved;
3820 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3821         int i;
3822 #endif
3823         unsigned int tmp;
3824
3825         pci_set_power_state(pci, PCI_D0);
3826         pci_restore_state(pci);
3827         if (pci_enable_device(pci) < 0) {
3828                 printk(KERN_ERR "cs46xx: pci_enable_device failed, "
3829                        "disabling device\n");
3830                 snd_card_disconnect(card);
3831                 return -EIO;
3832         }
3833         pci_set_master(pci);
3834
3835         amp_saved = chip->amplifier;
3836         chip->amplifier = 0;
3837         chip->active_ctrl(chip, 1); /* force to on */
3838
3839         snd_cs46xx_chip_init(chip);
3840
3841         snd_cs46xx_reset(chip);
3842 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3843         cs46xx_dsp_resume(chip);
3844         /* restore some registers */
3845         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3846                 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3847 #else
3848         snd_cs46xx_download_image(chip);
3849 #endif
3850
3851 #if 0
3852         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3853                                chip->ac97_general_purpose);
3854         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3855                                chip->ac97_powerdown);
3856         mdelay(10);
3857         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3858                                chip->ac97_powerdown);
3859         mdelay(5);
3860 #endif
3861
3862         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3863         snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3864
3865         /*
3866          *  Stop capture DMA.
3867          */
3868         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3869         chip->capt.ctl = tmp & 0x0000ffff;
3870         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3871
3872         mdelay(5);
3873
3874         /* reset playback/capture */
3875         snd_cs46xx_set_play_sample_rate(chip, 8000);
3876         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3877         snd_cs46xx_proc_start(chip);
3878
3879         cs46xx_enable_stream_irqs(chip);
3880
3881         if (amp_saved)
3882                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3883         else
3884                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3885         chip->amplifier = amp_saved;
3886         chip->in_suspend = 0;
3887         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3888         return 0;
3889 }
3890
3891 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3892 #endif /* CONFIG_PM_SLEEP */
3893
3894
3895 /*
3896  */
3897
3898 int snd_cs46xx_create(struct snd_card *card,
3899                       struct pci_dev *pci,
3900                       int external_amp, int thinkpad,
3901                       struct snd_cs46xx **rchip)
3902 {
3903         struct snd_cs46xx *chip;
3904         int err, idx;
3905         struct snd_cs46xx_region *region;
3906         struct cs_card_type *cp;
3907         u16 ss_card, ss_vendor;
3908         static struct snd_device_ops ops = {
3909                 .dev_free =     snd_cs46xx_dev_free,
3910         };
3911
3912         *rchip = NULL;
3913
3914         /* enable PCI device */
3915         if ((err = pci_enable_device(pci)) < 0)
3916                 return err;
3917
3918         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3919         if (chip == NULL) {
3920                 pci_disable_device(pci);
3921                 return -ENOMEM;
3922         }
3923         spin_lock_init(&chip->reg_lock);
3924 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3925         mutex_init(&chip->spos_mutex);
3926 #endif
3927         chip->card = card;
3928         chip->pci = pci;
3929         chip->irq = -1;
3930         chip->ba0_addr = pci_resource_start(pci, 0);
3931         chip->ba1_addr = pci_resource_start(pci, 1);
3932         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3933             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3934                 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3935                            chip->ba0_addr, chip->ba1_addr);
3936                 snd_cs46xx_free(chip);
3937                 return -ENOMEM;
3938         }
3939
3940         region = &chip->region.name.ba0;
3941         strcpy(region->name, "CS46xx_BA0");
3942         region->base = chip->ba0_addr;
3943         region->size = CS46XX_BA0_SIZE;
3944
3945         region = &chip->region.name.data0;
3946         strcpy(region->name, "CS46xx_BA1_data0");
3947         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3948         region->size = CS46XX_BA1_DATA0_SIZE;
3949
3950         region = &chip->region.name.data1;
3951         strcpy(region->name, "CS46xx_BA1_data1");
3952         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3953         region->size = CS46XX_BA1_DATA1_SIZE;
3954
3955         region = &chip->region.name.pmem;
3956         strcpy(region->name, "CS46xx_BA1_pmem");
3957         region->base = chip->ba1_addr + BA1_SP_PMEM;
3958         region->size = CS46XX_BA1_PRG_SIZE;
3959
3960         region = &chip->region.name.reg;
3961         strcpy(region->name, "CS46xx_BA1_reg");
3962         region->base = chip->ba1_addr + BA1_SP_REG;
3963         region->size = CS46XX_BA1_REG_SIZE;
3964
3965         /* set up amp and clkrun hack */
3966         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3967         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3968
3969         for (cp = &cards[0]; cp->name; cp++) {
3970                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3971                         snd_printdd ("hack for %s enabled\n", cp->name);
3972
3973                         chip->amplifier_ctrl = cp->amp;
3974                         chip->active_ctrl = cp->active;
3975                         chip->mixer_init = cp->mixer_init;
3976
3977                         if (cp->init)
3978                                 cp->init(chip);
3979                         break;
3980                 }
3981         }
3982
3983         if (external_amp) {
3984                 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
3985                 chip->amplifier_ctrl = amp_voyetra;
3986         }
3987
3988         if (thinkpad) {
3989                 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
3990                 chip->active_ctrl = clkrun_hack;
3991                 clkrun_init(chip);
3992         }
3993
3994         if (chip->amplifier_ctrl == NULL)
3995                 chip->amplifier_ctrl = amp_none;
3996         if (chip->active_ctrl == NULL)
3997                 chip->active_ctrl = amp_none;
3998
3999         chip->active_ctrl(chip, 1); /* enable CLKRUN */
4000
4001         pci_set_master(pci);
4002
4003         for (idx = 0; idx < 5; idx++) {
4004                 region = &chip->region.idx[idx];
4005                 if ((region->resource = request_mem_region(region->base, region->size,
4006                                                            region->name)) == NULL) {
4007                         snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
4008                                    region->base, region->base + region->size - 1);
4009                         snd_cs46xx_free(chip);
4010                         return -EBUSY;
4011                 }
4012                 region->remap_addr = ioremap_nocache(region->base, region->size);
4013                 if (region->remap_addr == NULL) {
4014                         snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
4015                         snd_cs46xx_free(chip);
4016                         return -ENOMEM;
4017                 }
4018         }
4019
4020         if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
4021                         KBUILD_MODNAME, chip)) {
4022                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
4023                 snd_cs46xx_free(chip);
4024                 return -EBUSY;
4025         }
4026         chip->irq = pci->irq;
4027
4028 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4029         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4030         if (chip->dsp_spos_instance == NULL) {
4031                 snd_cs46xx_free(chip);
4032                 return -ENOMEM;
4033         }
4034 #endif
4035
4036         err = snd_cs46xx_chip_init(chip);
4037         if (err < 0) {
4038                 snd_cs46xx_free(chip);
4039                 return err;
4040         }
4041
4042         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4043                 snd_cs46xx_free(chip);
4044                 return err;
4045         }
4046
4047         snd_cs46xx_proc_init(card, chip);
4048
4049 #ifdef CONFIG_PM_SLEEP
4050         chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) *
4051                                    ARRAY_SIZE(saved_regs), GFP_KERNEL);
4052         if (!chip->saved_regs) {
4053                 snd_cs46xx_free(chip);
4054                 return -ENOMEM;
4055         }
4056 #endif
4057
4058         chip->active_ctrl(chip, -1); /* disable CLKRUN */
4059
4060         snd_card_set_dev(card, &pci->dev);
4061
4062         *rchip = chip;
4063         return 0;
4064 }