2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Routines for control of EMU10K1 chips
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added support for Audigy 2 Value.
8 * Added EMU 1010 support.
9 * General bug fixes and enhancements.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include <linux/sched.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/interrupt.h>
39 #include <linux/iommu.h>
40 #include <linux/pci.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/mutex.h>
46 #include <sound/core.h>
47 #include <sound/emu10k1.h>
48 #include <linux/firmware.h>
54 #define HANA_FILENAME "emu/hana.fw"
55 #define DOCK_FILENAME "emu/audio_dock.fw"
56 #define EMU1010B_FILENAME "emu/emu1010b.fw"
57 #define MICRO_DOCK_FILENAME "emu/micro_dock.fw"
58 #define EMU0404_FILENAME "emu/emu0404.fw"
59 #define EMU1010_NOTEBOOK_FILENAME "emu/emu1010_notebook.fw"
61 MODULE_FIRMWARE(HANA_FILENAME);
62 MODULE_FIRMWARE(DOCK_FILENAME);
63 MODULE_FIRMWARE(EMU1010B_FILENAME);
64 MODULE_FIRMWARE(MICRO_DOCK_FILENAME);
65 MODULE_FIRMWARE(EMU0404_FILENAME);
66 MODULE_FIRMWARE(EMU1010_NOTEBOOK_FILENAME);
69 /*************************************************************************
71 *************************************************************************/
73 void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
75 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
76 snd_emu10k1_ptr_write(emu, IP, ch, 0);
77 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
78 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
79 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
80 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
81 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
83 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
84 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
85 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
86 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
87 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
88 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
90 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
91 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
92 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
93 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
94 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
95 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
96 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
97 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
99 /*** these are last so OFF prevents writing ***/
100 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
101 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
102 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
103 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
104 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
106 /* Audigy extra stuffs */
108 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
109 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
110 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
111 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
112 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
113 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
114 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
118 static unsigned int spi_dac_init[] = {
142 static unsigned int i2c_adc_init[][2] = {
143 { 0x17, 0x00 }, /* Reset */
144 { 0x07, 0x00 }, /* Timeout */
145 { 0x0b, 0x22 }, /* Interface control */
146 { 0x0c, 0x22 }, /* Master mode control */
147 { 0x0d, 0x08 }, /* Powerdown control */
148 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
149 { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
150 { 0x10, 0x7b }, /* ALC Control 1 */
151 { 0x11, 0x00 }, /* ALC Control 2 */
152 { 0x12, 0x32 }, /* ALC Control 3 */
153 { 0x13, 0x00 }, /* Noise gate control */
154 { 0x14, 0xa6 }, /* Limiter control */
155 { 0x15, ADC_MUX_2 }, /* ADC Mixer control. Mic for A2ZS Notebook */
158 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
160 unsigned int silent_page;
164 /* disable audio and lock cache */
165 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
166 HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
168 /* reset recording buffers */
169 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
170 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
171 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
172 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
173 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
174 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
176 /* disable channel interrupt */
177 outl(0, emu->port + INTE);
178 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
179 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
180 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
181 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
184 /* set SPDIF bypass mode */
185 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
186 /* enable rear left + rear right AC97 slots */
187 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
191 /* init envelope engine */
192 for (ch = 0; ch < NUM_G; ch++)
193 snd_emu10k1_voice_init(emu, ch);
195 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
196 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
197 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
199 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
200 /* Hacks for Alice3 to work independent of haP16V driver */
201 /* Setup SRCMulti_I2S SamplingRate */
202 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
205 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
207 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
208 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
209 /* Setup SRCMulti Input Audio Enable */
210 /* Use 0xFFFFFFFF to enable P16V sounds. */
211 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
213 /* Enabled Phased (8-channel) P16V playback */
214 outl(0x0201, emu->port + HCFG2);
215 /* Set playback routing. */
216 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
218 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
219 /* Hacks for Alice3 to work independent of haP16V driver */
220 dev_info(emu->card->dev, "Audigy2 value: Special config.\n");
221 /* Setup SRCMulti_I2S SamplingRate */
222 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
225 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
227 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
228 outl(0x600000, emu->port + 0x20);
229 outl(0x14, emu->port + 0x24);
231 /* Setup SRCMulti Input Audio Enable */
232 outl(0x7b0000, emu->port + 0x20);
233 outl(0xFF000000, emu->port + 0x24);
235 /* Setup SPDIF Out Audio Enable */
236 /* The Audigy 2 Value has a separate SPDIF out,
237 * so no need for a mixer switch
239 outl(0x7a0000, emu->port + 0x20);
240 outl(0xFF000000, emu->port + 0x24);
241 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
242 outl(tmp, emu->port + A_IOCFG);
244 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
247 size = ARRAY_SIZE(spi_dac_init);
248 for (n = 0; n < size; n++)
249 snd_emu10k1_spi_write(emu, spi_dac_init[n]);
251 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
254 * GPIO1: Speakers-enabled.
257 * GPIO4: IEC958 Output on.
262 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
264 if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
267 snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
268 tmp = inl(emu->port + A_IOCFG);
269 outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
270 tmp = inl(emu->port + A_IOCFG);
271 size = ARRAY_SIZE(i2c_adc_init);
272 for (n = 0; n < size; n++)
273 snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
274 for (n = 0; n < 4; n++) {
275 emu->i2c_capture_volume[n][0] = 0xcf;
276 emu->i2c_capture_volume[n][1] = 0xcf;
281 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
282 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
283 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
285 silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
286 for (ch = 0; ch < NUM_G; ch++) {
287 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
288 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
291 if (emu->card_capabilities->emu_model) {
292 outl(HCFG_AUTOMUTE_ASYNC |
294 HCFG_AUDIOENABLE, emu->port + HCFG);
297 * Mute Disable Audio = 0
298 * Lock Tank Memory = 1
299 * Lock Sound Memory = 0
302 } else if (emu->audigy) {
303 if (emu->revision == 4) /* audigy2 */
304 outl(HCFG_AUDIOENABLE |
305 HCFG_AC3ENABLE_CDSPDIF |
306 HCFG_AC3ENABLE_GPSPDIF |
307 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
309 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
310 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
311 * e.g. card_capabilities->joystick */
312 } else if (emu->model == 0x20 ||
313 emu->model == 0xc400 ||
314 (emu->model == 0x21 && emu->revision < 6))
315 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
317 /* With on-chip joystick */
318 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
320 if (enable_ir) { /* enable IR for SB Live */
321 if (emu->card_capabilities->emu_model) {
322 ; /* Disable all access to A_IOCFG for the emu1010 */
323 } else if (emu->card_capabilities->i2c_adc) {
324 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
325 } else if (emu->audigy) {
326 unsigned int reg = inl(emu->port + A_IOCFG);
327 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
329 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
331 outl(reg, emu->port + A_IOCFG);
333 unsigned int reg = inl(emu->port + HCFG);
334 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
336 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
338 outl(reg, emu->port + HCFG);
342 if (emu->card_capabilities->emu_model) {
343 ; /* Disable all access to A_IOCFG for the emu1010 */
344 } else if (emu->card_capabilities->i2c_adc) {
345 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
346 } else if (emu->audigy) { /* enable analog output */
347 unsigned int reg = inl(emu->port + A_IOCFG);
348 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
351 if (emu->address_mode == 0) {
353 outl(inl(emu->port + HCFG) | HCFG_EXPANDED_MEM, emu->port + HCFG);
359 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
362 * Enable the audio bit
364 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
366 /* Enable analog/digital outs on audigy */
367 if (emu->card_capabilities->emu_model) {
368 ; /* Disable all access to A_IOCFG for the emu1010 */
369 } else if (emu->card_capabilities->i2c_adc) {
370 ; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
371 } else if (emu->audigy) {
372 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
374 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
375 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
376 * This has to be done after init ALice3 I2SOut beyond 48KHz.
377 * So, sequence is important. */
378 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
379 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
380 /* Unmute Analog now. */
381 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
383 /* Disable routing from AC97 line out to Front speakers */
384 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
391 /* FIXME: the following routine disables LiveDrive-II !! */
392 /* TOSLink detection */
394 tmp = inl(emu->port + HCFG);
395 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
396 outl(tmp|0x800, emu->port + HCFG);
398 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
400 outl(tmp, emu->port + HCFG);
406 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
409 int snd_emu10k1_done(struct snd_emu10k1 *emu)
413 outl(0, emu->port + INTE);
418 for (ch = 0; ch < NUM_G; ch++)
419 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
420 for (ch = 0; ch < NUM_G; ch++) {
421 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
422 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
423 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
424 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
427 /* reset recording buffers */
428 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
429 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
430 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
431 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
432 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
433 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
434 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
435 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
436 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
438 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
440 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
442 /* disable channel interrupt */
443 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
444 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
445 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
446 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
448 /* disable audio and lock cache */
449 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
450 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
455 /*************************************************************************
456 * ECARD functional implementation
457 *************************************************************************/
459 /* In A1 Silicon, these bits are in the HC register */
460 #define HOOKN_BIT (1L << 12)
461 #define HANDN_BIT (1L << 11)
462 #define PULSEN_BIT (1L << 10)
464 #define EC_GDI1 (1 << 13)
465 #define EC_GDI0 (1 << 14)
467 #define EC_NUM_CONTROL_BITS 20
469 #define EC_AC3_DATA_SELN 0x0001L
470 #define EC_EE_DATA_SEL 0x0002L
471 #define EC_EE_CNTRL_SELN 0x0004L
472 #define EC_EECLK 0x0008L
473 #define EC_EECS 0x0010L
474 #define EC_EESDO 0x0020L
475 #define EC_TRIM_CSN 0x0040L
476 #define EC_TRIM_SCLK 0x0080L
477 #define EC_TRIM_SDATA 0x0100L
478 #define EC_TRIM_MUTEN 0x0200L
479 #define EC_ADCCAL 0x0400L
480 #define EC_ADCRSTN 0x0800L
481 #define EC_DACCAL 0x1000L
482 #define EC_DACMUTEN 0x2000L
483 #define EC_LEDN 0x4000L
485 #define EC_SPDIF0_SEL_SHIFT 15
486 #define EC_SPDIF1_SEL_SHIFT 17
487 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
488 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
489 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
490 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
491 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
492 * be incremented any time the EEPROM's
493 * format is changed. */
495 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
497 /* Addresses for special values stored in to EEPROM */
498 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
499 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
500 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
502 #define EC_LAST_PROMFILE_ADDR 0x2f
504 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
505 * can be up to 30 characters in length
506 * and is stored as a NULL-terminated
507 * ASCII string. Any unused bytes must be
508 * filled with zeros */
509 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
512 /* Most of this stuff is pretty self-evident. According to the hardware
513 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
514 * offset problem. Weird.
516 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
520 #define EC_DEFAULT_ADC_GAIN 0xC4C4
521 #define EC_DEFAULT_SPDIF0_SEL 0x0
522 #define EC_DEFAULT_SPDIF1_SEL 0x4
524 /**************************************************************************
525 * @func Clock bits into the Ecard's control latch. The Ecard uses a
526 * control latch will is loaded bit-serially by toggling the Modem control
527 * lines from function 2 on the E8010. This function hides these details
528 * and presents the illusion that we are actually writing to a distinct
532 static void snd_emu10k1_ecard_write(struct snd_emu10k1 *emu, unsigned int value)
534 unsigned short count;
536 unsigned long hc_port;
537 unsigned int hc_value;
539 hc_port = emu->port + HCFG;
540 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
541 outl(hc_value, hc_port);
543 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
545 /* Set up the value */
546 data = ((value & 0x1) ? PULSEN_BIT : 0);
549 outl(hc_value | data, hc_port);
551 /* Clock the shift register */
552 outl(hc_value | data | HANDN_BIT, hc_port);
553 outl(hc_value | data, hc_port);
557 outl(hc_value | HOOKN_BIT, hc_port);
558 outl(hc_value, hc_port);
561 /**************************************************************************
562 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
563 * trim value consists of a 16bit value which is composed of two
564 * 8 bit gain/trim values, one for the left channel and one for the
565 * right channel. The following table maps from the Gain/Attenuation
566 * value in decibels into the corresponding bit pattern for a single
570 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 *emu,
575 /* Enable writing to the TRIM registers */
576 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
578 /* Do it again to insure that we meet hold time requirements */
579 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
581 for (bit = (1 << 15); bit; bit >>= 1) {
584 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
587 value |= EC_TRIM_SDATA;
590 snd_emu10k1_ecard_write(emu, value);
591 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
592 snd_emu10k1_ecard_write(emu, value);
595 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
598 static int snd_emu10k1_ecard_init(struct snd_emu10k1 *emu)
600 unsigned int hc_value;
602 /* Set up the initial settings */
603 emu->ecard_ctrl = EC_RAW_RUN_MODE |
604 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
605 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
607 /* Step 0: Set the codec type in the hardware control register
608 * and enable audio output */
609 hc_value = inl(emu->port + HCFG);
610 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
611 inl(emu->port + HCFG);
613 /* Step 1: Turn off the led and deassert TRIM_CS */
614 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
616 /* Step 2: Calibrate the ADC and DAC */
617 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
619 /* Step 3: Wait for awhile; XXX We can't get away with this
620 * under a real operating system; we'll need to block and wait that
622 snd_emu10k1_wait(emu, 48000);
624 /* Step 4: Switch off the DAC and ADC calibration. Note
625 * That ADC_CAL is actually an inverted signal, so we assert
626 * it here to stop calibration. */
627 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
629 /* Step 4: Switch into run mode */
630 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
632 /* Step 5: Set the analog input gain */
633 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
638 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 *emu)
640 unsigned long special_port;
643 /* Special initialisation routine
644 * before the rest of the IO-Ports become active.
646 special_port = emu->port + 0x38;
647 value = inl(special_port);
648 outl(0x00d00000, special_port);
649 value = inl(special_port);
650 outl(0x00d00001, special_port);
651 value = inl(special_port);
652 outl(0x00d0005f, special_port);
653 value = inl(special_port);
654 outl(0x00d0007f, special_port);
655 value = inl(special_port);
656 outl(0x0090007f, special_port);
657 value = inl(special_port);
659 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
660 /* Delay to give time for ADC chip to switch on. It needs 113ms */
665 static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
666 const struct firmware *fw_entry)
671 unsigned int write_post;
677 /* The FPGA is a Xilinx Spartan IIE XC2S50E */
678 /* GPIO7 -> FPGA PGMN
681 * FPGA CONFIG OFF -> FPGA PGMN
683 spin_lock_irqsave(&emu->emu_lock, flags);
684 outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
685 write_post = inl(emu->port + A_IOCFG);
687 outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
688 write_post = inl(emu->port + A_IOCFG);
689 udelay(100); /* Allow FPGA memory to clean */
690 for (n = 0; n < fw_entry->size; n++) {
691 value = fw_entry->data[n];
692 for (i = 0; i < 8; i++) {
697 outl(reg, emu->port + A_IOCFG);
698 write_post = inl(emu->port + A_IOCFG);
699 outl(reg | 0x40, emu->port + A_IOCFG);
700 write_post = inl(emu->port + A_IOCFG);
703 /* After programming, set GPIO bit 4 high again. */
704 outl(0x10, emu->port + A_IOCFG);
705 write_post = inl(emu->port + A_IOCFG);
706 spin_unlock_irqrestore(&emu->emu_lock, flags);
711 /* firmware file names, per model, init-fw and dock-fw (optional) */
712 static const char * const firmware_names[5][2] = {
713 [EMU_MODEL_EMU1010] = {
714 HANA_FILENAME, DOCK_FILENAME
716 [EMU_MODEL_EMU1010B] = {
717 EMU1010B_FILENAME, MICRO_DOCK_FILENAME
719 [EMU_MODEL_EMU1616] = {
720 EMU1010_NOTEBOOK_FILENAME, MICRO_DOCK_FILENAME
722 [EMU_MODEL_EMU0404] = {
723 EMU0404_FILENAME, NULL
727 static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu, int dock,
728 const struct firmware **fw)
730 const char *filename;
734 filename = firmware_names[emu->card_capabilities->emu_model][dock];
737 err = request_firmware(fw, filename, &emu->pci->dev);
742 return snd_emu1010_load_firmware_entry(emu, *fw);
745 static void emu1010_firmware_work(struct work_struct *work)
747 struct snd_emu10k1 *emu;
751 emu = container_of(work, struct snd_emu10k1,
752 emu1010.firmware_work.work);
753 if (emu->card->shutdown)
755 #ifdef CONFIG_PM_SLEEP
759 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp); /* IRQ Status */
760 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */
761 if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) {
762 /* Audio Dock attached */
763 /* Return to Audio Dock programming mode */
764 dev_info(emu->card->dev,
765 "emu1010: Loading Audio Dock Firmware\n");
766 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
767 EMU_HANA_FPGA_CONFIG_AUDIODOCK);
768 err = snd_emu1010_load_firmware(emu, 1, &emu->dock_fw);
772 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
773 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp);
774 dev_info(emu->card->dev,
775 "emu1010: EMU_HANA+DOCK_IRQ_STATUS = 0x%x\n", tmp);
776 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
777 snd_emu1010_fpga_read(emu, EMU_HANA_ID, &tmp);
778 dev_info(emu->card->dev,
779 "emu1010: EMU_HANA+DOCK_ID = 0x%x\n", tmp);
780 if ((tmp & 0x1f) != 0x15) {
781 /* FPGA failed to be programmed */
782 dev_info(emu->card->dev,
783 "emu1010: Loading Audio Dock Firmware file failed, reg = 0x%x\n",
787 dev_info(emu->card->dev,
788 "emu1010: Audio Dock Firmware loaded\n");
789 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp);
790 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2);
791 dev_info(emu->card->dev, "Audio Dock ver: %u.%u\n", tmp, tmp2);
792 /* Sync clocking between 1010 and Dock */
793 /* Allow DLL to settle */
795 /* Unmute all. Default is muted after a firmware load */
796 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
797 } else if (!reg && emu->emu1010.last_reg) {
798 /* Audio Dock removed */
799 dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
801 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
805 emu->emu1010.last_reg = reg;
806 if (!emu->card->shutdown)
807 schedule_delayed_work(&emu->emu1010.firmware_work,
808 msecs_to_jiffies(1000));
812 * EMU-1010 - details found out from this driver, official MS Win drivers,
815 * Audigy2 (aka Alice2):
816 * ---------------------
817 * * communication over PCI
818 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
819 * to 2 x 16-bit, using internal DSP instructions
820 * * slave mode, clock supplied by HANA
821 * * linked to HANA using:
822 * 32 x 32-bit serial EMU32 output channels
823 * 16 x EMU32 input channels
824 * (?) x I2S I/O channels (?)
828 * * provides all (?) physical inputs and outputs of the card
829 * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
830 * * provides clock signal for the card and Alice2
831 * * two crystals - for 44.1kHz and 48kHz multiples
832 * * provides internal routing of signal sources to signal destinations
833 * * inputs/outputs to Alice2 - see above
835 * Current status of the driver:
836 * ----------------------------
837 * * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
838 * * PCM device nb. 2:
839 * 16 x 16-bit playback - snd_emu10k1_fx8010_playback_ops
840 * 16 x 32-bit capture - snd_emu10k1_capture_efx_ops
842 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
848 dev_info(emu->card->dev, "emu1010: Special config.\n");
849 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
850 * Lock Sound Memory Cache, Lock Tank Memory Cache,
853 outl(0x0005a00c, emu->port + HCFG);
854 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
855 * Lock Tank Memory Cache,
858 outl(0x0005a004, emu->port + HCFG);
859 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
862 outl(0x0005a000, emu->port + HCFG);
863 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
866 outl(0x0005a000, emu->port + HCFG);
868 /* Disable 48Volt power to Audio Dock */
869 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
871 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
872 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
873 dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg);
874 if ((reg & 0x3f) == 0x15) {
875 /* FPGA netlist already present so clear it */
876 /* Return to programming mode */
878 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
880 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
881 dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
882 if ((reg & 0x3f) == 0x15) {
883 /* FPGA failed to return to programming mode */
884 dev_info(emu->card->dev,
885 "emu1010: FPGA failed to return to programming mode\n");
888 dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg);
890 err = snd_emu1010_load_firmware(emu, 0, &emu->firmware);
892 dev_info(emu->card->dev, "emu1010: Loading Firmware failed\n");
896 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
897 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
898 if ((reg & 0x3f) != 0x15) {
899 /* FPGA failed to be programmed */
900 dev_info(emu->card->dev,
901 "emu1010: Loading Hana Firmware file failed, reg = 0x%x\n",
906 dev_info(emu->card->dev, "emu1010: Hana Firmware loaded\n");
907 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp);
908 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2);
909 dev_info(emu->card->dev, "emu1010: Hana version: %u.%u\n", tmp, tmp2);
910 /* Enable 48Volt power to Audio Dock */
911 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON);
913 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
914 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
915 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
916 dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
917 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp);
918 /* Optical -> ADAT I/O */
922 emu->emu1010.optical_in = 1; /* IN_ADAT */
923 emu->emu1010.optical_out = 1; /* IN_ADAT */
925 tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
926 (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
927 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
928 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp);
929 /* Set no attenuation on Audio Dock pads. */
930 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
931 emu->emu1010.adc_pads = 0x00;
932 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
933 /* Unmute Audio dock DACs, Headphone source DAC-4. */
934 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
935 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
936 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp);
938 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
939 emu->emu1010.dac_pads = 0x0f;
940 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp);
941 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
942 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
943 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
944 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
946 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
948 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
949 /* IRQ Enable: All on */
950 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
951 /* IRQ Enable: All off */
952 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
954 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
955 dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg);
956 /* Default WCLK set to 48kHz. */
957 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
958 /* Word Clock source, Internal 48kHz x1 */
959 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
960 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
961 /* Audio Dock LEDs. */
962 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
966 snd_emu1010_fpga_link_dst_src_write(emu,
967 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
968 snd_emu1010_fpga_link_dst_src_write(emu,
969 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
970 snd_emu1010_fpga_link_dst_src_write(emu,
971 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
972 snd_emu1010_fpga_link_dst_src_write(emu,
973 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
977 snd_emu1010_fpga_link_dst_src_write(emu,
978 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
979 snd_emu1010_fpga_link_dst_src_write(emu,
980 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
981 snd_emu1010_fpga_link_dst_src_write(emu,
982 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
983 snd_emu1010_fpga_link_dst_src_write(emu,
984 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
985 snd_emu1010_fpga_link_dst_src_write(emu,
986 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
987 snd_emu1010_fpga_link_dst_src_write(emu,
988 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
989 snd_emu1010_fpga_link_dst_src_write(emu,
990 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
991 snd_emu1010_fpga_link_dst_src_write(emu,
992 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
996 snd_emu1010_fpga_link_dst_src_write(emu,
997 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
998 snd_emu1010_fpga_link_dst_src_write(emu,
999 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
1000 snd_emu1010_fpga_link_dst_src_write(emu,
1001 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
1002 snd_emu1010_fpga_link_dst_src_write(emu,
1003 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
1004 snd_emu1010_fpga_link_dst_src_write(emu,
1005 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
1006 snd_emu1010_fpga_link_dst_src_write(emu,
1007 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
1008 snd_emu1010_fpga_link_dst_src_write(emu,
1009 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
1010 snd_emu1010_fpga_link_dst_src_write(emu,
1011 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
1012 /* Pavel Hofman - setting defaults for 8 more capture channels
1013 * Defaults only, users will set their own values anyways, let's
1017 snd_emu1010_fpga_link_dst_src_write(emu,
1018 EMU_DST_ALICE2_EMU32_8, EMU_SRC_DOCK_MIC_A1);
1019 snd_emu1010_fpga_link_dst_src_write(emu,
1020 EMU_DST_ALICE2_EMU32_9, EMU_SRC_DOCK_MIC_B1);
1021 snd_emu1010_fpga_link_dst_src_write(emu,
1022 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HAMOA_ADC_LEFT2);
1023 snd_emu1010_fpga_link_dst_src_write(emu,
1024 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HAMOA_ADC_LEFT2);
1025 snd_emu1010_fpga_link_dst_src_write(emu,
1026 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_ADC1_LEFT1);
1027 snd_emu1010_fpga_link_dst_src_write(emu,
1028 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_ADC1_RIGHT1);
1029 snd_emu1010_fpga_link_dst_src_write(emu,
1030 EMU_DST_ALICE2_EMU32_E, EMU_SRC_DOCK_ADC2_LEFT1);
1031 snd_emu1010_fpga_link_dst_src_write(emu,
1032 EMU_DST_ALICE2_EMU32_F, EMU_SRC_DOCK_ADC2_RIGHT1);
1036 snd_emu1010_fpga_link_dst_src_write(emu,
1037 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
1038 snd_emu1010_fpga_link_dst_src_write(emu,
1039 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
1040 snd_emu1010_fpga_link_dst_src_write(emu,
1041 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
1042 snd_emu1010_fpga_link_dst_src_write(emu,
1043 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
1044 snd_emu1010_fpga_link_dst_src_write(emu,
1045 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
1046 snd_emu1010_fpga_link_dst_src_write(emu,
1047 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
1048 snd_emu1010_fpga_link_dst_src_write(emu,
1049 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
1050 snd_emu1010_fpga_link_dst_src_write(emu,
1051 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
1052 snd_emu1010_fpga_link_dst_src_write(emu,
1053 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
1054 snd_emu1010_fpga_link_dst_src_write(emu,
1055 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
1056 snd_emu1010_fpga_link_dst_src_write(emu,
1057 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
1058 snd_emu1010_fpga_link_dst_src_write(emu,
1059 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
1061 for (i = 0; i < 0x20; i++) {
1062 /* AudioDock Elink <- Silence */
1063 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100 + i, EMU_SRC_SILENCE);
1065 for (i = 0; i < 4; i++) {
1066 /* Hana SPDIF Out <- Silence */
1067 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200 + i, EMU_SRC_SILENCE);
1069 for (i = 0; i < 7; i++) {
1070 /* Hamoa DAC <- Silence */
1071 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300 + i, EMU_SRC_SILENCE);
1073 for (i = 0; i < 7; i++) {
1074 /* Hana ADAT Out <- Silence */
1075 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
1077 snd_emu1010_fpga_link_dst_src_write(emu,
1078 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
1079 snd_emu1010_fpga_link_dst_src_write(emu,
1080 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
1081 snd_emu1010_fpga_link_dst_src_write(emu,
1082 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
1083 snd_emu1010_fpga_link_dst_src_write(emu,
1084 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
1085 snd_emu1010_fpga_link_dst_src_write(emu,
1086 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
1087 snd_emu1010_fpga_link_dst_src_write(emu,
1088 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
1089 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
1091 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1093 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1094 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1097 outl(0x0000a000, emu->port + HCFG);
1098 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
1099 * Lock Sound Memory Cache, Lock Tank Memory Cache,
1100 * Un-Mute all codecs.
1102 outl(0x0000a001, emu->port + HCFG);
1104 /* Initial boot complete. Now patches */
1106 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp);
1107 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1108 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1109 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19); /* MIDI Route */
1110 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c); /* Unknown */
1111 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp);
1112 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
1115 snd_emu1010_fpga_link_dst_src_write(emu,
1116 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
1117 snd_emu1010_fpga_link_dst_src_write(emu,
1118 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
1119 snd_emu1010_fpga_link_dst_src_write(emu,
1120 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
1121 snd_emu1010_fpga_link_dst_src_write(emu,
1122 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
1124 /* Default outputs */
1125 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1616) {
1126 /* 1616(M) cardbus default outputs */
1127 /* ALICE2 bus 0xa0 */
1128 snd_emu1010_fpga_link_dst_src_write(emu,
1129 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1130 emu->emu1010.output_source[0] = 17;
1131 snd_emu1010_fpga_link_dst_src_write(emu,
1132 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1133 emu->emu1010.output_source[1] = 18;
1134 snd_emu1010_fpga_link_dst_src_write(emu,
1135 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1136 emu->emu1010.output_source[2] = 19;
1137 snd_emu1010_fpga_link_dst_src_write(emu,
1138 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1139 emu->emu1010.output_source[3] = 20;
1140 snd_emu1010_fpga_link_dst_src_write(emu,
1141 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1142 emu->emu1010.output_source[4] = 21;
1143 snd_emu1010_fpga_link_dst_src_write(emu,
1144 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1145 emu->emu1010.output_source[5] = 22;
1146 /* ALICE2 bus 0xa0 */
1147 snd_emu1010_fpga_link_dst_src_write(emu,
1148 EMU_DST_MANA_DAC_LEFT, EMU_SRC_ALICE_EMU32A + 0);
1149 emu->emu1010.output_source[16] = 17;
1150 snd_emu1010_fpga_link_dst_src_write(emu,
1151 EMU_DST_MANA_DAC_RIGHT, EMU_SRC_ALICE_EMU32A + 1);
1152 emu->emu1010.output_source[17] = 18;
1154 /* ALICE2 bus 0xa0 */
1155 snd_emu1010_fpga_link_dst_src_write(emu,
1156 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1157 emu->emu1010.output_source[0] = 21;
1158 snd_emu1010_fpga_link_dst_src_write(emu,
1159 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1160 emu->emu1010.output_source[1] = 22;
1161 snd_emu1010_fpga_link_dst_src_write(emu,
1162 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
1163 emu->emu1010.output_source[2] = 23;
1164 snd_emu1010_fpga_link_dst_src_write(emu,
1165 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
1166 emu->emu1010.output_source[3] = 24;
1167 snd_emu1010_fpga_link_dst_src_write(emu,
1168 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
1169 emu->emu1010.output_source[4] = 25;
1170 snd_emu1010_fpga_link_dst_src_write(emu,
1171 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
1172 emu->emu1010.output_source[5] = 26;
1173 snd_emu1010_fpga_link_dst_src_write(emu,
1174 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
1175 emu->emu1010.output_source[6] = 27;
1176 snd_emu1010_fpga_link_dst_src_write(emu,
1177 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
1178 emu->emu1010.output_source[7] = 28;
1179 /* ALICE2 bus 0xa0 */
1180 snd_emu1010_fpga_link_dst_src_write(emu,
1181 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1182 emu->emu1010.output_source[8] = 21;
1183 snd_emu1010_fpga_link_dst_src_write(emu,
1184 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1185 emu->emu1010.output_source[9] = 22;
1186 /* ALICE2 bus 0xa0 */
1187 snd_emu1010_fpga_link_dst_src_write(emu,
1188 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1189 emu->emu1010.output_source[10] = 21;
1190 snd_emu1010_fpga_link_dst_src_write(emu,
1191 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1192 emu->emu1010.output_source[11] = 22;
1193 /* ALICE2 bus 0xa0 */
1194 snd_emu1010_fpga_link_dst_src_write(emu,
1195 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1196 emu->emu1010.output_source[12] = 21;
1197 snd_emu1010_fpga_link_dst_src_write(emu,
1198 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1199 emu->emu1010.output_source[13] = 22;
1200 /* ALICE2 bus 0xa0 */
1201 snd_emu1010_fpga_link_dst_src_write(emu,
1202 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0);
1203 emu->emu1010.output_source[14] = 21;
1204 snd_emu1010_fpga_link_dst_src_write(emu,
1205 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
1206 emu->emu1010.output_source[15] = 22;
1207 /* ALICE2 bus 0xa0 */
1208 snd_emu1010_fpga_link_dst_src_write(emu,
1209 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0);
1210 emu->emu1010.output_source[16] = 21;
1211 snd_emu1010_fpga_link_dst_src_write(emu,
1212 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
1213 emu->emu1010.output_source[17] = 22;
1214 snd_emu1010_fpga_link_dst_src_write(emu,
1215 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
1216 emu->emu1010.output_source[18] = 23;
1217 snd_emu1010_fpga_link_dst_src_write(emu,
1218 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
1219 emu->emu1010.output_source[19] = 24;
1220 snd_emu1010_fpga_link_dst_src_write(emu,
1221 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
1222 emu->emu1010.output_source[20] = 25;
1223 snd_emu1010_fpga_link_dst_src_write(emu,
1224 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1225 emu->emu1010.output_source[21] = 26;
1226 snd_emu1010_fpga_link_dst_src_write(emu,
1227 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1228 emu->emu1010.output_source[22] = 27;
1229 snd_emu1010_fpga_link_dst_src_write(emu,
1230 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1231 emu->emu1010.output_source[23] = 28;
1233 /* TEMP: Select SPDIF in/out */
1234 /* snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); */ /* Output spdif */
1236 /* TEMP: Select 48kHz SPDIF out */
1237 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1238 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1239 /* Word Clock source, Internal 48kHz x1 */
1240 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
1241 /* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
1242 emu->emu1010.internal_clock = 1; /* 48000 */
1243 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12); /* Set LEDs on Audio Dock */
1244 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1245 /* snd_emu1010_fpga_write(emu, 0x7, 0x0); */ /* Mute all */
1246 /* snd_emu1010_fpga_write(emu, 0x7, 0x1); */ /* Unmute all */
1247 /* snd_emu1010_fpga_write(emu, 0xe, 0x12); */ /* Set LEDs on Audio Dock */
1252 * Create the EMU10K1 instance
1255 #ifdef CONFIG_PM_SLEEP
1256 static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1257 static void free_pm_buffer(struct snd_emu10k1 *emu);
1260 static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1262 if (emu->port) { /* avoid access to already used hardware */
1263 snd_emu10k1_fx8010_tram_setup(emu, 0);
1264 snd_emu10k1_done(emu);
1265 snd_emu10k1_free_efx(emu);
1267 if (emu->card_capabilities->emu_model == EMU_MODEL_EMU1010) {
1268 /* Disable 48Volt power to Audio Dock */
1269 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0);
1271 cancel_delayed_work_sync(&emu->emu1010.firmware_work);
1272 release_firmware(emu->firmware);
1273 release_firmware(emu->dock_fw);
1275 free_irq(emu->irq, emu);
1276 snd_util_memhdr_free(emu->memhdr);
1277 if (emu->silent_page.area)
1278 snd_dma_free_pages(&emu->silent_page);
1279 if (emu->ptb_pages.area)
1280 snd_dma_free_pages(&emu->ptb_pages);
1281 vfree(emu->page_ptr_table);
1282 vfree(emu->page_addr_table);
1283 #ifdef CONFIG_PM_SLEEP
1284 free_pm_buffer(emu);
1287 pci_release_regions(emu->pci);
1288 if (emu->card_capabilities->ca0151_chip) /* P16V */
1290 pci_disable_device(emu->pci);
1295 static int snd_emu10k1_dev_free(struct snd_device *device)
1297 struct snd_emu10k1 *emu = device->device_data;
1298 return snd_emu10k1_free(emu);
1301 static struct snd_emu_chip_details emu_chip_details[] = {
1302 /* Audigy 5/Rx SB1550 */
1303 /* Tested by michael@gernoth.net 28 Mar 2015 */
1304 /* DSP: CA10300-IAT LF
1305 * DAC: Cirrus Logic CS4382-KQZ
1306 * ADC: Philips 1361T
1307 * AC97: Sigmatel STAC9750
1310 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10241102,
1311 .driver = "Audigy2", .name = "SB Audigy 5/Rx [SB1550]",
1316 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1318 /* Audigy4 (Not PRO) SB0610 */
1319 /* Tested by James@superbug.co.uk 4th April 2006 */
1325 * 3: 0 - Digital Out, 1 - Line in
1333 * A: Green jack sense (Front)
1335 * C: Black jack sense (Rear/Side Right)
1336 * D: Yellow jack sense (Center/LFE/Side Left)
1340 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1344 /* Mic input not tested.
1345 * Analog CD input not tested
1346 * Digital Out not tested.
1348 * Audio output 5.1 working. Side outputs not working.
1350 /* DSP: CA10300-IAT LF
1351 * DAC: Cirrus Logic CS4382-KQZ
1352 * ADC: Philips 1361T
1353 * AC97: Sigmatel STAC9750
1356 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1357 .driver = "Audigy2", .name = "SB Audigy 4 [SB0610]",
1362 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1364 /* Audigy 2 Value AC3 out does not work yet.
1365 * Need to find out how to turn off interpolators.
1367 /* Tested by James@superbug.co.uk 3rd July 2005 */
1370 * ADC: Philips 1361T
1374 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1375 .driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
1381 /* Audigy 2 ZS Notebook Cardbus card.*/
1382 /* Tested by James@superbug.co.uk 6th November 2006 */
1383 /* Audio output 7.1/Headphones working.
1384 * Digital output working. (AC3 not checked, only PCM)
1385 * Audio Mic/Line inputs working.
1386 * Digital input not tested.
1389 * DAC: Wolfson WM8768/WM8568
1390 * ADC: Wolfson WM8775
1394 /* Tested by James@superbug.co.uk 4th April 2006 */
1398 * 1: 0 = Mute all the 7.1 channel out. 1 = unmute.
1399 * 2: Analog input 0 = line in, 1 = mic in
1401 * 4: Digital output 0 = off, 1 = on.
1406 * All bits 1 (0x3fxx) means nothing plugged in.
1407 * 8-9: 0 = Line in/Mic, 2 = Optical in, 3 = Nothing.
1408 * A-B: 0 = Headphones, 2 = Optical out, 3 = Nothing.
1409 * C-D: 2 = Front/Rear/etc, 3 = nothing.
1413 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1414 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1418 .ca_cardbus_chip = 1,
1422 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1423 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
1424 .driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
1428 .ca_cardbus_chip = 1,
1430 .emu_model = EMU_MODEL_EMU1616},
1431 /* Tested by James@superbug.co.uk 4th Nov 2007. */
1432 /* This is MAEM8960, 0202 is MAEM 8980 */
1433 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
1434 .driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
1439 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
1440 /* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
1441 /* This is MAEM8986, 0202 is MAEM8980 */
1442 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
1443 .driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
1448 .emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
1449 /* Tested by James@superbug.co.uk 8th July 2005. */
1450 /* This is MAEM8810, 0202 is MAEM8820 */
1451 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
1452 .driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
1457 .emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
1459 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
1460 .driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
1465 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
1466 /* Tested by James@superbug.co.uk 20-3-2007. */
1467 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
1468 .driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
1473 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
1475 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
1476 .driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
1481 .emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
1482 /* Note that all E-mu cards require kernel 2.6 or newer. */
1483 {.vendor = 0x1102, .device = 0x0008,
1484 .driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
1489 /* Tested by James@superbug.co.uk 3rd July 2005 */
1490 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1491 .driver = "Audigy2", .name = "SB Audigy 4 PRO [SB0380]",
1499 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
1500 /* The 0x20061102 does have SB0350 written on it
1501 * Just like 0x20021102
1503 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
1504 .driver = "Audigy2", .name = "SB Audigy 2 [SB0350b]",
1511 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1513 /* 0x20051102 also has SB0350 written on it, treated as Audigy 2 ZS by
1514 Creative's Windows driver */
1515 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20051102,
1516 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350a]",
1523 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1525 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1526 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0350]",
1533 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1535 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1536 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0360]",
1543 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1546 /* Tested by James@superbug.co.uk 3rd July 2005 */
1549 * ADC: Philips 1361T
1553 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1554 .driver = "Audigy2", .name = "SB Audigy 2 [SB0240]",
1561 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1563 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1564 .driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
1571 /* Dell OEM/Creative Labs Audigy 2 ZS */
1572 /* See ALSA bug#1365 */
1573 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1574 .driver = "Audigy2", .name = "SB Audigy 2 ZS [SB0353]",
1581 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1583 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1584 .driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
1591 .invert_shared_spdif = 1, /* digital/analog switch swapped */
1592 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1594 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1595 .driver = "Audigy2", .name = "SB Audigy 2 [Unknown]",
1602 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1603 .driver = "Audigy", .name = "SB Audigy 1 [SB0092]",
1608 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1609 .driver = "Audigy", .name = "SB Audigy 1 ES [SB0160]",
1615 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1616 .driver = "Audigy", .name = "SB Audigy 1 [SB0090]",
1621 {.vendor = 0x1102, .device = 0x0004,
1622 .driver = "Audigy", .name = "Audigy 1 [Unknown]",
1627 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1628 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1633 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806b1102,
1634 .driver = "EMU10K1", .name = "SB Live! [SB0105]",
1639 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806a1102,
1640 .driver = "EMU10K1", .name = "SB Live! Value [SB0103]",
1645 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1646 .driver = "EMU10K1", .name = "SB Live! Value [SB0101]",
1651 /* Tested by ALSA bug#1680 26th December 2005 */
1652 /* note: It really has SB0220 written on the card, */
1653 /* but it's SB0228 according to kx.inf */
1654 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1655 .driver = "EMU10K1", .name = "SB Live! 5.1 Dell OEM [SB0228]",
1660 /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1661 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1662 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0220]",
1667 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1668 .driver = "EMU10K1", .name = "SB Live! 5.1",
1673 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
1674 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
1675 .driver = "EMU10K1", .name = "SB Live! 5.1 [SB0060]",
1678 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1679 * share the same IDs!
1682 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1683 .driver = "EMU10K1", .name = "SB Live! Value [CT4850]",
1688 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1689 .driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
1693 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1694 .driver = "EMU10K1", .name = "SB Live! Value [CT4871]",
1699 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1700 .driver = "EMU10K1", .name = "SB Live! Value [CT4831]",
1705 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1706 .driver = "EMU10K1", .name = "SB Live! Value [CT4870]",
1711 /* Tested by James@superbug.co.uk 3rd July 2005 */
1712 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1713 .driver = "EMU10K1", .name = "SB Live! Value [CT4832]",
1718 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1719 .driver = "EMU10K1", .name = "SB Live! Value [CT4830]",
1724 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1725 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
1730 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1731 .driver = "EMU10K1", .name = "SB Live! Value [CT4780]",
1736 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1737 .driver = "EMU10K1", .name = "E-mu APS [PC545]",
1741 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1742 .driver = "EMU10K1", .name = "SB Live! [CT4620]",
1747 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1748 .driver = "EMU10K1", .name = "SB Live! Value [CT4670]",
1753 {.vendor = 0x1102, .device = 0x0002,
1754 .driver = "EMU10K1", .name = "SB Live! [Unknown]",
1759 { } /* terminator */
1763 * The chip (at least the Audigy 2 CA0102 chip, but most likely others, too)
1764 * has a problem that from time to time it likes to do few DMA reads a bit
1765 * beyond its normal allocation and gets very confused if these reads get
1766 * blocked by a IOMMU.
1768 * This behaviour has been observed for the first (reserved) page
1769 * (for which it happens multiple times at every playback), often for various
1770 * synth pages and sometimes for PCM playback buffers and the page table
1773 * As a workaround let's widen these DMA allocations by an extra page if we
1774 * detect that the device is behind a non-passthrough IOMMU.
1776 static void snd_emu10k1_detect_iommu(struct snd_emu10k1 *emu)
1778 struct iommu_domain *domain;
1780 emu->iommu_workaround = false;
1782 if (!iommu_present(emu->card->dev->bus))
1785 domain = iommu_get_domain_for_dev(emu->card->dev);
1786 if (domain && domain->type == IOMMU_DOMAIN_IDENTITY)
1789 dev_notice(emu->card->dev,
1790 "non-passthrough IOMMU detected, widening DMA allocations");
1791 emu->iommu_workaround = true;
1794 int snd_emu10k1_create(struct snd_card *card,
1795 struct pci_dev *pci,
1796 unsigned short extin_mask,
1797 unsigned short extout_mask,
1798 long max_cache_bytes,
1801 struct snd_emu10k1 **remu)
1803 struct snd_emu10k1 *emu;
1806 size_t page_table_size;
1807 unsigned int silent_page;
1808 const struct snd_emu_chip_details *c;
1809 static struct snd_device_ops ops = {
1810 .dev_free = snd_emu10k1_dev_free,
1815 /* enable PCI device */
1816 err = pci_enable_device(pci);
1820 emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1822 pci_disable_device(pci);
1826 spin_lock_init(&emu->reg_lock);
1827 spin_lock_init(&emu->emu_lock);
1828 spin_lock_init(&emu->spi_lock);
1829 spin_lock_init(&emu->i2c_lock);
1830 spin_lock_init(&emu->voice_lock);
1831 spin_lock_init(&emu->synth_lock);
1832 spin_lock_init(&emu->memblk_lock);
1833 mutex_init(&emu->fx8010.lock);
1834 INIT_LIST_HEAD(&emu->mapped_link_head);
1835 INIT_LIST_HEAD(&emu->mapped_order_link_head);
1839 emu->get_synth_voice = NULL;
1840 INIT_DELAYED_WORK(&emu->emu1010.firmware_work, emu1010_firmware_work);
1841 /* read revision & serial */
1842 emu->revision = pci->revision;
1843 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1844 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1846 "vendor = 0x%x, device = 0x%x, subsystem_vendor_id = 0x%x, subsystem_id = 0x%x\n",
1847 pci->vendor, pci->device, emu->serial, emu->model);
1849 for (c = emu_chip_details; c->vendor; c++) {
1850 if (c->vendor == pci->vendor && c->device == pci->device) {
1852 if (c->subsystem && (c->subsystem == subsystem))
1857 if (c->subsystem && (c->subsystem != emu->serial))
1859 if (c->revision && c->revision != emu->revision)
1865 if (c->vendor == 0) {
1866 dev_err(card->dev, "emu10k1: Card not recognised\n");
1868 pci_disable_device(pci);
1871 emu->card_capabilities = c;
1872 if (c->subsystem && !subsystem)
1873 dev_dbg(card->dev, "Sound card name = %s\n", c->name);
1875 dev_dbg(card->dev, "Sound card name = %s, "
1876 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x. "
1877 "Forced to subsystem = 0x%x\n", c->name,
1878 pci->vendor, pci->device, emu->serial, c->subsystem);
1880 dev_dbg(card->dev, "Sound card name = %s, "
1881 "vendor = 0x%x, device = 0x%x, subsystem = 0x%x.\n",
1882 c->name, pci->vendor, pci->device,
1885 if (!*card->id && c->id) {
1887 strlcpy(card->id, c->id, sizeof(card->id));
1889 for (i = 0; i < snd_ecards_limit; i++) {
1890 if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
1893 if (i >= snd_ecards_limit)
1896 if (n >= SNDRV_CARDS)
1898 snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
1902 is_audigy = emu->audigy = c->emu10k2_chip;
1904 snd_emu10k1_detect_iommu(emu);
1906 /* set addressing mode */
1907 emu->address_mode = is_audigy ? 0 : 1;
1908 /* set the DMA transfer mask */
1909 emu->dma_mask = emu->address_mode ? EMU10K1_DMA_MASK : AUDIGY_DMA_MASK;
1910 if (dma_set_mask_and_coherent(&pci->dev, emu->dma_mask) < 0) {
1912 "architecture does not support PCI busmaster DMA with mask 0x%lx\n",
1915 pci_disable_device(pci);
1919 emu->gpr_base = A_FXGPREGBASE;
1921 emu->gpr_base = FXGPREGBASE;
1923 err = pci_request_regions(pci, "EMU10K1");
1926 pci_disable_device(pci);
1929 emu->port = pci_resource_start(pci, 0);
1931 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1933 page_table_size = sizeof(u32) * (emu->address_mode ? MAXPAGES1 :
1935 if (snd_emu10k1_alloc_pages_maybe_wider(emu, page_table_size,
1936 &emu->ptb_pages) < 0) {
1940 dev_dbg(card->dev, "page table address range is %.8lx:%.8lx\n",
1941 (unsigned long)emu->ptb_pages.addr,
1942 (unsigned long)(emu->ptb_pages.addr + emu->ptb_pages.bytes));
1944 emu->page_ptr_table = vmalloc(emu->max_cache_pages * sizeof(void *));
1945 emu->page_addr_table = vmalloc(emu->max_cache_pages *
1946 sizeof(unsigned long));
1947 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
1952 if (snd_emu10k1_alloc_pages_maybe_wider(emu, EMUPAGESIZE,
1953 &emu->silent_page) < 0) {
1957 dev_dbg(card->dev, "silent page range is %.8lx:%.8lx\n",
1958 (unsigned long)emu->silent_page.addr,
1959 (unsigned long)(emu->silent_page.addr +
1960 emu->silent_page.bytes));
1962 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1963 if (emu->memhdr == NULL) {
1967 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1968 sizeof(struct snd_util_memblk);
1970 pci_set_master(pci);
1972 emu->fx8010.fxbus_mask = 0x303f;
1973 if (extin_mask == 0)
1974 extin_mask = 0x3fcf;
1975 if (extout_mask == 0)
1976 extout_mask = 0x7fff;
1977 emu->fx8010.extin_mask = extin_mask;
1978 emu->fx8010.extout_mask = extout_mask;
1979 emu->enable_ir = enable_ir;
1981 if (emu->card_capabilities->ca_cardbus_chip) {
1982 err = snd_emu10k1_cardbus_init(emu);
1986 if (emu->card_capabilities->ecard) {
1987 err = snd_emu10k1_ecard_init(emu);
1990 } else if (emu->card_capabilities->emu_model) {
1991 err = snd_emu10k1_emu1010_init(emu);
1993 snd_emu10k1_free(emu);
1997 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1998 does not support this, it shouldn't do any harm */
1999 snd_emu10k1_ptr_write(emu, AC97SLOT, 0,
2000 AC97SLOT_CNTR|AC97SLOT_LFE);
2003 /* initialize TRAM setup */
2004 emu->fx8010.itram_size = (16 * 1024)/2;
2005 emu->fx8010.etram_pages.area = NULL;
2006 emu->fx8010.etram_pages.bytes = 0;
2008 /* irq handler must be registered after I/O ports are activated */
2009 if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
2010 KBUILD_MODNAME, emu)) {
2014 emu->irq = pci->irq;
2017 * Init to 0x02109204 :
2018 * Clock accuracy = 0 (1000ppm)
2019 * Sample Rate = 2 (48kHz)
2020 * Audio Channel = 1 (Left of 2)
2021 * Source Number = 0 (Unspecified)
2022 * Generation Status = 1 (Original for Cat Code 12)
2023 * Cat Code = 12 (Digital Signal Mixer)
2025 * Emphasis = 0 (None)
2026 * CP = 1 (Copyright unasserted)
2027 * AN = 0 (Audio data)
2030 emu->spdif_bits[0] = emu->spdif_bits[1] =
2031 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
2032 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
2033 SPCS_GENERATIONSTATUS | 0x00001200 |
2034 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
2036 /* Clear silent pages and set up pointers */
2037 memset(emu->silent_page.area, 0, emu->silent_page.bytes);
2038 silent_page = emu->silent_page.addr << emu->address_mode;
2039 for (idx = 0; idx < (emu->address_mode ? MAXPAGES1 : MAXPAGES0); idx++)
2040 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
2042 /* set up voice indices */
2043 for (idx = 0; idx < NUM_G; idx++) {
2044 emu->voices[idx].emu = emu;
2045 emu->voices[idx].number = idx;
2048 err = snd_emu10k1_init(emu, enable_ir, 0);
2051 #ifdef CONFIG_PM_SLEEP
2052 err = alloc_pm_buffer(emu);
2057 /* Initialize the effect engine */
2058 err = snd_emu10k1_init_efx(emu);
2061 snd_emu10k1_audio_enable(emu);
2063 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops);
2067 #ifdef CONFIG_SND_PROC_FS
2068 snd_emu10k1_proc_init(emu);
2075 snd_emu10k1_free(emu);
2079 #ifdef CONFIG_PM_SLEEP
2080 static unsigned char saved_regs[] = {
2081 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
2082 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
2083 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
2084 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
2085 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
2086 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
2089 static unsigned char saved_regs_audigy[] = {
2090 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
2091 A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
2095 static int alloc_pm_buffer(struct snd_emu10k1 *emu)
2099 size = ARRAY_SIZE(saved_regs);
2101 size += ARRAY_SIZE(saved_regs_audigy);
2102 emu->saved_ptr = vmalloc(4 * NUM_G * size);
2103 if (!emu->saved_ptr)
2105 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
2107 if (emu->card_capabilities->ca0151_chip &&
2108 snd_p16v_alloc_pm_buffer(emu) < 0)
2113 static void free_pm_buffer(struct snd_emu10k1 *emu)
2115 vfree(emu->saved_ptr);
2116 snd_emu10k1_efx_free_pm_buffer(emu);
2117 if (emu->card_capabilities->ca0151_chip)
2118 snd_p16v_free_pm_buffer(emu);
2121 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
2127 val = emu->saved_ptr;
2128 for (reg = saved_regs; *reg != 0xff; reg++)
2129 for (i = 0; i < NUM_G; i++, val++)
2130 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2132 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2133 for (i = 0; i < NUM_G; i++, val++)
2134 *val = snd_emu10k1_ptr_read(emu, *reg, i);
2137 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
2138 emu->saved_hcfg = inl(emu->port + HCFG);
2141 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
2143 if (emu->card_capabilities->ca_cardbus_chip)
2144 snd_emu10k1_cardbus_init(emu);
2145 if (emu->card_capabilities->ecard)
2146 snd_emu10k1_ecard_init(emu);
2147 else if (emu->card_capabilities->emu_model)
2148 snd_emu10k1_emu1010_init(emu);
2150 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
2151 snd_emu10k1_init(emu, emu->enable_ir, 1);
2154 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
2160 snd_emu10k1_audio_enable(emu);
2162 /* resore for spdif */
2164 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
2165 outl(emu->saved_hcfg, emu->port + HCFG);
2167 val = emu->saved_ptr;
2168 for (reg = saved_regs; *reg != 0xff; reg++)
2169 for (i = 0; i < NUM_G; i++, val++)
2170 snd_emu10k1_ptr_write(emu, *reg, i, *val);
2172 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
2173 for (i = 0; i < NUM_G; i++, val++)
2174 snd_emu10k1_ptr_write(emu, *reg, i, *val);