sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68 };
  69
  70 /* Defines for ATI HD Audio support in SB450 south bridge */
  71 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  72 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  73
  74 /* Defines for Nvidia HDA support */
  75 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  76 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  77 #define NVIDIA_HDA_ISTRM_COH          0x4d
  78 #define NVIDIA_HDA_OSTRM_COH          0x4c
  79 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  80
  81 /* Defines for Intel SCH HDA snoop control */
  82 #define INTEL_HDA_CGCTL  0x48
  83 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  84 #define INTEL_SCH_HDA_DEVC      0x78
  85 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  86
  87 /* Define IN stream 0 FIFO size offset in VIA controller */
  88 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 165
 166 #ifdef CONFIG_PM
 167 static int param_set_xint(const char *val, const struct kernel_param *kp);
 168 static const struct kernel_param_ops param_ops_xint = {
 169         .set = param_set_xint,
 170         .get = param_get_int,
 171 };
 172 #define param_check_xint param_check_int
 173
 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 175 module_param(power_save, xint, 0644);
 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 177                  "(in second, 0 = disable).");
 178
 179 static bool pm_blacklist = true;
 180 module_param(pm_blacklist, bool, 0644);
 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 182
 183 /* reset the HD-audio controller in power save mode.
 184  * this may give more power-saving, but will take longer time to
 185  * wake up.
 186  */
 187 static bool power_save_controller = 1;
 188 module_param(power_save_controller, bool, 0644);
 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 190 #else
 191 #define power_save      0
 192 #endif /* CONFIG_PM */
 193
 194 static int align_buffer_size = -1;
 195 module_param(align_buffer_size, bint, 0644);
 196 MODULE_PARM_DESC(align_buffer_size,
 197                 "Force buffer and period sizes to be multiple of 128 bytes.");
 198
 199 #ifdef CONFIG_X86
 200 static int hda_snoop = -1;
 201 module_param_named(snoop, hda_snoop, bint, 0444);
 202 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 203 #else
 204 #define hda_snoop               true
 205 #endif
 206
 207
 208 MODULE_LICENSE("GPL");
 209 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 210                          "{Intel, ICH6M},"
 211                          "{Intel, ICH7},"
 212                          "{Intel, ESB2},"
 213                          "{Intel, ICH8},"
 214                          "{Intel, ICH9},"
 215                          "{Intel, ICH10},"
 216                          "{Intel, PCH},"
 217                          "{Intel, CPT},"
 218                          "{Intel, PPT},"
 219                          "{Intel, LPT},"
 220                          "{Intel, LPT_LP},"
 221                          "{Intel, WPT_LP},"
 222                          "{Intel, SPT},"
 223                          "{Intel, SPT_LP},"
 224                          "{Intel, HPT},"
 225                          "{Intel, PBG},"
 226                          "{Intel, SCH},"
 227                          "{ATI, SB450},"
 228                          "{ATI, SB600},"
 229                          "{ATI, RS600},"
 230                          "{ATI, RS690},"
 231                          "{ATI, RS780},"
 232                          "{ATI, R600},"
 233                          "{ATI, RV630},"
 234                          "{ATI, RV610},"
 235                          "{ATI, RV670},"
 236                          "{ATI, RV635},"
 237                          "{ATI, RV620},"
 238                          "{ATI, RV770},"
 239                          "{VIA, VT8251},"
 240                          "{VIA, VT8237A},"
 241                          "{SiS, SIS966},"
 242                          "{ULI, M5461}}");
 243 MODULE_DESCRIPTION("Intel HDA driver");
 244
 245 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 246 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 247 #define SUPPORT_VGA_SWITCHEROO
 248 #endif
 249 #endif
 250
 251
 252 /*
 253  */
 254
 255 /* driver types */
 256 enum {
 257         AZX_DRIVER_ICH,
 258         AZX_DRIVER_PCH,
 259         AZX_DRIVER_SCH,
 260         AZX_DRIVER_SKL,
 261         AZX_DRIVER_HDMI,
 262         AZX_DRIVER_ATI,
 263         AZX_DRIVER_ATIHDMI,
 264         AZX_DRIVER_ATIHDMI_NS,
 265         AZX_DRIVER_VIA,
 266         AZX_DRIVER_SIS,
 267         AZX_DRIVER_ULI,
 268         AZX_DRIVER_NVIDIA,
 269         AZX_DRIVER_TERA,
 270         AZX_DRIVER_CTX,
 271         AZX_DRIVER_CTHDA,
 272         AZX_DRIVER_CMEDIA,
 273         AZX_DRIVER_ZHAOXIN,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH))
 305
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH))
 311
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 322
 323 #define AZX_DCAPS_INTEL_BROXTON \
 324         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 325          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 326
 327 /* quirks for ATI SB / AMD Hudson */
 328 #define AZX_DCAPS_PRESET_ATI_SB \
 329         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 330          AZX_DCAPS_SNOOP_TYPE(ATI))
 331
 332 /* quirks for ATI/AMD HDMI */
 333 #define AZX_DCAPS_PRESET_ATI_HDMI \
 334         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 335          AZX_DCAPS_NO_MSI64)
 336
 337 /* quirks for ATI HDMI with snoop off */
 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 339         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 340
 341 /* quirks for Nvidia */
 342 #define AZX_DCAPS_PRESET_NVIDIA \
 343         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 344          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 345
 346 #define AZX_DCAPS_PRESET_CTHDA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 348          AZX_DCAPS_NO_64BIT |\
 349          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 350
 351 /*
 352  * vga_switcheroo support
 353  */
 354 #ifdef SUPPORT_VGA_SWITCHEROO
 355 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 356 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 357 #else
 358 #define use_vga_switcheroo(chip)        0
 359 #define needs_eld_notify_link(chip)     false
 360 #endif
 361
 362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 363                                         ((pci)->device == 0x0c0c) || \
 364                                         ((pci)->device == 0x0d0c) || \
 365                                         ((pci)->device == 0x160c))
 366
 367 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 368 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 369 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 370
 371 static char *driver_short_names[] = {
 372         [AZX_DRIVER_ICH] = "HDA Intel",
 373         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 374         [AZX_DRIVER_SCH] = "HDA Intel MID",
 375         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 376         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 377         [AZX_DRIVER_ATI] = "HDA ATI SB",
 378         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 379         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 380         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 381         [AZX_DRIVER_SIS] = "HDA SIS966",
 382         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 383         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 384         [AZX_DRIVER_TERA] = "HDA Teradici",
 385         [AZX_DRIVER_CTX] = "HDA Creative",
 386         [AZX_DRIVER_CTHDA] = "HDA Creative",
 387         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 388         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 389         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 390 };
 391
 392 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 393 static void set_default_power_save(struct azx *chip);
 394
 395 /*
 396  * initialize the PCI registers
 397  */
 398 /* update bits in a PCI register byte */
 399 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 400                             unsigned char mask, unsigned char val)
 401 {
 402         unsigned char data;
 403
 404         pci_read_config_byte(pci, reg, &data);
 405         data &= ~mask;
 406         data |= (val & mask);
 407         pci_write_config_byte(pci, reg, data);
 408 }
 409
 410 static void azx_init_pci(struct azx *chip)
 411 {
 412         int snoop_type = azx_get_snoop_type(chip);
 413
 414         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 415          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 416          * Ensuring these bits are 0 clears playback static on some HD Audio
 417          * codecs.
 418          * The PCI register TCSEL is defined in the Intel manuals.
 419          */
 420         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 421                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 422                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 423         }
 424
 425         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 426          * we need to enable snoop.
 427          */
 428         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 429                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 430                         azx_snoop(chip));
 431                 update_pci_byte(chip->pci,
 432                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 433                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 434         }
 435
 436         /* For NVIDIA HDA, enable snoop */
 437         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 438                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 439                         azx_snoop(chip));
 440                 update_pci_byte(chip->pci,
 441                                 NVIDIA_HDA_TRANSREG_ADDR,
 442                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 443                 update_pci_byte(chip->pci,
 444                                 NVIDIA_HDA_ISTRM_COH,
 445                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 446                 update_pci_byte(chip->pci,
 447                                 NVIDIA_HDA_OSTRM_COH,
 448                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 449         }
 450
 451         /* Enable SCH/PCH snoop if needed */
 452         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 453                 unsigned short snoop;
 454                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 455                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 456                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 457                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 458                         if (!azx_snoop(chip))
 459                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 460                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 461                         pci_read_config_word(chip->pci,
 462                                 INTEL_SCH_HDA_DEVC, &snoop);
 463                 }
 464                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 465                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 466                         "Disabled" : "Enabled");
 467         }
 468 }
 469
 470 /*
 471  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 472  * and makes an audio stream sensitive to system latencies when
 473  * 24/32 bits are playing.
 474  * Adjusting threshold of DMA fifo to force the DMA request
 475  * sooner to improve latency tolerance at the expense of power.
 476  */
 477 static void bxt_reduce_dma_latency(struct azx *chip)
 478 {
 479         u32 val;
 480
 481         val = azx_readl(chip, VS_EM4L);
 482         val &= (0x3 << 20);
 483         azx_writel(chip, VS_EM4L, val);
 484 }
 485
 486 /*
 487  * ML_LCAP bits:
 488  *  bit 0: 6 MHz Supported
 489  *  bit 1: 12 MHz Supported
 490  *  bit 2: 24 MHz Supported
 491  *  bit 3: 48 MHz Supported
 492  *  bit 4: 96 MHz Supported
 493  *  bit 5: 192 MHz Supported
 494  */
 495 static int intel_get_lctl_scf(struct azx *chip)
 496 {
 497         struct hdac_bus *bus = azx_bus(chip);
 498         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 499         u32 val, t;
 500         int i;
 501
 502         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 503
 504         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 505                 t = preferred_bits[i];
 506                 if (val & (1 << t))
 507                         return t;
 508         }
 509
 510         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 511         return 0;
 512 }
 513
 514 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 515 {
 516         struct hdac_bus *bus = azx_bus(chip);
 517         u32 val;
 518         int timeout;
 519
 520         /*
 521          * the codecs are sharing the first link setting by default
 522          * If other links are enabled for stream, they need similar fix
 523          */
 524         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 525         val &= ~AZX_MLCTL_SPA;
 526         val |= state << AZX_MLCTL_SPA_SHIFT;
 527         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 528         /* wait for CPA */
 529         timeout = 50;
 530         while (timeout) {
 531                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 532                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 533                         return 0;
 534                 timeout--;
 535                 udelay(10);
 536         }
 537
 538         return -1;
 539 }
 540
 541 static void intel_init_lctl(struct azx *chip)
 542 {
 543         struct hdac_bus *bus = azx_bus(chip);
 544         u32 val;
 545         int ret;
 546
 547         /* 0. check lctl register value is correct or not */
 548         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 549         /* if SCF is already set, let's use it */
 550         if ((val & ML_LCTL_SCF_MASK) != 0)
 551                 return;
 552
 553         /*
 554          * Before operating on SPA, CPA must match SPA.
 555          * Any deviation may result in undefined behavior.
 556          */
 557         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 558                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 559                 return;
 560
 561         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 562         ret = intel_ml_lctl_set_power(chip, 0);
 563         udelay(100);
 564         if (ret)
 565                 goto set_spa;
 566
 567         /* 2. update SCF to select a properly audio clock*/
 568         val &= ~ML_LCTL_SCF_MASK;
 569         val |= intel_get_lctl_scf(chip);
 570         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 571
 572 set_spa:
 573         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 574         intel_ml_lctl_set_power(chip, 1);
 575         udelay(100);
 576 }
 577
 578 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 579 {
 580         struct hdac_bus *bus = azx_bus(chip);
 581         struct pci_dev *pci = chip->pci;
 582         u32 val;
 583
 584         snd_hdac_set_codec_wakeup(bus, true);
 585         if (chip->driver_type == AZX_DRIVER_SKL) {
 586                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 587                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 588                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 589         }
 590         azx_init_chip(chip, full_reset);
 591         if (chip->driver_type == AZX_DRIVER_SKL) {
 592                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 593                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 594                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 595         }
 596
 597         snd_hdac_set_codec_wakeup(bus, false);
 598
 599         /* reduce dma latency to avoid noise */
 600         if (IS_BXT(pci))
 601                 bxt_reduce_dma_latency(chip);
 602
 603         if (bus->mlcap != NULL)
 604                 intel_init_lctl(chip);
 605 }
 606
 607 /* calculate runtime delay from LPIB */
 608 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 609                                    unsigned int pos)
 610 {
 611         struct snd_pcm_substream *substream = azx_dev->core.substream;
 612         int stream = substream->stream;
 613         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 614         int delay;
 615
 616         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 617                 delay = pos - lpib_pos;
 618         else
 619                 delay = lpib_pos - pos;
 620         if (delay < 0) {
 621                 if (delay >= azx_dev->core.delay_negative_threshold)
 622                         delay = 0;
 623                 else
 624                         delay += azx_dev->core.bufsize;
 625         }
 626
 627         if (delay >= azx_dev->core.period_bytes) {
 628                 dev_info(chip->card->dev,
 629                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 630                          delay, azx_dev->core.period_bytes);
 631                 delay = 0;
 632                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 633                 chip->get_delay[stream] = NULL;
 634         }
 635
 636         return bytes_to_frames(substream->runtime, delay);
 637 }
 638
 639 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 640
 641 /* called from IRQ */
 642 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 643 {
 644         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 645         int ok;
 646
 647         ok = azx_position_ok(chip, azx_dev);
 648         if (ok == 1) {
 649                 azx_dev->irq_pending = 0;
 650                 return ok;
 651         } else if (ok == 0) {
 652                 /* bogus IRQ, process it later */
 653                 azx_dev->irq_pending = 1;
 654                 schedule_work(&hda->irq_pending_work);
 655         }
 656         return 0;
 657 }
 658
 659 #define display_power(chip, enable) \
 660         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 661
 662 /*
 663  * Check whether the current DMA position is acceptable for updating
 664  * periods.  Returns non-zero if it's OK.
 665  *
 666  * Many HD-audio controllers appear pretty inaccurate about
 667  * the update-IRQ timing.  The IRQ is issued before actually the
 668  * data is processed.  So, we need to process it afterwords in a
 669  * workqueue.
 670  */
 671 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 672 {
 673         struct snd_pcm_substream *substream = azx_dev->core.substream;
 674         int stream = substream->stream;
 675         u32 wallclk;
 676         unsigned int pos;
 677
 678         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 679         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 680                 return -1;      /* bogus (too early) interrupt */
 681
 682         if (chip->get_position[stream])
 683                 pos = chip->get_position[stream](chip, azx_dev);
 684         else { /* use the position buffer as default */
 685                 pos = azx_get_pos_posbuf(chip, azx_dev);
 686                 if (!pos || pos == (u32)-1) {
 687                         dev_info(chip->card->dev,
 688                                  "Invalid position buffer, using LPIB read method instead.\n");
 689                         chip->get_position[stream] = azx_get_pos_lpib;
 690                         if (chip->get_position[0] == azx_get_pos_lpib &&
 691                             chip->get_position[1] == azx_get_pos_lpib)
 692                                 azx_bus(chip)->use_posbuf = false;
 693                         pos = azx_get_pos_lpib(chip, azx_dev);
 694                         chip->get_delay[stream] = NULL;
 695                 } else {
 696                         chip->get_position[stream] = azx_get_pos_posbuf;
 697                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 698                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 699                 }
 700         }
 701
 702         if (pos >= azx_dev->core.bufsize)
 703                 pos = 0;
 704
 705         if (WARN_ONCE(!azx_dev->core.period_bytes,
 706                       "hda-intel: zero azx_dev->period_bytes"))
 707                 return -1; /* this shouldn't happen! */
 708         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 709             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 710                 /* NG - it's below the first next period boundary */
 711                 return chip->bdl_pos_adj ? 0 : -1;
 712         azx_dev->core.start_wallclk += wallclk;
 713         return 1; /* OK, it's fine */
 714 }
 715
 716 /*
 717  * The work for pending PCM period updates.
 718  */
 719 static void azx_irq_pending_work(struct work_struct *work)
 720 {
 721         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 722         struct azx *chip = &hda->chip;
 723         struct hdac_bus *bus = azx_bus(chip);
 724         struct hdac_stream *s;
 725         int pending, ok;
 726
 727         if (!hda->irq_pending_warned) {
 728                 dev_info(chip->card->dev,
 729                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 730                          chip->card->number);
 731                 hda->irq_pending_warned = 1;
 732         }
 733
 734         for (;;) {
 735                 pending = 0;
 736                 spin_lock_irq(&bus->reg_lock);
 737                 list_for_each_entry(s, &bus->stream_list, list) {
 738                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 739                         if (!azx_dev->irq_pending ||
 740                             !s->substream ||
 741                             !s->running)
 742                                 continue;
 743                         ok = azx_position_ok(chip, azx_dev);
 744                         if (ok > 0) {
 745                                 azx_dev->irq_pending = 0;
 746                                 spin_unlock(&bus->reg_lock);
 747                                 snd_pcm_period_elapsed(s->substream);
 748                                 spin_lock(&bus->reg_lock);
 749                         } else if (ok < 0) {
 750                                 pending = 0;    /* too early */
 751                         } else
 752                                 pending++;
 753                 }
 754                 spin_unlock_irq(&bus->reg_lock);
 755                 if (!pending)
 756                         return;
 757                 msleep(1);
 758         }
 759 }
 760
 761 /* clear irq_pending flags and assure no on-going workq */
 762 static void azx_clear_irq_pending(struct azx *chip)
 763 {
 764         struct hdac_bus *bus = azx_bus(chip);
 765         struct hdac_stream *s;
 766
 767         spin_lock_irq(&bus->reg_lock);
 768         list_for_each_entry(s, &bus->stream_list, list) {
 769                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 770                 azx_dev->irq_pending = 0;
 771         }
 772         spin_unlock_irq(&bus->reg_lock);
 773 }
 774
 775 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 776 {
 777         struct hdac_bus *bus = azx_bus(chip);
 778
 779         if (request_irq(chip->pci->irq, azx_interrupt,
 780                         chip->msi ? 0 : IRQF_SHARED,
 781                         chip->card->irq_descr, chip)) {
 782                 dev_err(chip->card->dev,
 783                         "unable to grab IRQ %d, disabling device\n",
 784                         chip->pci->irq);
 785                 if (do_disconnect)
 786                         snd_card_disconnect(chip->card);
 787                 return -1;
 788         }
 789         bus->irq = chip->pci->irq;
 790         pci_intx(chip->pci, !chip->msi);
 791         return 0;
 792 }
 793
 794 /* get the current DMA position with correction on VIA chips */
 795 static unsigned int azx_via_get_position(struct azx *chip,
 796                                          struct azx_dev *azx_dev)
 797 {
 798         unsigned int link_pos, mini_pos, bound_pos;
 799         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 800         unsigned int fifo_size;
 801
 802         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 803         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 804                 /* Playback, no problem using link position */
 805                 return link_pos;
 806         }
 807
 808         /* Capture */
 809         /* For new chipset,
 810          * use mod to get the DMA position just like old chipset
 811          */
 812         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 813         mod_dma_pos %= azx_dev->core.period_bytes;
 814
 815         /* azx_dev->fifo_size can't get FIFO size of in stream.
 816          * Get from base address + offset.
 817          */
 818         fifo_size = readw(azx_bus(chip)->remap_addr +
 819                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 820
 821         if (azx_dev->insufficient) {
 822                 /* Link position never gather than FIFO size */
 823                 if (link_pos <= fifo_size)
 824                         return 0;
 825
 826                 azx_dev->insufficient = 0;
 827         }
 828
 829         if (link_pos <= fifo_size)
 830                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 831         else
 832                 mini_pos = link_pos - fifo_size;
 833
 834         /* Find nearest previous boudary */
 835         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 836         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 837         if (mod_link_pos >= fifo_size)
 838                 bound_pos = link_pos - mod_link_pos;
 839         else if (mod_dma_pos >= mod_mini_pos)
 840                 bound_pos = mini_pos - mod_mini_pos;
 841         else {
 842                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 843                 if (bound_pos >= azx_dev->core.bufsize)
 844                         bound_pos = 0;
 845         }
 846
 847         /* Calculate real DMA position we want */
 848         return bound_pos + mod_dma_pos;
 849 }
 850
 851 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 852                                          struct azx_dev *azx_dev)
 853 {
 854         return _snd_hdac_chip_readl(azx_bus(chip),
 855                                     AZX_REG_VS_SDXDPIB_XBASE +
 856                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 857                                      azx_dev->core.index));
 858 }
 859
 860 /* get the current DMA position with correction on SKL+ chips */
 861 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 862 {
 863         /* DPIB register gives a more accurate position for playback */
 864         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 865                 return azx_skl_get_dpib_pos(chip, azx_dev);
 866
 867         /* For capture, we need to read posbuf, but it requires a delay
 868          * for the possible boundary overlap; the read of DPIB fetches the
 869          * actual posbuf
 870          */
 871         udelay(20);
 872         azx_skl_get_dpib_pos(chip, azx_dev);
 873         return azx_get_pos_posbuf(chip, azx_dev);
 874 }
 875
 876 #ifdef CONFIG_PM
 877 static DEFINE_MUTEX(card_list_lock);
 878 static LIST_HEAD(card_list);
 879
 880 static void azx_add_card_list(struct azx *chip)
 881 {
 882         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 883         mutex_lock(&card_list_lock);
 884         list_add(&hda->list, &card_list);
 885         mutex_unlock(&card_list_lock);
 886 }
 887
 888 static void azx_del_card_list(struct azx *chip)
 889 {
 890         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 891         mutex_lock(&card_list_lock);
 892         list_del_init(&hda->list);
 893         mutex_unlock(&card_list_lock);
 894 }
 895
 896 /* trigger power-save check at writing parameter */
 897 static int param_set_xint(const char *val, const struct kernel_param *kp)
 898 {
 899         struct hda_intel *hda;
 900         struct azx *chip;
 901         int prev = power_save;
 902         int ret = param_set_int(val, kp);
 903
 904         if (ret || prev == power_save)
 905                 return ret;
 906
 907         mutex_lock(&card_list_lock);
 908         list_for_each_entry(hda, &card_list, list) {
 909                 chip = &hda->chip;
 910                 if (!hda->probe_continued || chip->disabled)
 911                         continue;
 912                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 913         }
 914         mutex_unlock(&card_list_lock);
 915         return 0;
 916 }
 917
 918 /*
 919  * power management
 920  */
 921 static bool azx_is_pm_ready(struct snd_card *card)
 922 {
 923         struct azx *chip;
 924         struct hda_intel *hda;
 925
 926         if (!card)
 927                 return false;
 928         chip = card->private_data;
 929         hda = container_of(chip, struct hda_intel, chip);
 930         if (chip->disabled || hda->init_failed || !chip->running)
 931                 return false;
 932         return true;
 933 }
 934
 935 static void __azx_runtime_suspend(struct azx *chip)
 936 {
 937         azx_stop_chip(chip);
 938         azx_enter_link_reset(chip);
 939         azx_clear_irq_pending(chip);
 940         display_power(chip, false);
 941 }
 942
 943 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 944 {
 945         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 946         struct hdac_bus *bus = azx_bus(chip);
 947         struct hda_codec *codec;
 948         int status;
 949
 950         display_power(chip, true);
 951         if (hda->need_i915_power)
 952                 snd_hdac_i915_set_bclk(bus);
 953
 954         /* Read STATESTS before controller reset */
 955         status = azx_readw(chip, STATESTS);
 956
 957         azx_init_pci(chip);
 958         hda_intel_init_chip(chip, true);
 959
 960         if (status && from_rt) {
 961                 list_for_each_codec(codec, &chip->bus)
 962                         if (status & (1 << codec->addr))
 963                                 schedule_delayed_work(&codec->jackpoll_work,
 964                                                       codec->jackpoll_interval);
 965         }
 966
 967         /* power down again for link-controlled chips */
 968         if (!hda->need_i915_power)
 969                 display_power(chip, false);
 970 }
 971
 972 #ifdef CONFIG_PM_SLEEP
 973 static int azx_suspend(struct device *dev)
 974 {
 975         struct snd_card *card = dev_get_drvdata(dev);
 976         struct azx *chip;
 977         struct hdac_bus *bus;
 978
 979         if (!azx_is_pm_ready(card))
 980                 return 0;
 981
 982         chip = card->private_data;
 983         bus = azx_bus(chip);
 984         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 985         __azx_runtime_suspend(chip);
 986         if (bus->irq >= 0) {
 987                 free_irq(bus->irq, chip);
 988                 bus->irq = -1;
 989         }
 990
 991         if (chip->msi)
 992                 pci_disable_msi(chip->pci);
 993
 994         trace_azx_suspend(chip);
 995         return 0;
 996 }
 997
 998 static int azx_resume(struct device *dev)
 999 {
1000         struct snd_card *card = dev_get_drvdata(dev);
1001         struct azx *chip;
1002
1003         if (!azx_is_pm_ready(card))
1004                 return 0;
1005
1006         chip = card->private_data;
1007         if (chip->msi)
1008                 if (pci_enable_msi(chip->pci) < 0)
1009                         chip->msi = 0;
1010         if (azx_acquire_irq(chip, 1) < 0)
1011                 return -EIO;
1012         __azx_runtime_resume(chip, false);
1013         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1014
1015         trace_azx_resume(chip);
1016         return 0;
1017 }
1018
1019 /* put codec down to D3 at hibernation for Intel SKL+;
1020  * otherwise BIOS may still access the codec and screw up the driver
1021  */
1022 static int azx_freeze_noirq(struct device *dev)
1023 {
1024         struct snd_card *card = dev_get_drvdata(dev);
1025         struct azx *chip = card->private_data;
1026         struct pci_dev *pci = to_pci_dev(dev);
1027
1028         if (chip->driver_type == AZX_DRIVER_SKL)
1029                 pci_set_power_state(pci, PCI_D3hot);
1030
1031         return 0;
1032 }
1033
1034 static int azx_thaw_noirq(struct device *dev)
1035 {
1036         struct snd_card *card = dev_get_drvdata(dev);
1037         struct azx *chip = card->private_data;
1038         struct pci_dev *pci = to_pci_dev(dev);
1039
1040         if (chip->driver_type == AZX_DRIVER_SKL)
1041                 pci_set_power_state(pci, PCI_D0);
1042
1043         return 0;
1044 }
1045 #endif /* CONFIG_PM_SLEEP */
1046
1047 static int azx_runtime_suspend(struct device *dev)
1048 {
1049         struct snd_card *card = dev_get_drvdata(dev);
1050         struct azx *chip;
1051
1052         if (!azx_is_pm_ready(card))
1053                 return 0;
1054         chip = card->private_data;
1055         if (!azx_has_pm_runtime(chip))
1056                 return 0;
1057
1058         /* enable controller wake up event */
1059         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1060                   STATESTS_INT_MASK);
1061
1062         __azx_runtime_suspend(chip);
1063         trace_azx_runtime_suspend(chip);
1064         return 0;
1065 }
1066
1067 static int azx_runtime_resume(struct device *dev)
1068 {
1069         struct snd_card *card = dev_get_drvdata(dev);
1070         struct azx *chip;
1071
1072         if (!azx_is_pm_ready(card))
1073                 return 0;
1074         chip = card->private_data;
1075         if (!azx_has_pm_runtime(chip))
1076                 return 0;
1077         __azx_runtime_resume(chip, true);
1078
1079         /* disable controller Wake Up event*/
1080         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1081                         ~STATESTS_INT_MASK);
1082
1083         trace_azx_runtime_resume(chip);
1084         return 0;
1085 }
1086
1087 static int azx_runtime_idle(struct device *dev)
1088 {
1089         struct snd_card *card = dev_get_drvdata(dev);
1090         struct azx *chip;
1091         struct hda_intel *hda;
1092
1093         if (!card)
1094                 return 0;
1095
1096         chip = card->private_data;
1097         hda = container_of(chip, struct hda_intel, chip);
1098         if (chip->disabled || hda->init_failed)
1099                 return 0;
1100
1101         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1102             azx_bus(chip)->codec_powered || !chip->running)
1103                 return -EBUSY;
1104
1105         /* ELD notification gets broken when HD-audio bus is off */
1106         if (needs_eld_notify_link(hda))
1107                 return -EBUSY;
1108
1109         return 0;
1110 }
1111
1112 static const struct dev_pm_ops azx_pm = {
1113         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1114 #ifdef CONFIG_PM_SLEEP
1115         .freeze_noirq = azx_freeze_noirq,
1116         .thaw_noirq = azx_thaw_noirq,
1117 #endif
1118         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1119 };
1120
1121 #define AZX_PM_OPS      &azx_pm
1122 #else
1123 #define azx_add_card_list(chip) /* NOP */
1124 #define azx_del_card_list(chip) /* NOP */
1125 #define AZX_PM_OPS      NULL
1126 #endif /* CONFIG_PM */
1127
1128
1129 static int azx_probe_continue(struct azx *chip);
1130
1131 #ifdef SUPPORT_VGA_SWITCHEROO
1132 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1133
1134 static void azx_vs_set_state(struct pci_dev *pci,
1135                              enum vga_switcheroo_state state)
1136 {
1137         struct snd_card *card = pci_get_drvdata(pci);
1138         struct azx *chip = card->private_data;
1139         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1140         struct hda_codec *codec;
1141         bool disabled;
1142
1143         wait_for_completion(&hda->probe_wait);
1144         if (hda->init_failed)
1145                 return;
1146
1147         disabled = (state == VGA_SWITCHEROO_OFF);
1148         if (chip->disabled == disabled)
1149                 return;
1150
1151         if (!hda->probe_continued) {
1152                 chip->disabled = disabled;
1153                 if (!disabled) {
1154                         dev_info(chip->card->dev,
1155                                  "Start delayed initialization\n");
1156                         if (azx_probe_continue(chip) < 0) {
1157                                 dev_err(chip->card->dev, "initialization error\n");
1158                                 hda->init_failed = true;
1159                         }
1160                 }
1161         } else {
1162                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1163                          disabled ? "Disabling" : "Enabling");
1164                 if (disabled) {
1165                         list_for_each_codec(codec, &chip->bus) {
1166                                 pm_runtime_suspend(hda_codec_dev(codec));
1167                                 pm_runtime_disable(hda_codec_dev(codec));
1168                         }
1169                         pm_runtime_suspend(card->dev);
1170                         pm_runtime_disable(card->dev);
1171                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1172                          * however we have no ACPI handle, so pci/acpi can't put us there,
1173                          * put ourselves there */
1174                         pci->current_state = PCI_D3cold;
1175                         chip->disabled = true;
1176                         if (snd_hda_lock_devices(&chip->bus))
1177                                 dev_warn(chip->card->dev,
1178                                          "Cannot lock devices!\n");
1179                 } else {
1180                         snd_hda_unlock_devices(&chip->bus);
1181                         chip->disabled = false;
1182                         pm_runtime_enable(card->dev);
1183                         list_for_each_codec(codec, &chip->bus) {
1184                                 pm_runtime_enable(hda_codec_dev(codec));
1185                                 pm_runtime_resume(hda_codec_dev(codec));
1186                         }
1187                 }
1188         }
1189 }
1190
1191 static bool azx_vs_can_switch(struct pci_dev *pci)
1192 {
1193         struct snd_card *card = pci_get_drvdata(pci);
1194         struct azx *chip = card->private_data;
1195         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1196
1197         wait_for_completion(&hda->probe_wait);
1198         if (hda->init_failed)
1199                 return false;
1200         if (chip->disabled || !hda->probe_continued)
1201                 return true;
1202         if (snd_hda_lock_devices(&chip->bus))
1203                 return false;
1204         snd_hda_unlock_devices(&chip->bus);
1205         return true;
1206 }
1207
1208 /*
1209  * The discrete GPU cannot power down unless the HDA controller runtime
1210  * suspends, so activate runtime PM on codecs even if power_save == 0.
1211  */
1212 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1213 {
1214         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1215         struct hda_codec *codec;
1216
1217         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1218                 list_for_each_codec(codec, &chip->bus)
1219                         codec->auto_runtime_pm = 1;
1220                 /* reset the power save setup */
1221                 if (chip->running)
1222                         set_default_power_save(chip);
1223         }
1224 }
1225
1226 static void azx_vs_gpu_bound(struct pci_dev *pci,
1227                              enum vga_switcheroo_client_id client_id)
1228 {
1229         struct snd_card *card = pci_get_drvdata(pci);
1230         struct azx *chip = card->private_data;
1231         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1232
1233         if (client_id == VGA_SWITCHEROO_DIS)
1234                 hda->need_eld_notify_link = 0;
1235         setup_vga_switcheroo_runtime_pm(chip);
1236 }
1237
1238 static void init_vga_switcheroo(struct azx *chip)
1239 {
1240         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1241         struct pci_dev *p = get_bound_vga(chip->pci);
1242         if (p) {
1243                 dev_info(chip->card->dev,
1244                          "Handle vga_switcheroo audio client\n");
1245                 hda->use_vga_switcheroo = 1;
1246                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1247                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1248                 pci_dev_put(p);
1249         }
1250 }
1251
1252 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1253         .set_gpu_state = azx_vs_set_state,
1254         .can_switch = azx_vs_can_switch,
1255         .gpu_bound = azx_vs_gpu_bound,
1256 };
1257
1258 static int register_vga_switcheroo(struct azx *chip)
1259 {
1260         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1261         struct pci_dev *p;
1262         int err;
1263
1264         if (!hda->use_vga_switcheroo)
1265                 return 0;
1266
1267         p = get_bound_vga(chip->pci);
1268         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1269         pci_dev_put(p);
1270
1271         if (err < 0)
1272                 return err;
1273         hda->vga_switcheroo_registered = 1;
1274
1275         return 0;
1276 }
1277 #else
1278 #define init_vga_switcheroo(chip)               /* NOP */
1279 #define register_vga_switcheroo(chip)           0
1280 #define check_hdmi_disabled(pci)        false
1281 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1282 #endif /* SUPPORT_VGA_SWITCHER */
1283
1284 /*
1285  * destructor
1286  */
1287 static int azx_free(struct azx *chip)
1288 {
1289         struct pci_dev *pci = chip->pci;
1290         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1291         struct hdac_bus *bus = azx_bus(chip);
1292
1293         if (azx_has_pm_runtime(chip) && chip->running)
1294                 pm_runtime_get_noresume(&pci->dev);
1295         chip->running = 0;
1296
1297         azx_del_card_list(chip);
1298
1299         hda->init_failed = 1; /* to be sure */
1300         complete_all(&hda->probe_wait);
1301
1302         if (use_vga_switcheroo(hda)) {
1303                 if (chip->disabled && hda->probe_continued)
1304                         snd_hda_unlock_devices(&chip->bus);
1305                 if (hda->vga_switcheroo_registered)
1306                         vga_switcheroo_unregister_client(chip->pci);
1307         }
1308
1309         if (bus->chip_init) {
1310                 azx_stop_chip(chip);
1311                 azx_clear_irq_pending(chip);
1312                 azx_stop_all_streams(chip);
1313         }
1314
1315         if (bus->irq >= 0)
1316                 free_irq(bus->irq, (void*)chip);
1317         if (chip->msi)
1318                 pci_disable_msi(chip->pci);
1319         iounmap(bus->remap_addr);
1320
1321         azx_free_stream_pages(chip);
1322         azx_free_streams(chip);
1323         snd_hdac_bus_exit(bus);
1324
1325         if (chip->region_requested)
1326                 pci_release_regions(chip->pci);
1327
1328         pci_disable_device(chip->pci);
1329 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1330         release_firmware(chip->fw);
1331 #endif
1332         display_power(chip, false);
1333
1334         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1335                 snd_hdac_i915_exit(bus);
1336         kfree(hda);
1337
1338         return 0;
1339 }
1340
1341 static int azx_dev_disconnect(struct snd_device *device)
1342 {
1343         struct azx *chip = device->device_data;
1344
1345         chip->bus.shutdown = 1;
1346         return 0;
1347 }
1348
1349 static int azx_dev_free(struct snd_device *device)
1350 {
1351         return azx_free(device->device_data);
1352 }
1353
1354 #ifdef SUPPORT_VGA_SWITCHEROO
1355 /*
1356  * Check of disabled HDMI controller by vga_switcheroo
1357  */
1358 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1359 {
1360         struct pci_dev *p;
1361
1362         /* check only discrete GPU */
1363         switch (pci->vendor) {
1364         case PCI_VENDOR_ID_ATI:
1365         case PCI_VENDOR_ID_AMD:
1366         case PCI_VENDOR_ID_NVIDIA:
1367                 if (pci->devfn == 1) {
1368                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1369                                                         pci->bus->number, 0);
1370                         if (p) {
1371                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1372                                         return p;
1373                                 pci_dev_put(p);
1374                         }
1375                 }
1376                 break;
1377         }
1378         return NULL;
1379 }
1380
1381 static bool check_hdmi_disabled(struct pci_dev *pci)
1382 {
1383         bool vga_inactive = false;
1384         struct pci_dev *p = get_bound_vga(pci);
1385
1386         if (p) {
1387                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1388                         vga_inactive = true;
1389                 pci_dev_put(p);
1390         }
1391         return vga_inactive;
1392 }
1393 #endif /* SUPPORT_VGA_SWITCHEROO */
1394
1395 /*
1396  * white/black-listing for position_fix
1397  */
1398 static struct snd_pci_quirk position_fix_list[] = {
1399         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1400         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1401         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1402         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1403         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1404         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1405         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1406         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1407         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1408         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1409         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1410         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1411         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1412         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1413         {}
1414 };
1415
1416 static int check_position_fix(struct azx *chip, int fix)
1417 {
1418         const struct snd_pci_quirk *q;
1419
1420         switch (fix) {
1421         case POS_FIX_AUTO:
1422         case POS_FIX_LPIB:
1423         case POS_FIX_POSBUF:
1424         case POS_FIX_VIACOMBO:
1425         case POS_FIX_COMBO:
1426         case POS_FIX_SKL:
1427                 return fix;
1428         }
1429
1430         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1431         if (q) {
1432                 dev_info(chip->card->dev,
1433                          "position_fix set to %d for device %04x:%04x\n",
1434                          q->value, q->subvendor, q->subdevice);
1435                 return q->value;
1436         }
1437
1438         /* Check VIA/ATI HD Audio Controller exist */
1439         if (chip->driver_type == AZX_DRIVER_VIA) {
1440                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1441                 return POS_FIX_VIACOMBO;
1442         }
1443         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1444                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1445                 return POS_FIX_LPIB;
1446         }
1447         if (chip->driver_type == AZX_DRIVER_SKL) {
1448                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1449                 return POS_FIX_SKL;
1450         }
1451         return POS_FIX_AUTO;
1452 }
1453
1454 static void assign_position_fix(struct azx *chip, int fix)
1455 {
1456         static azx_get_pos_callback_t callbacks[] = {
1457                 [POS_FIX_AUTO] = NULL,
1458                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1459                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1460                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1461                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1462                 [POS_FIX_SKL] = azx_get_pos_skl,
1463         };
1464
1465         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1466
1467         /* combo mode uses LPIB only for playback */
1468         if (fix == POS_FIX_COMBO)
1469                 chip->get_position[1] = NULL;
1470
1471         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1472             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1473                 chip->get_delay[0] = chip->get_delay[1] =
1474                         azx_get_delay_from_lpib;
1475         }
1476
1477 }
1478
1479 /*
1480  * black-lists for probe_mask
1481  */
1482 static struct snd_pci_quirk probe_mask_list[] = {
1483         /* Thinkpad often breaks the controller communication when accessing
1484          * to the non-working (or non-existing) modem codec slot.
1485          */
1486         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1487         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1488         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1489         /* broken BIOS */
1490         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1491         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1492         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1493         /* forced codec slots */
1494         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1495         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1496         /* WinFast VP200 H (Teradici) user reported broken communication */
1497         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1498         {}
1499 };
1500
1501 #define AZX_FORCE_CODEC_MASK    0x100
1502
1503 static void check_probe_mask(struct azx *chip, int dev)
1504 {
1505         const struct snd_pci_quirk *q;
1506
1507         chip->codec_probe_mask = probe_mask[dev];
1508         if (chip->codec_probe_mask == -1) {
1509                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1510                 if (q) {
1511                         dev_info(chip->card->dev,
1512                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1513                                  q->value, q->subvendor, q->subdevice);
1514                         chip->codec_probe_mask = q->value;
1515                 }
1516         }
1517
1518         /* check forced option */
1519         if (chip->codec_probe_mask != -1 &&
1520             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1521                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1522                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1523                          (int)azx_bus(chip)->codec_mask);
1524         }
1525 }
1526
1527 /*
1528  * white/black-list for enable_msi
1529  */
1530 static struct snd_pci_quirk msi_black_list[] = {
1531         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1532         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1533         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1534         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1535         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1536         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1537         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1538         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1539         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1540         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1541         {}
1542 };
1543
1544 static void check_msi(struct azx *chip)
1545 {
1546         const struct snd_pci_quirk *q;
1547
1548         if (enable_msi >= 0) {
1549                 chip->msi = !!enable_msi;
1550                 return;
1551         }
1552         chip->msi = 1;  /* enable MSI as default */
1553         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1554         if (q) {
1555                 dev_info(chip->card->dev,
1556                          "msi for device %04x:%04x set to %d\n",
1557                          q->subvendor, q->subdevice, q->value);
1558                 chip->msi = q->value;
1559                 return;
1560         }
1561
1562         /* NVidia chipsets seem to cause troubles with MSI */
1563         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1564                 dev_info(chip->card->dev, "Disabling MSI\n");
1565                 chip->msi = 0;
1566         }
1567 }
1568
1569 /* check the snoop mode availability */
1570 static void azx_check_snoop_available(struct azx *chip)
1571 {
1572         int snoop = hda_snoop;
1573
1574         if (snoop >= 0) {
1575                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1576                          snoop ? "snoop" : "non-snoop");
1577                 chip->snoop = snoop;
1578                 chip->uc_buffer = !snoop;
1579                 return;
1580         }
1581
1582         snoop = true;
1583         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1584             chip->driver_type == AZX_DRIVER_VIA) {
1585                 /* force to non-snoop mode for a new VIA controller
1586                  * when BIOS is set
1587                  */
1588                 u8 val;
1589                 pci_read_config_byte(chip->pci, 0x42, &val);
1590                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1591                                       chip->pci->revision == 0x20))
1592                         snoop = false;
1593         }
1594
1595         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1596                 snoop = false;
1597
1598         chip->snoop = snoop;
1599         if (!snoop) {
1600                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1601                 /* C-Media requires non-cached pages only for CORB/RIRB */
1602                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1603                         chip->uc_buffer = true;
1604         }
1605 }
1606
1607 static void azx_probe_work(struct work_struct *work)
1608 {
1609         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1610         azx_probe_continue(&hda->chip);
1611 }
1612
1613 static int default_bdl_pos_adj(struct azx *chip)
1614 {
1615         /* some exceptions: Atoms seem problematic with value 1 */
1616         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1617                 switch (chip->pci->device) {
1618                 case 0x0f04: /* Baytrail */
1619                 case 0x2284: /* Braswell */
1620                         return 32;
1621                 }
1622         }
1623
1624         switch (chip->driver_type) {
1625         case AZX_DRIVER_ICH:
1626         case AZX_DRIVER_PCH:
1627                 return 1;
1628         default:
1629                 return 32;
1630         }
1631 }
1632
1633 /*
1634  * constructor
1635  */
1636 static const struct hdac_io_ops pci_hda_io_ops;
1637 static const struct hda_controller_ops pci_hda_ops;
1638
1639 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1640                       int dev, unsigned int driver_caps,
1641                       struct azx **rchip)
1642 {
1643         static struct snd_device_ops ops = {
1644                 .dev_disconnect = azx_dev_disconnect,
1645                 .dev_free = azx_dev_free,
1646         };
1647         struct hda_intel *hda;
1648         struct azx *chip;
1649         int err;
1650
1651         *rchip = NULL;
1652
1653         err = pci_enable_device(pci);
1654         if (err < 0)
1655                 return err;
1656
1657         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1658         if (!hda) {
1659                 pci_disable_device(pci);
1660                 return -ENOMEM;
1661         }
1662
1663         chip = &hda->chip;
1664         mutex_init(&chip->open_mutex);
1665         chip->card = card;
1666         chip->pci = pci;
1667         chip->ops = &pci_hda_ops;
1668         chip->driver_caps = driver_caps;
1669         chip->driver_type = driver_caps & 0xff;
1670         check_msi(chip);
1671         chip->dev_index = dev;
1672         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1673                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1674         INIT_LIST_HEAD(&chip->pcm_list);
1675         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1676         INIT_LIST_HEAD(&hda->list);
1677         init_vga_switcheroo(chip);
1678         init_completion(&hda->probe_wait);
1679
1680         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1681
1682         check_probe_mask(chip, dev);
1683
1684         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1685                 chip->fallback_to_single_cmd = 1;
1686         else /* explicitly set to single_cmd or not */
1687                 chip->single_cmd = single_cmd;
1688
1689         azx_check_snoop_available(chip);
1690
1691         if (bdl_pos_adj[dev] < 0)
1692                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1693         else
1694                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1695
1696         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1697         if (err < 0) {
1698                 kfree(hda);
1699                 pci_disable_device(pci);
1700                 return err;
1701         }
1702
1703         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1704         if (IS_CFL(pci) || IS_CNL(pci))
1705                 azx_bus(chip)->polling_mode = 1;
1706
1707         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1708                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1709                 chip->bus.needs_damn_long_delay = 1;
1710         }
1711
1712         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1713         if (err < 0) {
1714                 dev_err(card->dev, "Error creating device [card]!\n");
1715                 azx_free(chip);
1716                 return err;
1717         }
1718
1719         /* continue probing in work context as may trigger request module */
1720         INIT_WORK(&hda->probe_work, azx_probe_work);
1721
1722         *rchip = chip;
1723
1724         return 0;
1725 }
1726
1727 static int azx_first_init(struct azx *chip)
1728 {
1729         int dev = chip->dev_index;
1730         struct pci_dev *pci = chip->pci;
1731         struct snd_card *card = chip->card;
1732         struct hdac_bus *bus = azx_bus(chip);
1733         int err;
1734         unsigned short gcap;
1735         unsigned int dma_bits = 64;
1736
1737 #if BITS_PER_LONG != 64
1738         /* Fix up base address on ULI M5461 */
1739         if (chip->driver_type == AZX_DRIVER_ULI) {
1740                 u16 tmp3;
1741                 pci_read_config_word(pci, 0x40, &tmp3);
1742                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1743                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1744         }
1745 #endif
1746
1747         err = pci_request_regions(pci, "ICH HD audio");
1748         if (err < 0)
1749                 return err;
1750         chip->region_requested = 1;
1751
1752         bus->addr = pci_resource_start(pci, 0);
1753         bus->remap_addr = pci_ioremap_bar(pci, 0);
1754         if (bus->remap_addr == NULL) {
1755                 dev_err(card->dev, "ioremap error\n");
1756                 return -ENXIO;
1757         }
1758
1759         if (chip->driver_type == AZX_DRIVER_SKL)
1760                 snd_hdac_bus_parse_capabilities(bus);
1761
1762         /*
1763          * Some Intel CPUs has always running timer (ART) feature and
1764          * controller may have Global time sync reporting capability, so
1765          * check both of these before declaring synchronized time reporting
1766          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1767          */
1768         chip->gts_present = false;
1769
1770 #ifdef CONFIG_X86
1771         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1772                 chip->gts_present = true;
1773 #endif
1774
1775         if (chip->msi) {
1776                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1777                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1778                         pci->no_64bit_msi = true;
1779                 }
1780                 if (pci_enable_msi(pci) < 0)
1781                         chip->msi = 0;
1782         }
1783
1784         pci_set_master(pci);
1785         synchronize_irq(bus->irq);
1786
1787         gcap = azx_readw(chip, GCAP);
1788         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1789
1790         /* AMD devices support 40 or 48bit DMA, take the safe one */
1791         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1792                 dma_bits = 40;
1793
1794         /* disable SB600 64bit support for safety */
1795         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1796                 struct pci_dev *p_smbus;
1797                 dma_bits = 40;
1798                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1799                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1800                                          NULL);
1801                 if (p_smbus) {
1802                         if (p_smbus->revision < 0x30)
1803                                 gcap &= ~AZX_GCAP_64OK;
1804                         pci_dev_put(p_smbus);
1805                 }
1806         }
1807
1808         /* NVidia hardware normally only supports up to 40 bits of DMA */
1809         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1810                 dma_bits = 40;
1811
1812         /* disable 64bit DMA address on some devices */
1813         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1814                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1815                 gcap &= ~AZX_GCAP_64OK;
1816         }
1817
1818         /* disable buffer size rounding to 128-byte multiples if supported */
1819         if (align_buffer_size >= 0)
1820                 chip->align_buffer_size = !!align_buffer_size;
1821         else {
1822                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1823                         chip->align_buffer_size = 0;
1824                 else
1825                         chip->align_buffer_size = 1;
1826         }
1827
1828         /* allow 64bit DMA address if supported by H/W */
1829         if (!(gcap & AZX_GCAP_64OK))
1830                 dma_bits = 32;
1831         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1832                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1833         } else {
1834                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1835                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1836         }
1837
1838         /* read number of streams from GCAP register instead of using
1839          * hardcoded value
1840          */
1841         chip->capture_streams = (gcap >> 8) & 0x0f;
1842         chip->playback_streams = (gcap >> 12) & 0x0f;
1843         if (!chip->playback_streams && !chip->capture_streams) {
1844                 /* gcap didn't give any info, switching to old method */
1845
1846                 switch (chip->driver_type) {
1847                 case AZX_DRIVER_ULI:
1848                         chip->playback_streams = ULI_NUM_PLAYBACK;
1849                         chip->capture_streams = ULI_NUM_CAPTURE;
1850                         break;
1851                 case AZX_DRIVER_ATIHDMI:
1852                 case AZX_DRIVER_ATIHDMI_NS:
1853                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1854                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1855                         break;
1856                 case AZX_DRIVER_GENERIC:
1857                 default:
1858                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1859                         chip->capture_streams = ICH6_NUM_CAPTURE;
1860                         break;
1861                 }
1862         }
1863         chip->capture_index_offset = 0;
1864         chip->playback_index_offset = chip->capture_streams;
1865         chip->num_streams = chip->playback_streams + chip->capture_streams;
1866
1867         /* sanity check for the SDxCTL.STRM field overflow */
1868         if (chip->num_streams > 15 &&
1869             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1870                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1871                          "forcing separate stream tags", chip->num_streams);
1872                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1873         }
1874
1875         /* initialize streams */
1876         err = azx_init_streams(chip);
1877         if (err < 0)
1878                 return err;
1879
1880         err = azx_alloc_stream_pages(chip);
1881         if (err < 0)
1882                 return err;
1883
1884         /* initialize chip */
1885         azx_init_pci(chip);
1886
1887         snd_hdac_i915_set_bclk(bus);
1888
1889         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1890
1891         /* codec detection */
1892         if (!azx_bus(chip)->codec_mask) {
1893                 dev_err(card->dev, "no codecs found!\n");
1894                 return -ENODEV;
1895         }
1896
1897         if (azx_acquire_irq(chip, 0) < 0)
1898                 return -EBUSY;
1899
1900         strcpy(card->driver, "HDA-Intel");
1901         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1902                 sizeof(card->shortname));
1903         snprintf(card->longname, sizeof(card->longname),
1904                  "%s at 0x%lx irq %i",
1905                  card->shortname, bus->addr, bus->irq);
1906
1907         return 0;
1908 }
1909
1910 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1911 /* callback from request_firmware_nowait() */
1912 static void azx_firmware_cb(const struct firmware *fw, void *context)
1913 {
1914         struct snd_card *card = context;
1915         struct azx *chip = card->private_data;
1916         struct pci_dev *pci = chip->pci;
1917
1918         if (!fw) {
1919                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1920                 goto error;
1921         }
1922
1923         chip->fw = fw;
1924         if (!chip->disabled) {
1925                 /* continue probing */
1926                 if (azx_probe_continue(chip))
1927                         goto error;
1928         }
1929         return; /* OK */
1930
1931  error:
1932         snd_card_free(card);
1933         pci_set_drvdata(pci, NULL);
1934 }
1935 #endif
1936
1937 /*
1938  * HDA controller ops.
1939  */
1940
1941 /* PCI register access. */
1942 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1943 {
1944         writel(value, addr);
1945 }
1946
1947 static u32 pci_azx_readl(u32 __iomem *addr)
1948 {
1949         return readl(addr);
1950 }
1951
1952 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1953 {
1954         writew(value, addr);
1955 }
1956
1957 static u16 pci_azx_readw(u16 __iomem *addr)
1958 {
1959         return readw(addr);
1960 }
1961
1962 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1963 {
1964         writeb(value, addr);
1965 }
1966
1967 static u8 pci_azx_readb(u8 __iomem *addr)
1968 {
1969         return readb(addr);
1970 }
1971
1972 static int disable_msi_reset_irq(struct azx *chip)
1973 {
1974         struct hdac_bus *bus = azx_bus(chip);
1975         int err;
1976
1977         free_irq(bus->irq, chip);
1978         bus->irq = -1;
1979         pci_disable_msi(chip->pci);
1980         chip->msi = 0;
1981         err = azx_acquire_irq(chip, 1);
1982         if (err < 0)
1983                 return err;
1984
1985         return 0;
1986 }
1987
1988 /* DMA page allocation helpers.  */
1989 static int dma_alloc_pages(struct hdac_bus *bus,
1990                            int type,
1991                            size_t size,
1992                            struct snd_dma_buffer *buf)
1993 {
1994         struct azx *chip = bus_to_azx(bus);
1995
1996         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
1997                 type = SNDRV_DMA_TYPE_DEV_UC;
1998         return snd_dma_alloc_pages(type, bus->dev, size, buf);
1999 }
2000
2001 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2002 {
2003         snd_dma_free_pages(buf);
2004 }
2005
2006 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2007                              struct vm_area_struct *area)
2008 {
2009 #ifdef CONFIG_X86
2010         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2011         struct azx *chip = apcm->chip;
2012         if (chip->uc_buffer)
2013                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2014 #endif
2015 }
2016
2017 static const struct hdac_io_ops pci_hda_io_ops = {
2018         .reg_writel = pci_azx_writel,
2019         .reg_readl = pci_azx_readl,
2020         .reg_writew = pci_azx_writew,
2021         .reg_readw = pci_azx_readw,
2022         .reg_writeb = pci_azx_writeb,
2023         .reg_readb = pci_azx_readb,
2024         .dma_alloc_pages = dma_alloc_pages,
2025         .dma_free_pages = dma_free_pages,
2026 };
2027
2028 static const struct hda_controller_ops pci_hda_ops = {
2029         .disable_msi_reset_irq = disable_msi_reset_irq,
2030         .pcm_mmap_prepare = pcm_mmap_prepare,
2031         .position_check = azx_position_check,
2032 };
2033
2034 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2035 {
2036         struct nhlt_acpi_table *nhlt;
2037         int ret = 0;
2038
2039         if (chip->driver_type == AZX_DRIVER_SKL &&
2040             pci->class != 0x040300) {
2041                 nhlt = intel_nhlt_init(&pci->dev);
2042                 if (nhlt) {
2043                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2044                                 ret = -ENODEV;
2045                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2046                         }
2047                         intel_nhlt_free(nhlt);
2048                 }
2049         }
2050         return ret;
2051 }
2052
2053 static int azx_probe(struct pci_dev *pci,
2054                      const struct pci_device_id *pci_id)
2055 {
2056         static int dev;
2057         struct snd_card *card;
2058         struct hda_intel *hda;
2059         struct azx *chip;
2060         bool schedule_probe;
2061         int err;
2062
2063         if (dev >= SNDRV_CARDS)
2064                 return -ENODEV;
2065         if (!enable[dev]) {
2066                 dev++;
2067                 return -ENOENT;
2068         }
2069
2070         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2071                            0, &card);
2072         if (err < 0) {
2073                 dev_err(&pci->dev, "Error creating card!\n");
2074                 return err;
2075         }
2076
2077         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2078         if (err < 0)
2079                 goto out_free;
2080         card->private_data = chip;
2081         hda = container_of(chip, struct hda_intel, chip);
2082
2083         /*
2084          * stop probe if digital microphones detected on Skylake+ platform
2085          * with the DSP enabled. This is an opt-in behavior defined at build
2086          * time or at run-time with a module parameter
2087          */
2088         if (dmic_detect) {
2089                 err = azx_check_dmic(pci, chip);
2090                 if (err < 0)
2091                         goto out_free;
2092         }
2093
2094         pci_set_drvdata(pci, card);
2095
2096         err = register_vga_switcheroo(chip);
2097         if (err < 0) {
2098                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2099                 goto out_free;
2100         }
2101
2102         if (check_hdmi_disabled(pci)) {
2103                 dev_info(card->dev, "VGA controller is disabled\n");
2104                 dev_info(card->dev, "Delaying initialization\n");
2105                 chip->disabled = true;
2106         }
2107
2108         schedule_probe = !chip->disabled;
2109
2110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2111         if (patch[dev] && *patch[dev]) {
2112                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2113                          patch[dev]);
2114                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2115                                               &pci->dev, GFP_KERNEL, card,
2116                                               azx_firmware_cb);
2117                 if (err < 0)
2118                         goto out_free;
2119                 schedule_probe = false; /* continued in azx_firmware_cb() */
2120         }
2121 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2122
2123 #ifndef CONFIG_SND_HDA_I915
2124         if (CONTROLLER_IN_GPU(pci))
2125                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2126 #endif
2127
2128         if (schedule_probe)
2129                 schedule_work(&hda->probe_work);
2130
2131         dev++;
2132         if (chip->disabled)
2133                 complete_all(&hda->probe_wait);
2134         return 0;
2135
2136 out_free:
2137         snd_card_free(card);
2138         return err;
2139 }
2140
2141 #ifdef CONFIG_PM
2142 /* On some boards setting power_save to a non 0 value leads to clicking /
2143  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2144  * figure out how to avoid these sounds, but that is not always feasible.
2145  * So we keep a list of devices where we disable powersaving as its known
2146  * to causes problems on these devices.
2147  */
2148 static struct snd_pci_quirk power_save_blacklist[] = {
2149         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2150         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2151         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2152         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2155         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2156         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2157         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2158         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2159         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2160         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2161         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2162         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2163         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2164         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2165         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2166         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2167         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2168         /* https://bugs.launchpad.net/bugs/1821663 */
2169         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2170         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2171         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2172         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2173         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2174         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2175         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2176         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2177         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2178         /* https://bugs.launchpad.net/bugs/1821663 */
2179         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2180         {}
2181 };
2182 #endif /* CONFIG_PM */
2183
2184 static void set_default_power_save(struct azx *chip)
2185 {
2186         int val = power_save;
2187
2188 #ifdef CONFIG_PM
2189         if (pm_blacklist) {
2190                 const struct snd_pci_quirk *q;
2191
2192                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2193                 if (q && val) {
2194                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2195                                  q->subvendor, q->subdevice);
2196                         val = 0;
2197                 }
2198         }
2199 #endif /* CONFIG_PM */
2200         snd_hda_set_power_save(&chip->bus, val * 1000);
2201 }
2202
2203 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2204 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2205         [AZX_DRIVER_NVIDIA] = 8,
2206         [AZX_DRIVER_TERA] = 1,
2207 };
2208
2209 static int azx_probe_continue(struct azx *chip)
2210 {
2211         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2212         struct hdac_bus *bus = azx_bus(chip);
2213         struct pci_dev *pci = chip->pci;
2214         int dev = chip->dev_index;
2215         int err;
2216
2217         to_hda_bus(bus)->bus_probing = 1;
2218         hda->probe_continued = 1;
2219
2220         /* bind with i915 if needed */
2221         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2222                 err = snd_hdac_i915_init(bus);
2223                 if (err < 0) {
2224                         /* if the controller is bound only with HDMI/DP
2225                          * (for HSW and BDW), we need to abort the probe;
2226                          * for other chips, still continue probing as other
2227                          * codecs can be on the same link.
2228                          */
2229                         if (CONTROLLER_IN_GPU(pci)) {
2230                                 dev_err(chip->card->dev,
2231                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2232                                 goto out_free;
2233                         } else {
2234                                 /* don't bother any longer */
2235                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2236                         }
2237                 }
2238
2239                 /* HSW/BDW controllers need this power */
2240                 if (CONTROLLER_IN_GPU(pci))
2241                         hda->need_i915_power = 1;
2242         }
2243
2244         /* Request display power well for the HDA controller or codec. For
2245          * Haswell/Broadwell, both the display HDA controller and codec need
2246          * this power. For other platforms, like Baytrail/Braswell, only the
2247          * display codec needs the power and it can be released after probe.
2248          */
2249         display_power(chip, true);
2250
2251         err = azx_first_init(chip);
2252         if (err < 0)
2253                 goto out_free;
2254
2255 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2256         chip->beep_mode = beep_mode[dev];
2257 #endif
2258
2259         /* create codec instances */
2260         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2261         if (err < 0)
2262                 goto out_free;
2263
2264 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2265         if (chip->fw) {
2266                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2267                                          chip->fw->data);
2268                 if (err < 0)
2269                         goto out_free;
2270 #ifndef CONFIG_PM
2271                 release_firmware(chip->fw); /* no longer needed */
2272                 chip->fw = NULL;
2273 #endif
2274         }
2275 #endif
2276         if ((probe_only[dev] & 1) == 0) {
2277                 err = azx_codec_configure(chip);
2278                 if (err < 0)
2279                         goto out_free;
2280         }
2281
2282         err = snd_card_register(chip->card);
2283         if (err < 0)
2284                 goto out_free;
2285
2286         setup_vga_switcheroo_runtime_pm(chip);
2287
2288         chip->running = 1;
2289         azx_add_card_list(chip);
2290
2291         set_default_power_save(chip);
2292
2293         if (azx_has_pm_runtime(chip))
2294                 pm_runtime_put_autosuspend(&pci->dev);
2295
2296 out_free:
2297         if (err < 0 || !hda->need_i915_power)
2298                 display_power(chip, false);
2299         if (err < 0)
2300                 hda->init_failed = 1;
2301         complete_all(&hda->probe_wait);
2302         to_hda_bus(bus)->bus_probing = 0;
2303         return err;
2304 }
2305
2306 static void azx_remove(struct pci_dev *pci)
2307 {
2308         struct snd_card *card = pci_get_drvdata(pci);
2309         struct azx *chip;
2310         struct hda_intel *hda;
2311
2312         if (card) {
2313                 /* cancel the pending probing work */
2314                 chip = card->private_data;
2315                 hda = container_of(chip, struct hda_intel, chip);
2316                 /* FIXME: below is an ugly workaround.
2317                  * Both device_release_driver() and driver_probe_device()
2318                  * take *both* the device's and its parent's lock before
2319                  * calling the remove() and probe() callbacks.  The codec
2320                  * probe takes the locks of both the codec itself and its
2321                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2322                  * the PCI controller is unbound, it takes its lock, too
2323                  * ==> ouch, a deadlock!
2324                  * As a workaround, we unlock temporarily here the controller
2325                  * device during cancel_work_sync() call.
2326                  */
2327                 device_unlock(&pci->dev);
2328                 cancel_work_sync(&hda->probe_work);
2329                 device_lock(&pci->dev);
2330
2331                 snd_card_free(card);
2332         }
2333 }
2334
2335 static void azx_shutdown(struct pci_dev *pci)
2336 {
2337         struct snd_card *card = pci_get_drvdata(pci);
2338         struct azx *chip;
2339
2340         if (!card)
2341                 return;
2342         chip = card->private_data;
2343         if (chip && chip->running)
2344                 azx_stop_chip(chip);
2345 }
2346
2347 /* PCI IDs */
2348 static const struct pci_device_id azx_ids[] = {
2349         /* CPT */
2350         { PCI_DEVICE(0x8086, 0x1c20),
2351           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2352         /* PBG */
2353         { PCI_DEVICE(0x8086, 0x1d20),
2354           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2355         /* Panther Point */
2356         { PCI_DEVICE(0x8086, 0x1e20),
2357           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2358         /* Lynx Point */
2359         { PCI_DEVICE(0x8086, 0x8c20),
2360           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2361         /* 9 Series */
2362         { PCI_DEVICE(0x8086, 0x8ca0),
2363           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2364         /* Wellsburg */
2365         { PCI_DEVICE(0x8086, 0x8d20),
2366           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2367         { PCI_DEVICE(0x8086, 0x8d21),
2368           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2369         /* Lewisburg */
2370         { PCI_DEVICE(0x8086, 0xa1f0),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2372         { PCI_DEVICE(0x8086, 0xa270),
2373           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2374         /* Lynx Point-LP */
2375         { PCI_DEVICE(0x8086, 0x9c20),
2376           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2377         /* Lynx Point-LP */
2378         { PCI_DEVICE(0x8086, 0x9c21),
2379           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2380         /* Wildcat Point-LP */
2381         { PCI_DEVICE(0x8086, 0x9ca0),
2382           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2383         /* Sunrise Point */
2384         { PCI_DEVICE(0x8086, 0xa170),
2385           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2386         /* Sunrise Point-LP */
2387         { PCI_DEVICE(0x8086, 0x9d70),
2388           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2389         /* Kabylake */
2390         { PCI_DEVICE(0x8086, 0xa171),
2391           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2392         /* Kabylake-LP */
2393         { PCI_DEVICE(0x8086, 0x9d71),
2394           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2395         /* Kabylake-H */
2396         { PCI_DEVICE(0x8086, 0xa2f0),
2397           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2398         /* Coffelake */
2399         { PCI_DEVICE(0x8086, 0xa348),
2400           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2401         /* Cannonlake */
2402         { PCI_DEVICE(0x8086, 0x9dc8),
2403           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2404         /* CometLake-LP */
2405         { PCI_DEVICE(0x8086, 0x02C8),
2406           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2407         /* CometLake-H */
2408         { PCI_DEVICE(0x8086, 0x06C8),
2409           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2410         /* Icelake */
2411         { PCI_DEVICE(0x8086, 0x34c8),
2412           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2413         /* Elkhart Lake */
2414         { PCI_DEVICE(0x8086, 0x4b55),
2415           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2416         /* Broxton-P(Apollolake) */
2417         { PCI_DEVICE(0x8086, 0x5a98),
2418           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2419         /* Broxton-T */
2420         { PCI_DEVICE(0x8086, 0x1a98),
2421           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2422         /* Gemini-Lake */
2423         { PCI_DEVICE(0x8086, 0x3198),
2424           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2425         /* Haswell */
2426         { PCI_DEVICE(0x8086, 0x0a0c),
2427           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2428         { PCI_DEVICE(0x8086, 0x0c0c),
2429           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2430         { PCI_DEVICE(0x8086, 0x0d0c),
2431           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2432         /* Broadwell */
2433         { PCI_DEVICE(0x8086, 0x160c),
2434           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2435         /* 5 Series/3400 */
2436         { PCI_DEVICE(0x8086, 0x3b56),
2437           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2438         /* Poulsbo */
2439         { PCI_DEVICE(0x8086, 0x811b),
2440           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2441         /* Oaktrail */
2442         { PCI_DEVICE(0x8086, 0x080a),
2443           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2444         /* BayTrail */
2445         { PCI_DEVICE(0x8086, 0x0f04),
2446           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2447         /* Braswell */
2448         { PCI_DEVICE(0x8086, 0x2284),
2449           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2450         /* ICH6 */
2451         { PCI_DEVICE(0x8086, 0x2668),
2452           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453         /* ICH7 */
2454         { PCI_DEVICE(0x8086, 0x27d8),
2455           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2456         /* ESB2 */
2457         { PCI_DEVICE(0x8086, 0x269a),
2458           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2459         /* ICH8 */
2460         { PCI_DEVICE(0x8086, 0x284b),
2461           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2462         /* ICH9 */
2463         { PCI_DEVICE(0x8086, 0x293e),
2464           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2465         /* ICH9 */
2466         { PCI_DEVICE(0x8086, 0x293f),
2467           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2468         /* ICH10 */
2469         { PCI_DEVICE(0x8086, 0x3a3e),
2470           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2471         /* ICH10 */
2472         { PCI_DEVICE(0x8086, 0x3a6e),
2473           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2474         /* Generic Intel */
2475         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2476           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2477           .class_mask = 0xffffff,
2478           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2479         /* ATI SB 450/600/700/800/900 */
2480         { PCI_DEVICE(0x1002, 0x437b),
2481           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2482         { PCI_DEVICE(0x1002, 0x4383),
2483           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2484         /* AMD Hudson */
2485         { PCI_DEVICE(0x1022, 0x780d),
2486           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2487         /* AMD Stoney */
2488         { PCI_DEVICE(0x1022, 0x157a),
2489           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2490                          AZX_DCAPS_PM_RUNTIME },
2491         /* AMD Raven */
2492         { PCI_DEVICE(0x1022, 0x15e3),
2493           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2494                          AZX_DCAPS_PM_RUNTIME },
2495         /* ATI HDMI */
2496         { PCI_DEVICE(0x1002, 0x0002),
2497           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2498         { PCI_DEVICE(0x1002, 0x1308),
2499           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2500         { PCI_DEVICE(0x1002, 0x157a),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x15b3),
2503           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2504         { PCI_DEVICE(0x1002, 0x793b),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0x7919),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0x960f),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x970f),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0x9840),
2513           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2514         { PCI_DEVICE(0x1002, 0xaa00),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa08),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa10),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa18),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa20),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa28),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa30),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa38),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa40),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa48),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa50),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa58),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa60),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa68),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa80),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa88),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa90),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa98),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0x9902),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaaa0),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaaa8),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaab0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaac0),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaac8),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaad8),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaae8),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaae0),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         { PCI_DEVICE(0x1002, 0xaaf0),
2569           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2570         /* VIA VT8251/VT8237A */
2571         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2572         /* VIA GFX VT7122/VX900 */
2573         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2574         /* VIA GFX VT6122/VX11 */
2575         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2576         /* SIS966 */
2577         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2578         /* ULI M5461 */
2579         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2580         /* NVIDIA MCP */
2581         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2582           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2583           .class_mask = 0xffffff,
2584           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2585         /* Teradici */
2586         { PCI_DEVICE(0x6549, 0x1200),
2587           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2588         { PCI_DEVICE(0x6549, 0x2200),
2589           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2590         /* Creative X-Fi (CA0110-IBG) */
2591         /* CTHDA chips */
2592         { PCI_DEVICE(0x1102, 0x0010),
2593           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2594         { PCI_DEVICE(0x1102, 0x0012),
2595           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2596 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2597         /* the following entry conflicts with snd-ctxfi driver,
2598          * as ctxfi driver mutates from HD-audio to native mode with
2599          * a special command sequence.
2600          */
2601         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2602           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2603           .class_mask = 0xffffff,
2604           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2605           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2606 #else
2607         /* this entry seems still valid -- i.e. without emu20kx chip */
2608         { PCI_DEVICE(0x1102, 0x0009),
2609           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2610           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2611 #endif
2612         /* CM8888 */
2613         { PCI_DEVICE(0x13f6, 0x5011),
2614           .driver_data = AZX_DRIVER_CMEDIA |
2615           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2616         /* Vortex86MX */
2617         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2618         /* VMware HDAudio */
2619         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2620         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2621         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2622           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2623           .class_mask = 0xffffff,
2624           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2626           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2627           .class_mask = 0xffffff,
2628           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2629         /* Zhaoxin */
2630         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2631         { 0, }
2632 };
2633 MODULE_DEVICE_TABLE(pci, azx_ids);
2634
2635 /* pci_driver definition */
2636 static struct pci_driver azx_driver = {
2637         .name = KBUILD_MODNAME,
2638         .id_table = azx_ids,
2639         .probe = azx_probe,
2640         .remove = azx_remove,
2641         .shutdown = azx_shutdown,
2642         .driver = {
2643                 .pm = AZX_PM_OPS,
2644         },
2645 };
2646
2647 module_pci_driver(azx_driver);