sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include <sound/hda_codec.h>
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 static bool pm_blacklist = true;
 190 module_param(pm_blacklist, bool, 0644);
 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 192
 193 /* reset the HD-audio controller in power save mode.
 194  * this may give more power-saving, but will take longer time to
 195  * wake up.
 196  */
 197 static bool power_save_controller = 1;
 198 module_param(power_save_controller, bool, 0644);
 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 200 #else
 201 #define power_save      0
 202 #endif /* CONFIG_PM */
 203
 204 static int align_buffer_size = -1;
 205 module_param(align_buffer_size, bint, 0644);
 206 MODULE_PARM_DESC(align_buffer_size,
 207                 "Force buffer and period sizes to be multiple of 128 bytes.");
 208
 209 #ifdef CONFIG_X86
 210 static int hda_snoop = -1;
 211 module_param_named(snoop, hda_snoop, bint, 0444);
 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 213 #else
 214 #define hda_snoop               true
 215 #endif
 216
 217
 218 MODULE_LICENSE("GPL");
 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 220                          "{Intel, ICH6M},"
 221                          "{Intel, ICH7},"
 222                          "{Intel, ESB2},"
 223                          "{Intel, ICH8},"
 224                          "{Intel, ICH9},"
 225                          "{Intel, ICH10},"
 226                          "{Intel, PCH},"
 227                          "{Intel, CPT},"
 228                          "{Intel, PPT},"
 229                          "{Intel, LPT},"
 230                          "{Intel, LPT_LP},"
 231                          "{Intel, WPT_LP},"
 232                          "{Intel, SPT},"
 233                          "{Intel, SPT_LP},"
 234                          "{Intel, HPT},"
 235                          "{Intel, PBG},"
 236                          "{Intel, SCH},"
 237                          "{ATI, SB450},"
 238                          "{ATI, SB600},"
 239                          "{ATI, RS600},"
 240                          "{ATI, RS690},"
 241                          "{ATI, RS780},"
 242                          "{ATI, R600},"
 243                          "{ATI, RV630},"
 244                          "{ATI, RV610},"
 245                          "{ATI, RV670},"
 246                          "{ATI, RV635},"
 247                          "{ATI, RV620},"
 248                          "{ATI, RV770},"
 249                          "{VIA, VT8251},"
 250                          "{VIA, VT8237A},"
 251                          "{SiS, SIS966},"
 252                          "{ULI, M5461}}");
 253 MODULE_DESCRIPTION("Intel HDA driver");
 254
 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 257 #define SUPPORT_VGA_SWITCHEROO
 258 #endif
 259 #endif
 260
 261
 262 /*
 263  */
 264
 265 /* driver types */
 266 enum {
 267         AZX_DRIVER_ICH,
 268         AZX_DRIVER_PCH,
 269         AZX_DRIVER_SCH,
 270         AZX_DRIVER_SKL,
 271         AZX_DRIVER_HDMI,
 272         AZX_DRIVER_ATI,
 273         AZX_DRIVER_ATIHDMI,
 274         AZX_DRIVER_ATIHDMI_NS,
 275         AZX_DRIVER_VIA,
 276         AZX_DRIVER_SIS,
 277         AZX_DRIVER_ULI,
 278         AZX_DRIVER_NVIDIA,
 279         AZX_DRIVER_TERA,
 280         AZX_DRIVER_CTX,
 281         AZX_DRIVER_CTHDA,
 282         AZX_DRIVER_CMEDIA,
 283         AZX_DRIVER_GENERIC,
 284         AZX_NUM_DRIVERS, /* keep this as last entry */
 285 };
 286
 287 #define azx_get_snoop_type(chip) \
 288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 290
 291 /* quirks for old Intel chipsets */
 292 #define AZX_DCAPS_INTEL_ICH \
 293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 294
 295 /* quirks for Intel PCH */
 296 #define AZX_DCAPS_INTEL_PCH_BASE \
 297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 301 #define AZX_DCAPS_INTEL_PCH_NOPM \
 302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 303
 304 /* PCH for HSW/BDW; with runtime PM */
 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 306 #define AZX_DCAPS_INTEL_PCH \
 307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 308
 309 /* HSW HDMI */
 310 #define AZX_DCAPS_INTEL_HASWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 316 #define AZX_DCAPS_INTEL_BROADWELL \
 317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 319          AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
 320
 321 #define AZX_DCAPS_INTEL_BAYTRAIL \
 322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
 323          AZX_DCAPS_I915_POWERWELL)
 324
 325 #define AZX_DCAPS_INTEL_BRASWELL \
 326         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 327          AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
 328
 329 #define AZX_DCAPS_INTEL_SKYLAKE \
 330         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 331          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 332          AZX_DCAPS_I915_POWERWELL)
 333
 334 #define AZX_DCAPS_INTEL_BROXTON \
 335         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 336          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
 337          AZX_DCAPS_I915_POWERWELL)
 338
 339 /* quirks for ATI SB / AMD Hudson */
 340 #define AZX_DCAPS_PRESET_ATI_SB \
 341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 342          AZX_DCAPS_SNOOP_TYPE(ATI))
 343
 344 /* quirks for ATI/AMD HDMI */
 345 #define AZX_DCAPS_PRESET_ATI_HDMI \
 346         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 347          AZX_DCAPS_NO_MSI64)
 348
 349 /* quirks for ATI HDMI with snoop off */
 350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 351         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 352
 353 /* quirks for Nvidia */
 354 #define AZX_DCAPS_PRESET_NVIDIA \
 355         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 356          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 357
 358 #define AZX_DCAPS_PRESET_CTHDA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 360          AZX_DCAPS_NO_64BIT |\
 361          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 362
 363 /*
 364  * vga_switcheroo support
 365  */
 366 #ifdef SUPPORT_VGA_SWITCHEROO
 367 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 368 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 369 #else
 370 #define use_vga_switcheroo(chip)        0
 371 #define needs_eld_notify_link(chip)     false
 372 #endif
 373
 374 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 375                                         ((pci)->device == 0x0c0c) || \
 376                                         ((pci)->device == 0x0d0c) || \
 377                                         ((pci)->device == 0x160c))
 378
 379 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 380 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 381
 382 static char *driver_short_names[] = {
 383         [AZX_DRIVER_ICH] = "HDA Intel",
 384         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 385         [AZX_DRIVER_SCH] = "HDA Intel MID",
 386         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 387         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 388         [AZX_DRIVER_ATI] = "HDA ATI SB",
 389         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 390         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 391         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 392         [AZX_DRIVER_SIS] = "HDA SIS966",
 393         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 394         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 395         [AZX_DRIVER_TERA] = "HDA Teradici",
 396         [AZX_DRIVER_CTX] = "HDA Creative",
 397         [AZX_DRIVER_CTHDA] = "HDA Creative",
 398         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 399         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 400 };
 401
 402 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 403 static void set_default_power_save(struct azx *chip);
 404
 405 /*
 406  * initialize the PCI registers
 407  */
 408 /* update bits in a PCI register byte */
 409 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 410                             unsigned char mask, unsigned char val)
 411 {
 412         unsigned char data;
 413
 414         pci_read_config_byte(pci, reg, &data);
 415         data &= ~mask;
 416         data |= (val & mask);
 417         pci_write_config_byte(pci, reg, data);
 418 }
 419
 420 static void azx_init_pci(struct azx *chip)
 421 {
 422         int snoop_type = azx_get_snoop_type(chip);
 423
 424         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 425          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 426          * Ensuring these bits are 0 clears playback static on some HD Audio
 427          * codecs.
 428          * The PCI register TCSEL is defined in the Intel manuals.
 429          */
 430         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 431                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 432                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 433         }
 434
 435         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 436          * we need to enable snoop.
 437          */
 438         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 439                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 440                         azx_snoop(chip));
 441                 update_pci_byte(chip->pci,
 442                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 443                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 444         }
 445
 446         /* For NVIDIA HDA, enable snoop */
 447         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 448                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 449                         azx_snoop(chip));
 450                 update_pci_byte(chip->pci,
 451                                 NVIDIA_HDA_TRANSREG_ADDR,
 452                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 453                 update_pci_byte(chip->pci,
 454                                 NVIDIA_HDA_ISTRM_COH,
 455                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 456                 update_pci_byte(chip->pci,
 457                                 NVIDIA_HDA_OSTRM_COH,
 458                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 459         }
 460
 461         /* Enable SCH/PCH snoop if needed */
 462         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 463                 unsigned short snoop;
 464                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 465                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 466                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 467                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 468                         if (!azx_snoop(chip))
 469                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 470                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 471                         pci_read_config_word(chip->pci,
 472                                 INTEL_SCH_HDA_DEVC, &snoop);
 473                 }
 474                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 475                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 476                         "Disabled" : "Enabled");
 477         }
 478 }
 479
 480 /*
 481  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 482  * and makes an audio stream sensitive to system latencies when
 483  * 24/32 bits are playing.
 484  * Adjusting threshold of DMA fifo to force the DMA request
 485  * sooner to improve latency tolerance at the expense of power.
 486  */
 487 static void bxt_reduce_dma_latency(struct azx *chip)
 488 {
 489         u32 val;
 490
 491         val = azx_readl(chip, VS_EM4L);
 492         val &= (0x3 << 20);
 493         azx_writel(chip, VS_EM4L, val);
 494 }
 495
 496 /*
 497  * ML_LCAP bits:
 498  *  bit 0: 6 MHz Supported
 499  *  bit 1: 12 MHz Supported
 500  *  bit 2: 24 MHz Supported
 501  *  bit 3: 48 MHz Supported
 502  *  bit 4: 96 MHz Supported
 503  *  bit 5: 192 MHz Supported
 504  */
 505 static int intel_get_lctl_scf(struct azx *chip)
 506 {
 507         struct hdac_bus *bus = azx_bus(chip);
 508         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 509         u32 val, t;
 510         int i;
 511
 512         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 513
 514         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 515                 t = preferred_bits[i];
 516                 if (val & (1 << t))
 517                         return t;
 518         }
 519
 520         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 521         return 0;
 522 }
 523
 524 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 525 {
 526         struct hdac_bus *bus = azx_bus(chip);
 527         u32 val;
 528         int timeout;
 529
 530         /*
 531          * the codecs are sharing the first link setting by default
 532          * If other links are enabled for stream, they need similar fix
 533          */
 534         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 535         val &= ~AZX_MLCTL_SPA;
 536         val |= state << AZX_MLCTL_SPA_SHIFT;
 537         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 538         /* wait for CPA */
 539         timeout = 50;
 540         while (timeout) {
 541                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 542                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 543                         return 0;
 544                 timeout--;
 545                 udelay(10);
 546         }
 547
 548         return -1;
 549 }
 550
 551 static void intel_init_lctl(struct azx *chip)
 552 {
 553         struct hdac_bus *bus = azx_bus(chip);
 554         u32 val;
 555         int ret;
 556
 557         /* 0. check lctl register value is correct or not */
 558         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 559         /* if SCF is already set, let's use it */
 560         if ((val & ML_LCTL_SCF_MASK) != 0)
 561                 return;
 562
 563         /*
 564          * Before operating on SPA, CPA must match SPA.
 565          * Any deviation may result in undefined behavior.
 566          */
 567         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 568                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 569                 return;
 570
 571         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 572         ret = intel_ml_lctl_set_power(chip, 0);
 573         udelay(100);
 574         if (ret)
 575                 goto set_spa;
 576
 577         /* 2. update SCF to select a properly audio clock*/
 578         val &= ~ML_LCTL_SCF_MASK;
 579         val |= intel_get_lctl_scf(chip);
 580         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 581
 582 set_spa:
 583         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 584         intel_ml_lctl_set_power(chip, 1);
 585         udelay(100);
 586 }
 587
 588 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 589 {
 590         struct hdac_bus *bus = azx_bus(chip);
 591         struct pci_dev *pci = chip->pci;
 592         u32 val;
 593
 594         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 595                 snd_hdac_set_codec_wakeup(bus, true);
 596         if (chip->driver_type == AZX_DRIVER_SKL) {
 597                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 598                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 599                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 600         }
 601         azx_init_chip(chip, full_reset);
 602         if (chip->driver_type == AZX_DRIVER_SKL) {
 603                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 604                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 605                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 606         }
 607         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 608                 snd_hdac_set_codec_wakeup(bus, false);
 609
 610         /* reduce dma latency to avoid noise */
 611         if (IS_BXT(pci))
 612                 bxt_reduce_dma_latency(chip);
 613
 614         if (bus->mlcap != NULL)
 615                 intel_init_lctl(chip);
 616 }
 617
 618 /* calculate runtime delay from LPIB */
 619 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 620                                    unsigned int pos)
 621 {
 622         struct snd_pcm_substream *substream = azx_dev->core.substream;
 623         int stream = substream->stream;
 624         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 625         int delay;
 626
 627         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 628                 delay = pos - lpib_pos;
 629         else
 630                 delay = lpib_pos - pos;
 631         if (delay < 0) {
 632                 if (delay >= azx_dev->core.delay_negative_threshold)
 633                         delay = 0;
 634                 else
 635                         delay += azx_dev->core.bufsize;
 636         }
 637
 638         if (delay >= azx_dev->core.period_bytes) {
 639                 dev_info(chip->card->dev,
 640                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 641                          delay, azx_dev->core.period_bytes);
 642                 delay = 0;
 643                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 644                 chip->get_delay[stream] = NULL;
 645         }
 646
 647         return bytes_to_frames(substream->runtime, delay);
 648 }
 649
 650 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 651
 652 /* called from IRQ */
 653 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 654 {
 655         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 656         int ok;
 657
 658         ok = azx_position_ok(chip, azx_dev);
 659         if (ok == 1) {
 660                 azx_dev->irq_pending = 0;
 661                 return ok;
 662         } else if (ok == 0) {
 663                 /* bogus IRQ, process it later */
 664                 azx_dev->irq_pending = 1;
 665                 schedule_work(&hda->irq_pending_work);
 666         }
 667         return 0;
 668 }
 669
 670 /* Enable/disable i915 display power for the link */
 671 static int azx_intel_link_power(struct azx *chip, bool enable)
 672 {
 673         struct hdac_bus *bus = azx_bus(chip);
 674
 675         return snd_hdac_display_power(bus, enable);
 676 }
 677
 678 /*
 679  * Check whether the current DMA position is acceptable for updating
 680  * periods.  Returns non-zero if it's OK.
 681  *
 682  * Many HD-audio controllers appear pretty inaccurate about
 683  * the update-IRQ timing.  The IRQ is issued before actually the
 684  * data is processed.  So, we need to process it afterwords in a
 685  * workqueue.
 686  */
 687 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 688 {
 689         struct snd_pcm_substream *substream = azx_dev->core.substream;
 690         int stream = substream->stream;
 691         u32 wallclk;
 692         unsigned int pos;
 693
 694         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 695         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 696                 return -1;      /* bogus (too early) interrupt */
 697
 698         if (chip->get_position[stream])
 699                 pos = chip->get_position[stream](chip, azx_dev);
 700         else { /* use the position buffer as default */
 701                 pos = azx_get_pos_posbuf(chip, azx_dev);
 702                 if (!pos || pos == (u32)-1) {
 703                         dev_info(chip->card->dev,
 704                                  "Invalid position buffer, using LPIB read method instead.\n");
 705                         chip->get_position[stream] = azx_get_pos_lpib;
 706                         if (chip->get_position[0] == azx_get_pos_lpib &&
 707                             chip->get_position[1] == azx_get_pos_lpib)
 708                                 azx_bus(chip)->use_posbuf = false;
 709                         pos = azx_get_pos_lpib(chip, azx_dev);
 710                         chip->get_delay[stream] = NULL;
 711                 } else {
 712                         chip->get_position[stream] = azx_get_pos_posbuf;
 713                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 714                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 715                 }
 716         }
 717
 718         if (pos >= azx_dev->core.bufsize)
 719                 pos = 0;
 720
 721         if (WARN_ONCE(!azx_dev->core.period_bytes,
 722                       "hda-intel: zero azx_dev->period_bytes"))
 723                 return -1; /* this shouldn't happen! */
 724         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 725             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 726                 /* NG - it's below the first next period boundary */
 727                 return chip->bdl_pos_adj ? 0 : -1;
 728         azx_dev->core.start_wallclk += wallclk;
 729         return 1; /* OK, it's fine */
 730 }
 731
 732 /*
 733  * The work for pending PCM period updates.
 734  */
 735 static void azx_irq_pending_work(struct work_struct *work)
 736 {
 737         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 738         struct azx *chip = &hda->chip;
 739         struct hdac_bus *bus = azx_bus(chip);
 740         struct hdac_stream *s;
 741         int pending, ok;
 742
 743         if (!hda->irq_pending_warned) {
 744                 dev_info(chip->card->dev,
 745                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 746                          chip->card->number);
 747                 hda->irq_pending_warned = 1;
 748         }
 749
 750         for (;;) {
 751                 pending = 0;
 752                 spin_lock_irq(&bus->reg_lock);
 753                 list_for_each_entry(s, &bus->stream_list, list) {
 754                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 755                         if (!azx_dev->irq_pending ||
 756                             !s->substream ||
 757                             !s->running)
 758                                 continue;
 759                         ok = azx_position_ok(chip, azx_dev);
 760                         if (ok > 0) {
 761                                 azx_dev->irq_pending = 0;
 762                                 spin_unlock(&bus->reg_lock);
 763                                 snd_pcm_period_elapsed(s->substream);
 764                                 spin_lock(&bus->reg_lock);
 765                         } else if (ok < 0) {
 766                                 pending = 0;    /* too early */
 767                         } else
 768                                 pending++;
 769                 }
 770                 spin_unlock_irq(&bus->reg_lock);
 771                 if (!pending)
 772                         return;
 773                 msleep(1);
 774         }
 775 }
 776
 777 /* clear irq_pending flags and assure no on-going workq */
 778 static void azx_clear_irq_pending(struct azx *chip)
 779 {
 780         struct hdac_bus *bus = azx_bus(chip);
 781         struct hdac_stream *s;
 782
 783         spin_lock_irq(&bus->reg_lock);
 784         list_for_each_entry(s, &bus->stream_list, list) {
 785                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 786                 azx_dev->irq_pending = 0;
 787         }
 788         spin_unlock_irq(&bus->reg_lock);
 789 }
 790
 791 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 792 {
 793         struct hdac_bus *bus = azx_bus(chip);
 794
 795         if (request_irq(chip->pci->irq, azx_interrupt,
 796                         chip->msi ? 0 : IRQF_SHARED,
 797                         chip->card->irq_descr, chip)) {
 798                 dev_err(chip->card->dev,
 799                         "unable to grab IRQ %d, disabling device\n",
 800                         chip->pci->irq);
 801                 if (do_disconnect)
 802                         snd_card_disconnect(chip->card);
 803                 return -1;
 804         }
 805         bus->irq = chip->pci->irq;
 806         pci_intx(chip->pci, !chip->msi);
 807         return 0;
 808 }
 809
 810 /* get the current DMA position with correction on VIA chips */
 811 static unsigned int azx_via_get_position(struct azx *chip,
 812                                          struct azx_dev *azx_dev)
 813 {
 814         unsigned int link_pos, mini_pos, bound_pos;
 815         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 816         unsigned int fifo_size;
 817
 818         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 819         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 820                 /* Playback, no problem using link position */
 821                 return link_pos;
 822         }
 823
 824         /* Capture */
 825         /* For new chipset,
 826          * use mod to get the DMA position just like old chipset
 827          */
 828         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 829         mod_dma_pos %= azx_dev->core.period_bytes;
 830
 831         /* azx_dev->fifo_size can't get FIFO size of in stream.
 832          * Get from base address + offset.
 833          */
 834         fifo_size = readw(azx_bus(chip)->remap_addr +
 835                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 836
 837         if (azx_dev->insufficient) {
 838                 /* Link position never gather than FIFO size */
 839                 if (link_pos <= fifo_size)
 840                         return 0;
 841
 842                 azx_dev->insufficient = 0;
 843         }
 844
 845         if (link_pos <= fifo_size)
 846                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 847         else
 848                 mini_pos = link_pos - fifo_size;
 849
 850         /* Find nearest previous boudary */
 851         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 852         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 853         if (mod_link_pos >= fifo_size)
 854                 bound_pos = link_pos - mod_link_pos;
 855         else if (mod_dma_pos >= mod_mini_pos)
 856                 bound_pos = mini_pos - mod_mini_pos;
 857         else {
 858                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 859                 if (bound_pos >= azx_dev->core.bufsize)
 860                         bound_pos = 0;
 861         }
 862
 863         /* Calculate real DMA position we want */
 864         return bound_pos + mod_dma_pos;
 865 }
 866
 867 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 868                                          struct azx_dev *azx_dev)
 869 {
 870         return _snd_hdac_chip_readl(azx_bus(chip),
 871                                     AZX_REG_VS_SDXDPIB_XBASE +
 872                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 873                                      azx_dev->core.index));
 874 }
 875
 876 /* get the current DMA position with correction on SKL+ chips */
 877 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 878 {
 879         /* DPIB register gives a more accurate position for playback */
 880         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 881                 return azx_skl_get_dpib_pos(chip, azx_dev);
 882
 883         /* For capture, we need to read posbuf, but it requires a delay
 884          * for the possible boundary overlap; the read of DPIB fetches the
 885          * actual posbuf
 886          */
 887         udelay(20);
 888         azx_skl_get_dpib_pos(chip, azx_dev);
 889         return azx_get_pos_posbuf(chip, azx_dev);
 890 }
 891
 892 #ifdef CONFIG_PM
 893 static DEFINE_MUTEX(card_list_lock);
 894 static LIST_HEAD(card_list);
 895
 896 static void azx_add_card_list(struct azx *chip)
 897 {
 898         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 899         mutex_lock(&card_list_lock);
 900         list_add(&hda->list, &card_list);
 901         mutex_unlock(&card_list_lock);
 902 }
 903
 904 static void azx_del_card_list(struct azx *chip)
 905 {
 906         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 907         mutex_lock(&card_list_lock);
 908         list_del_init(&hda->list);
 909         mutex_unlock(&card_list_lock);
 910 }
 911
 912 /* trigger power-save check at writing parameter */
 913 static int param_set_xint(const char *val, const struct kernel_param *kp)
 914 {
 915         struct hda_intel *hda;
 916         struct azx *chip;
 917         int prev = power_save;
 918         int ret = param_set_int(val, kp);
 919
 920         if (ret || prev == power_save)
 921                 return ret;
 922
 923         mutex_lock(&card_list_lock);
 924         list_for_each_entry(hda, &card_list, list) {
 925                 chip = &hda->chip;
 926                 if (!hda->probe_continued || chip->disabled)
 927                         continue;
 928                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 929         }
 930         mutex_unlock(&card_list_lock);
 931         return 0;
 932 }
 933
 934 /*
 935  * power management
 936  */
 937 static bool azx_is_pm_ready(struct snd_card *card)
 938 {
 939         struct azx *chip;
 940         struct hda_intel *hda;
 941
 942         if (!card)
 943                 return false;
 944         chip = card->private_data;
 945         hda = container_of(chip, struct hda_intel, chip);
 946         if (chip->disabled || hda->init_failed || !chip->running)
 947                 return false;
 948         return true;
 949 }
 950
 951 static void __azx_runtime_suspend(struct azx *chip)
 952 {
 953         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 954
 955         azx_stop_chip(chip);
 956         azx_enter_link_reset(chip);
 957         azx_clear_irq_pending(chip);
 958         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 959             hda->need_i915_power)
 960                 snd_hdac_display_power(azx_bus(chip), false);
 961 }
 962
 963 static void __azx_runtime_resume(struct azx *chip)
 964 {
 965         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 966         struct hdac_bus *bus = azx_bus(chip);
 967         struct hda_codec *codec;
 968         int status;
 969
 970         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 971                 snd_hdac_display_power(bus, true);
 972                 if (hda->need_i915_power)
 973                         snd_hdac_i915_set_bclk(bus);
 974         }
 975
 976         /* Read STATESTS before controller reset */
 977         status = azx_readw(chip, STATESTS);
 978
 979         azx_init_pci(chip);
 980         hda_intel_init_chip(chip, true);
 981
 982         if (status) {
 983                 list_for_each_codec(codec, &chip->bus)
 984                         if (status & (1 << codec->addr))
 985                                 schedule_delayed_work(&codec->jackpoll_work,
 986                                                       codec->jackpoll_interval);
 987         }
 988
 989         /* power down again for link-controlled chips */
 990         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 991             !hda->need_i915_power)
 992                 snd_hdac_display_power(bus, false);
 993 }
 994
 995 #ifdef CONFIG_PM_SLEEP
 996 static int azx_suspend(struct device *dev)
 997 {
 998         struct snd_card *card = dev_get_drvdata(dev);
 999         struct azx *chip;
1000         struct hdac_bus *bus;
1001
1002         if (!azx_is_pm_ready(card))
1003                 return 0;
1004
1005         chip = card->private_data;
1006         bus = azx_bus(chip);
1007         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1008         __azx_runtime_suspend(chip);
1009         if (bus->irq >= 0) {
1010                 free_irq(bus->irq, chip);
1011                 bus->irq = -1;
1012         }
1013
1014         if (chip->msi)
1015                 pci_disable_msi(chip->pci);
1016
1017         trace_azx_suspend(chip);
1018         return 0;
1019 }
1020
1021 static int azx_resume(struct device *dev)
1022 {
1023         struct snd_card *card = dev_get_drvdata(dev);
1024         struct azx *chip;
1025
1026         if (!azx_is_pm_ready(card))
1027                 return 0;
1028
1029         chip = card->private_data;
1030         if (chip->msi)
1031                 if (pci_enable_msi(chip->pci) < 0)
1032                         chip->msi = 0;
1033         if (azx_acquire_irq(chip, 1) < 0)
1034                 return -EIO;
1035         __azx_runtime_resume(chip);
1036         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1037
1038         trace_azx_resume(chip);
1039         return 0;
1040 }
1041
1042 /* put codec down to D3 at hibernation for Intel SKL+;
1043  * otherwise BIOS may still access the codec and screw up the driver
1044  */
1045 static int azx_freeze_noirq(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip = card->private_data;
1049         struct pci_dev *pci = to_pci_dev(dev);
1050
1051         if (chip->driver_type == AZX_DRIVER_SKL)
1052                 pci_set_power_state(pci, PCI_D3hot);
1053
1054         return 0;
1055 }
1056
1057 static int azx_thaw_noirq(struct device *dev)
1058 {
1059         struct snd_card *card = dev_get_drvdata(dev);
1060         struct azx *chip = card->private_data;
1061         struct pci_dev *pci = to_pci_dev(dev);
1062
1063         if (chip->driver_type == AZX_DRIVER_SKL)
1064                 pci_set_power_state(pci, PCI_D0);
1065
1066         return 0;
1067 }
1068 #endif /* CONFIG_PM_SLEEP */
1069
1070 static int azx_runtime_suspend(struct device *dev)
1071 {
1072         struct snd_card *card = dev_get_drvdata(dev);
1073         struct azx *chip;
1074
1075         if (!azx_is_pm_ready(card))
1076                 return 0;
1077         chip = card->private_data;
1078         if (!azx_has_pm_runtime(chip))
1079                 return 0;
1080
1081         /* enable controller wake up event */
1082         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1083                   STATESTS_INT_MASK);
1084
1085         __azx_runtime_suspend(chip);
1086         trace_azx_runtime_suspend(chip);
1087         return 0;
1088 }
1089
1090 static int azx_runtime_resume(struct device *dev)
1091 {
1092         struct snd_card *card = dev_get_drvdata(dev);
1093         struct azx *chip;
1094
1095         if (!azx_is_pm_ready(card))
1096                 return 0;
1097         chip = card->private_data;
1098         if (!azx_has_pm_runtime(chip))
1099                 return 0;
1100         __azx_runtime_resume(chip);
1101
1102         /* disable controller Wake Up event*/
1103         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1104                         ~STATESTS_INT_MASK);
1105
1106         trace_azx_runtime_resume(chip);
1107         return 0;
1108 }
1109
1110 static int azx_runtime_idle(struct device *dev)
1111 {
1112         struct snd_card *card = dev_get_drvdata(dev);
1113         struct azx *chip;
1114         struct hda_intel *hda;
1115
1116         if (!card)
1117                 return 0;
1118
1119         chip = card->private_data;
1120         hda = container_of(chip, struct hda_intel, chip);
1121         if (chip->disabled || hda->init_failed)
1122                 return 0;
1123
1124         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1125             azx_bus(chip)->codec_powered || !chip->running)
1126                 return -EBUSY;
1127
1128         /* ELD notification gets broken when HD-audio bus is off */
1129         if (needs_eld_notify_link(hda))
1130                 return -EBUSY;
1131
1132         return 0;
1133 }
1134
1135 static const struct dev_pm_ops azx_pm = {
1136         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1137 #ifdef CONFIG_PM_SLEEP
1138         .freeze_noirq = azx_freeze_noirq,
1139         .thaw_noirq = azx_thaw_noirq,
1140 #endif
1141         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1142 };
1143
1144 #define AZX_PM_OPS      &azx_pm
1145 #else
1146 #define azx_add_card_list(chip) /* NOP */
1147 #define azx_del_card_list(chip) /* NOP */
1148 #define AZX_PM_OPS      NULL
1149 #endif /* CONFIG_PM */
1150
1151
1152 static int azx_probe_continue(struct azx *chip);
1153
1154 #ifdef SUPPORT_VGA_SWITCHEROO
1155 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1156
1157 static void azx_vs_set_state(struct pci_dev *pci,
1158                              enum vga_switcheroo_state state)
1159 {
1160         struct snd_card *card = pci_get_drvdata(pci);
1161         struct azx *chip = card->private_data;
1162         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1163         struct hda_codec *codec;
1164         bool disabled;
1165
1166         wait_for_completion(&hda->probe_wait);
1167         if (hda->init_failed)
1168                 return;
1169
1170         disabled = (state == VGA_SWITCHEROO_OFF);
1171         if (chip->disabled == disabled)
1172                 return;
1173
1174         if (!hda->probe_continued) {
1175                 chip->disabled = disabled;
1176                 if (!disabled) {
1177                         dev_info(chip->card->dev,
1178                                  "Start delayed initialization\n");
1179                         if (azx_probe_continue(chip) < 0) {
1180                                 dev_err(chip->card->dev, "initialization error\n");
1181                                 hda->init_failed = true;
1182                         }
1183                 }
1184         } else {
1185                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1186                          disabled ? "Disabling" : "Enabling");
1187                 if (disabled) {
1188                         list_for_each_codec(codec, &chip->bus) {
1189                                 pm_runtime_suspend(hda_codec_dev(codec));
1190                                 pm_runtime_disable(hda_codec_dev(codec));
1191                         }
1192                         pm_runtime_suspend(card->dev);
1193                         pm_runtime_disable(card->dev);
1194                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1195                          * however we have no ACPI handle, so pci/acpi can't put us there,
1196                          * put ourselves there */
1197                         pci->current_state = PCI_D3cold;
1198                         chip->disabled = true;
1199                         if (snd_hda_lock_devices(&chip->bus))
1200                                 dev_warn(chip->card->dev,
1201                                          "Cannot lock devices!\n");
1202                 } else {
1203                         snd_hda_unlock_devices(&chip->bus);
1204                         chip->disabled = false;
1205                         pm_runtime_enable(card->dev);
1206                         list_for_each_codec(codec, &chip->bus) {
1207                                 pm_runtime_enable(hda_codec_dev(codec));
1208                                 pm_runtime_resume(hda_codec_dev(codec));
1209                         }
1210                 }
1211         }
1212 }
1213
1214 static bool azx_vs_can_switch(struct pci_dev *pci)
1215 {
1216         struct snd_card *card = pci_get_drvdata(pci);
1217         struct azx *chip = card->private_data;
1218         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1219
1220         wait_for_completion(&hda->probe_wait);
1221         if (hda->init_failed)
1222                 return false;
1223         if (chip->disabled || !hda->probe_continued)
1224                 return true;
1225         if (snd_hda_lock_devices(&chip->bus))
1226                 return false;
1227         snd_hda_unlock_devices(&chip->bus);
1228         return true;
1229 }
1230
1231 /*
1232  * The discrete GPU cannot power down unless the HDA controller runtime
1233  * suspends, so activate runtime PM on codecs even if power_save == 0.
1234  */
1235 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1236 {
1237         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1238         struct hda_codec *codec;
1239
1240         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1241                 list_for_each_codec(codec, &chip->bus)
1242                         codec->auto_runtime_pm = 1;
1243                 /* reset the power save setup */
1244                 if (chip->running)
1245                         set_default_power_save(chip);
1246         }
1247 }
1248
1249 static void azx_vs_gpu_bound(struct pci_dev *pci,
1250                              enum vga_switcheroo_client_id client_id)
1251 {
1252         struct snd_card *card = pci_get_drvdata(pci);
1253         struct azx *chip = card->private_data;
1254         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1255
1256         if (client_id == VGA_SWITCHEROO_DIS)
1257                 hda->need_eld_notify_link = 0;
1258         setup_vga_switcheroo_runtime_pm(chip);
1259 }
1260
1261 static void init_vga_switcheroo(struct azx *chip)
1262 {
1263         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1264         struct pci_dev *p = get_bound_vga(chip->pci);
1265         if (p) {
1266                 dev_info(chip->card->dev,
1267                          "Handle vga_switcheroo audio client\n");
1268                 hda->use_vga_switcheroo = 1;
1269                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1270                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1271                 pci_dev_put(p);
1272         }
1273 }
1274
1275 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1276         .set_gpu_state = azx_vs_set_state,
1277         .can_switch = azx_vs_can_switch,
1278         .gpu_bound = azx_vs_gpu_bound,
1279 };
1280
1281 static int register_vga_switcheroo(struct azx *chip)
1282 {
1283         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1284         struct pci_dev *p;
1285         int err;
1286
1287         if (!hda->use_vga_switcheroo)
1288                 return 0;
1289
1290         p = get_bound_vga(chip->pci);
1291         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1292         pci_dev_put(p);
1293
1294         if (err < 0)
1295                 return err;
1296         hda->vga_switcheroo_registered = 1;
1297
1298         return 0;
1299 }
1300 #else
1301 #define init_vga_switcheroo(chip)               /* NOP */
1302 #define register_vga_switcheroo(chip)           0
1303 #define check_hdmi_disabled(pci)        false
1304 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1305 #endif /* SUPPORT_VGA_SWITCHER */
1306
1307 /*
1308  * destructor
1309  */
1310 static int azx_free(struct azx *chip)
1311 {
1312         struct pci_dev *pci = chip->pci;
1313         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1314         struct hdac_bus *bus = azx_bus(chip);
1315
1316         if (azx_has_pm_runtime(chip) && chip->running)
1317                 pm_runtime_get_noresume(&pci->dev);
1318         chip->running = 0;
1319
1320         azx_del_card_list(chip);
1321
1322         hda->init_failed = 1; /* to be sure */
1323         complete_all(&hda->probe_wait);
1324
1325         if (use_vga_switcheroo(hda)) {
1326                 if (chip->disabled && hda->probe_continued)
1327                         snd_hda_unlock_devices(&chip->bus);
1328                 if (hda->vga_switcheroo_registered)
1329                         vga_switcheroo_unregister_client(chip->pci);
1330         }
1331
1332         if (bus->chip_init) {
1333                 azx_clear_irq_pending(chip);
1334                 azx_stop_all_streams(chip);
1335                 azx_stop_chip(chip);
1336         }
1337
1338         if (bus->irq >= 0)
1339                 free_irq(bus->irq, (void*)chip);
1340         if (chip->msi)
1341                 pci_disable_msi(chip->pci);
1342         iounmap(bus->remap_addr);
1343
1344         azx_free_stream_pages(chip);
1345         azx_free_streams(chip);
1346         snd_hdac_bus_exit(bus);
1347
1348         if (chip->region_requested)
1349                 pci_release_regions(chip->pci);
1350
1351         pci_disable_device(chip->pci);
1352 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1353         release_firmware(chip->fw);
1354 #endif
1355
1356         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1357                 if (hda->need_i915_power)
1358                         snd_hdac_display_power(bus, false);
1359         }
1360         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1361                 snd_hdac_i915_exit(bus);
1362         kfree(hda);
1363
1364         return 0;
1365 }
1366
1367 static int azx_dev_disconnect(struct snd_device *device)
1368 {
1369         struct azx *chip = device->device_data;
1370
1371         chip->bus.shutdown = 1;
1372         return 0;
1373 }
1374
1375 static int azx_dev_free(struct snd_device *device)
1376 {
1377         return azx_free(device->device_data);
1378 }
1379
1380 #ifdef SUPPORT_VGA_SWITCHEROO
1381 /*
1382  * Check of disabled HDMI controller by vga_switcheroo
1383  */
1384 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1385 {
1386         struct pci_dev *p;
1387
1388         /* check only discrete GPU */
1389         switch (pci->vendor) {
1390         case PCI_VENDOR_ID_ATI:
1391         case PCI_VENDOR_ID_AMD:
1392         case PCI_VENDOR_ID_NVIDIA:
1393                 if (pci->devfn == 1) {
1394                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1395                                                         pci->bus->number, 0);
1396                         if (p) {
1397                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1398                                         return p;
1399                                 pci_dev_put(p);
1400                         }
1401                 }
1402                 break;
1403         }
1404         return NULL;
1405 }
1406
1407 static bool check_hdmi_disabled(struct pci_dev *pci)
1408 {
1409         bool vga_inactive = false;
1410         struct pci_dev *p = get_bound_vga(pci);
1411
1412         if (p) {
1413                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1414                         vga_inactive = true;
1415                 pci_dev_put(p);
1416         }
1417         return vga_inactive;
1418 }
1419 #endif /* SUPPORT_VGA_SWITCHEROO */
1420
1421 /*
1422  * white/black-listing for position_fix
1423  */
1424 static struct snd_pci_quirk position_fix_list[] = {
1425         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1426         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1427         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1428         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1429         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1430         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1431         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1432         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1433         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1434         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1435         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1436         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1437         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1438         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1439         {}
1440 };
1441
1442 static int check_position_fix(struct azx *chip, int fix)
1443 {
1444         const struct snd_pci_quirk *q;
1445
1446         switch (fix) {
1447         case POS_FIX_AUTO:
1448         case POS_FIX_LPIB:
1449         case POS_FIX_POSBUF:
1450         case POS_FIX_VIACOMBO:
1451         case POS_FIX_COMBO:
1452         case POS_FIX_SKL:
1453                 return fix;
1454         }
1455
1456         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1457         if (q) {
1458                 dev_info(chip->card->dev,
1459                          "position_fix set to %d for device %04x:%04x\n",
1460                          q->value, q->subvendor, q->subdevice);
1461                 return q->value;
1462         }
1463
1464         /* Check VIA/ATI HD Audio Controller exist */
1465         if (chip->driver_type == AZX_DRIVER_VIA) {
1466                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1467                 return POS_FIX_VIACOMBO;
1468         }
1469         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1470                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1471                 return POS_FIX_LPIB;
1472         }
1473         if (chip->driver_type == AZX_DRIVER_SKL) {
1474                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1475                 return POS_FIX_SKL;
1476         }
1477         return POS_FIX_AUTO;
1478 }
1479
1480 static void assign_position_fix(struct azx *chip, int fix)
1481 {
1482         static azx_get_pos_callback_t callbacks[] = {
1483                 [POS_FIX_AUTO] = NULL,
1484                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1485                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1486                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1487                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1488                 [POS_FIX_SKL] = azx_get_pos_skl,
1489         };
1490
1491         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1492
1493         /* combo mode uses LPIB only for playback */
1494         if (fix == POS_FIX_COMBO)
1495                 chip->get_position[1] = NULL;
1496
1497         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1498             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1499                 chip->get_delay[0] = chip->get_delay[1] =
1500                         azx_get_delay_from_lpib;
1501         }
1502
1503 }
1504
1505 /*
1506  * black-lists for probe_mask
1507  */
1508 static struct snd_pci_quirk probe_mask_list[] = {
1509         /* Thinkpad often breaks the controller communication when accessing
1510          * to the non-working (or non-existing) modem codec slot.
1511          */
1512         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1513         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1514         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1515         /* broken BIOS */
1516         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1517         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1518         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1519         /* forced codec slots */
1520         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1521         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1522         /* WinFast VP200 H (Teradici) user reported broken communication */
1523         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1524         {}
1525 };
1526
1527 #define AZX_FORCE_CODEC_MASK    0x100
1528
1529 static void check_probe_mask(struct azx *chip, int dev)
1530 {
1531         const struct snd_pci_quirk *q;
1532
1533         chip->codec_probe_mask = probe_mask[dev];
1534         if (chip->codec_probe_mask == -1) {
1535                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1536                 if (q) {
1537                         dev_info(chip->card->dev,
1538                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1539                                  q->value, q->subvendor, q->subdevice);
1540                         chip->codec_probe_mask = q->value;
1541                 }
1542         }
1543
1544         /* check forced option */
1545         if (chip->codec_probe_mask != -1 &&
1546             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1547                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1548                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1549                          (int)azx_bus(chip)->codec_mask);
1550         }
1551 }
1552
1553 /*
1554  * white/black-list for enable_msi
1555  */
1556 static struct snd_pci_quirk msi_black_list[] = {
1557         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1558         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1559         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1560         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1561         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1562         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1563         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1564         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1565         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1566         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1567         {}
1568 };
1569
1570 static void check_msi(struct azx *chip)
1571 {
1572         const struct snd_pci_quirk *q;
1573
1574         if (enable_msi >= 0) {
1575                 chip->msi = !!enable_msi;
1576                 return;
1577         }
1578         chip->msi = 1;  /* enable MSI as default */
1579         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1580         if (q) {
1581                 dev_info(chip->card->dev,
1582                          "msi for device %04x:%04x set to %d\n",
1583                          q->subvendor, q->subdevice, q->value);
1584                 chip->msi = q->value;
1585                 return;
1586         }
1587
1588         /* NVidia chipsets seem to cause troubles with MSI */
1589         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1590                 dev_info(chip->card->dev, "Disabling MSI\n");
1591                 chip->msi = 0;
1592         }
1593 }
1594
1595 /* check the snoop mode availability */
1596 static void azx_check_snoop_available(struct azx *chip)
1597 {
1598         int snoop = hda_snoop;
1599
1600         if (snoop >= 0) {
1601                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1602                          snoop ? "snoop" : "non-snoop");
1603                 chip->snoop = snoop;
1604                 chip->uc_buffer = !snoop;
1605                 return;
1606         }
1607
1608         snoop = true;
1609         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1610             chip->driver_type == AZX_DRIVER_VIA) {
1611                 /* force to non-snoop mode for a new VIA controller
1612                  * when BIOS is set
1613                  */
1614                 u8 val;
1615                 pci_read_config_byte(chip->pci, 0x42, &val);
1616                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1617                                       chip->pci->revision == 0x20))
1618                         snoop = false;
1619         }
1620
1621         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1622                 snoop = false;
1623
1624         chip->snoop = snoop;
1625         if (!snoop) {
1626                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1627                 /* C-Media requires non-cached pages only for CORB/RIRB */
1628                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1629                         chip->uc_buffer = true;
1630         }
1631 }
1632
1633 static void azx_probe_work(struct work_struct *work)
1634 {
1635         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1636         azx_probe_continue(&hda->chip);
1637 }
1638
1639 static int default_bdl_pos_adj(struct azx *chip)
1640 {
1641         /* some exceptions: Atoms seem problematic with value 1 */
1642         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1643                 switch (chip->pci->device) {
1644                 case 0x0f04: /* Baytrail */
1645                 case 0x2284: /* Braswell */
1646                         return 32;
1647                 }
1648         }
1649
1650         switch (chip->driver_type) {
1651         case AZX_DRIVER_ICH:
1652         case AZX_DRIVER_PCH:
1653                 return 1;
1654         default:
1655                 return 32;
1656         }
1657 }
1658
1659 /*
1660  * constructor
1661  */
1662 static const struct hdac_io_ops pci_hda_io_ops;
1663 static const struct hda_controller_ops pci_hda_ops;
1664
1665 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1666                       int dev, unsigned int driver_caps,
1667                       struct azx **rchip)
1668 {
1669         static struct snd_device_ops ops = {
1670                 .dev_disconnect = azx_dev_disconnect,
1671                 .dev_free = azx_dev_free,
1672         };
1673         struct hda_intel *hda;
1674         struct azx *chip;
1675         int err;
1676
1677         *rchip = NULL;
1678
1679         err = pci_enable_device(pci);
1680         if (err < 0)
1681                 return err;
1682
1683         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1684         if (!hda) {
1685                 pci_disable_device(pci);
1686                 return -ENOMEM;
1687         }
1688
1689         chip = &hda->chip;
1690         mutex_init(&chip->open_mutex);
1691         chip->card = card;
1692         chip->pci = pci;
1693         chip->ops = &pci_hda_ops;
1694         chip->driver_caps = driver_caps;
1695         chip->driver_type = driver_caps & 0xff;
1696         check_msi(chip);
1697         chip->dev_index = dev;
1698         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1699                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1700         INIT_LIST_HEAD(&chip->pcm_list);
1701         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1702         INIT_LIST_HEAD(&hda->list);
1703         init_vga_switcheroo(chip);
1704         init_completion(&hda->probe_wait);
1705
1706         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1707
1708         check_probe_mask(chip, dev);
1709
1710         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1711                 chip->fallback_to_single_cmd = 1;
1712         else /* explicitly set to single_cmd or not */
1713                 chip->single_cmd = single_cmd;
1714
1715         azx_check_snoop_available(chip);
1716
1717         if (bdl_pos_adj[dev] < 0)
1718                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1719         else
1720                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1721
1722         /* Workaround for a communication error on CFL (bko#199007) */
1723         if (IS_CFL(pci))
1724                 chip->polling_mode = 1;
1725
1726         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1727         if (err < 0) {
1728                 kfree(hda);
1729                 pci_disable_device(pci);
1730                 return err;
1731         }
1732
1733         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1734                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1735                 chip->bus.needs_damn_long_delay = 1;
1736         }
1737
1738         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1739         if (err < 0) {
1740                 dev_err(card->dev, "Error creating device [card]!\n");
1741                 azx_free(chip);
1742                 return err;
1743         }
1744
1745         /* continue probing in work context as may trigger request module */
1746         INIT_WORK(&hda->probe_work, azx_probe_work);
1747
1748         *rchip = chip;
1749
1750         return 0;
1751 }
1752
1753 static int azx_first_init(struct azx *chip)
1754 {
1755         int dev = chip->dev_index;
1756         struct pci_dev *pci = chip->pci;
1757         struct snd_card *card = chip->card;
1758         struct hdac_bus *bus = azx_bus(chip);
1759         int err;
1760         unsigned short gcap;
1761         unsigned int dma_bits = 64;
1762
1763 #if BITS_PER_LONG != 64
1764         /* Fix up base address on ULI M5461 */
1765         if (chip->driver_type == AZX_DRIVER_ULI) {
1766                 u16 tmp3;
1767                 pci_read_config_word(pci, 0x40, &tmp3);
1768                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1769                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1770         }
1771 #endif
1772
1773         err = pci_request_regions(pci, "ICH HD audio");
1774         if (err < 0)
1775                 return err;
1776         chip->region_requested = 1;
1777
1778         bus->addr = pci_resource_start(pci, 0);
1779         bus->remap_addr = pci_ioremap_bar(pci, 0);
1780         if (bus->remap_addr == NULL) {
1781                 dev_err(card->dev, "ioremap error\n");
1782                 return -ENXIO;
1783         }
1784
1785         if (chip->driver_type == AZX_DRIVER_SKL)
1786                 snd_hdac_bus_parse_capabilities(bus);
1787
1788         /*
1789          * Some Intel CPUs has always running timer (ART) feature and
1790          * controller may have Global time sync reporting capability, so
1791          * check both of these before declaring synchronized time reporting
1792          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1793          */
1794         chip->gts_present = false;
1795
1796 #ifdef CONFIG_X86
1797         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1798                 chip->gts_present = true;
1799 #endif
1800
1801         if (chip->msi) {
1802                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1803                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1804                         pci->no_64bit_msi = true;
1805                 }
1806                 if (pci_enable_msi(pci) < 0)
1807                         chip->msi = 0;
1808         }
1809
1810         if (azx_acquire_irq(chip, 0) < 0)
1811                 return -EBUSY;
1812
1813         pci_set_master(pci);
1814         synchronize_irq(bus->irq);
1815
1816         gcap = azx_readw(chip, GCAP);
1817         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1818
1819         /* AMD devices support 40 or 48bit DMA, take the safe one */
1820         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1821                 dma_bits = 40;
1822
1823         /* disable SB600 64bit support for safety */
1824         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1825                 struct pci_dev *p_smbus;
1826                 dma_bits = 40;
1827                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1828                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1829                                          NULL);
1830                 if (p_smbus) {
1831                         if (p_smbus->revision < 0x30)
1832                                 gcap &= ~AZX_GCAP_64OK;
1833                         pci_dev_put(p_smbus);
1834                 }
1835         }
1836
1837         /* NVidia hardware normally only supports up to 40 bits of DMA */
1838         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1839                 dma_bits = 40;
1840
1841         /* disable 64bit DMA address on some devices */
1842         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1843                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1844                 gcap &= ~AZX_GCAP_64OK;
1845         }
1846
1847         /* disable buffer size rounding to 128-byte multiples if supported */
1848         if (align_buffer_size >= 0)
1849                 chip->align_buffer_size = !!align_buffer_size;
1850         else {
1851                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1852                         chip->align_buffer_size = 0;
1853                 else
1854                         chip->align_buffer_size = 1;
1855         }
1856
1857         /* allow 64bit DMA address if supported by H/W */
1858         if (!(gcap & AZX_GCAP_64OK))
1859                 dma_bits = 32;
1860         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1861                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1862         } else {
1863                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1864                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1865         }
1866
1867         /* read number of streams from GCAP register instead of using
1868          * hardcoded value
1869          */
1870         chip->capture_streams = (gcap >> 8) & 0x0f;
1871         chip->playback_streams = (gcap >> 12) & 0x0f;
1872         if (!chip->playback_streams && !chip->capture_streams) {
1873                 /* gcap didn't give any info, switching to old method */
1874
1875                 switch (chip->driver_type) {
1876                 case AZX_DRIVER_ULI:
1877                         chip->playback_streams = ULI_NUM_PLAYBACK;
1878                         chip->capture_streams = ULI_NUM_CAPTURE;
1879                         break;
1880                 case AZX_DRIVER_ATIHDMI:
1881                 case AZX_DRIVER_ATIHDMI_NS:
1882                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1883                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1884                         break;
1885                 case AZX_DRIVER_GENERIC:
1886                 default:
1887                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1888                         chip->capture_streams = ICH6_NUM_CAPTURE;
1889                         break;
1890                 }
1891         }
1892         chip->capture_index_offset = 0;
1893         chip->playback_index_offset = chip->capture_streams;
1894         chip->num_streams = chip->playback_streams + chip->capture_streams;
1895
1896         /* sanity check for the SDxCTL.STRM field overflow */
1897         if (chip->num_streams > 15 &&
1898             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1899                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1900                          "forcing separate stream tags", chip->num_streams);
1901                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1902         }
1903
1904         /* initialize streams */
1905         err = azx_init_streams(chip);
1906         if (err < 0)
1907                 return err;
1908
1909         err = azx_alloc_stream_pages(chip);
1910         if (err < 0)
1911                 return err;
1912
1913         /* initialize chip */
1914         azx_init_pci(chip);
1915
1916         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1917                 snd_hdac_i915_set_bclk(bus);
1918
1919         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1920
1921         /* codec detection */
1922         if (!azx_bus(chip)->codec_mask) {
1923                 dev_err(card->dev, "no codecs found!\n");
1924                 return -ENODEV;
1925         }
1926
1927         strcpy(card->driver, "HDA-Intel");
1928         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1929                 sizeof(card->shortname));
1930         snprintf(card->longname, sizeof(card->longname),
1931                  "%s at 0x%lx irq %i",
1932                  card->shortname, bus->addr, bus->irq);
1933
1934         return 0;
1935 }
1936
1937 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1938 /* callback from request_firmware_nowait() */
1939 static void azx_firmware_cb(const struct firmware *fw, void *context)
1940 {
1941         struct snd_card *card = context;
1942         struct azx *chip = card->private_data;
1943         struct pci_dev *pci = chip->pci;
1944
1945         if (!fw) {
1946                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1947                 goto error;
1948         }
1949
1950         chip->fw = fw;
1951         if (!chip->disabled) {
1952                 /* continue probing */
1953                 if (azx_probe_continue(chip))
1954                         goto error;
1955         }
1956         return; /* OK */
1957
1958  error:
1959         snd_card_free(card);
1960         pci_set_drvdata(pci, NULL);
1961 }
1962 #endif
1963
1964 /*
1965  * HDA controller ops.
1966  */
1967
1968 /* PCI register access. */
1969 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1970 {
1971         writel(value, addr);
1972 }
1973
1974 static u32 pci_azx_readl(u32 __iomem *addr)
1975 {
1976         return readl(addr);
1977 }
1978
1979 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1980 {
1981         writew(value, addr);
1982 }
1983
1984 static u16 pci_azx_readw(u16 __iomem *addr)
1985 {
1986         return readw(addr);
1987 }
1988
1989 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1990 {
1991         writeb(value, addr);
1992 }
1993
1994 static u8 pci_azx_readb(u8 __iomem *addr)
1995 {
1996         return readb(addr);
1997 }
1998
1999 static int disable_msi_reset_irq(struct azx *chip)
2000 {
2001         struct hdac_bus *bus = azx_bus(chip);
2002         int err;
2003
2004         free_irq(bus->irq, chip);
2005         bus->irq = -1;
2006         pci_disable_msi(chip->pci);
2007         chip->msi = 0;
2008         err = azx_acquire_irq(chip, 1);
2009         if (err < 0)
2010                 return err;
2011
2012         return 0;
2013 }
2014
2015 /* DMA page allocation helpers.  */
2016 static int dma_alloc_pages(struct hdac_bus *bus,
2017                            int type,
2018                            size_t size,
2019                            struct snd_dma_buffer *buf)
2020 {
2021         struct azx *chip = bus_to_azx(bus);
2022
2023         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2024                 type = SNDRV_DMA_TYPE_DEV_UC;
2025         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2026 }
2027
2028 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2029 {
2030         snd_dma_free_pages(buf);
2031 }
2032
2033 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2034                              struct vm_area_struct *area)
2035 {
2036 #ifdef CONFIG_X86
2037         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2038         struct azx *chip = apcm->chip;
2039         if (chip->uc_buffer)
2040                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2041 #endif
2042 }
2043
2044 static const struct hdac_io_ops pci_hda_io_ops = {
2045         .reg_writel = pci_azx_writel,
2046         .reg_readl = pci_azx_readl,
2047         .reg_writew = pci_azx_writew,
2048         .reg_readw = pci_azx_readw,
2049         .reg_writeb = pci_azx_writeb,
2050         .reg_readb = pci_azx_readb,
2051         .dma_alloc_pages = dma_alloc_pages,
2052         .dma_free_pages = dma_free_pages,
2053 };
2054
2055 static const struct hda_controller_ops pci_hda_ops = {
2056         .disable_msi_reset_irq = disable_msi_reset_irq,
2057         .pcm_mmap_prepare = pcm_mmap_prepare,
2058         .position_check = azx_position_check,
2059         .link_power = azx_intel_link_power,
2060 };
2061
2062 static int azx_probe(struct pci_dev *pci,
2063                      const struct pci_device_id *pci_id)
2064 {
2065         static int dev;
2066         struct snd_card *card;
2067         struct hda_intel *hda;
2068         struct azx *chip;
2069         bool schedule_probe;
2070         int err;
2071
2072         if (dev >= SNDRV_CARDS)
2073                 return -ENODEV;
2074         if (!enable[dev]) {
2075                 dev++;
2076                 return -ENOENT;
2077         }
2078
2079         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2080                            0, &card);
2081         if (err < 0) {
2082                 dev_err(&pci->dev, "Error creating card!\n");
2083                 return err;
2084         }
2085
2086         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2087         if (err < 0)
2088                 goto out_free;
2089         card->private_data = chip;
2090         hda = container_of(chip, struct hda_intel, chip);
2091
2092         pci_set_drvdata(pci, card);
2093
2094         err = register_vga_switcheroo(chip);
2095         if (err < 0) {
2096                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2097                 goto out_free;
2098         }
2099
2100         if (check_hdmi_disabled(pci)) {
2101                 dev_info(card->dev, "VGA controller is disabled\n");
2102                 dev_info(card->dev, "Delaying initialization\n");
2103                 chip->disabled = true;
2104         }
2105
2106         schedule_probe = !chip->disabled;
2107
2108 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2109         if (patch[dev] && *patch[dev]) {
2110                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2111                          patch[dev]);
2112                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2113                                               &pci->dev, GFP_KERNEL, card,
2114                                               azx_firmware_cb);
2115                 if (err < 0)
2116                         goto out_free;
2117                 schedule_probe = false; /* continued in azx_firmware_cb() */
2118         }
2119 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2120
2121 #ifndef CONFIG_SND_HDA_I915
2122         if (CONTROLLER_IN_GPU(pci))
2123                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2124 #endif
2125
2126         if (schedule_probe)
2127                 schedule_work(&hda->probe_work);
2128
2129         dev++;
2130         if (chip->disabled)
2131                 complete_all(&hda->probe_wait);
2132         return 0;
2133
2134 out_free:
2135         snd_card_free(card);
2136         return err;
2137 }
2138
2139 #ifdef CONFIG_PM
2140 /* On some boards setting power_save to a non 0 value leads to clicking /
2141  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2142  * figure out how to avoid these sounds, but that is not always feasible.
2143  * So we keep a list of devices where we disable powersaving as its known
2144  * to causes problems on these devices.
2145  */
2146 static struct snd_pci_quirk power_save_blacklist[] = {
2147         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2148         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2149         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2150         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2151         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2152         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2155         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2156         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2157         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2158         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2159         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2160         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2161         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2162         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2163         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2164         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2165         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2166         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2167         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2168         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2169         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2170         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2171         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2172         {}
2173 };
2174 #endif /* CONFIG_PM */
2175
2176 static void set_default_power_save(struct azx *chip)
2177 {
2178         int val = power_save;
2179
2180 #ifdef CONFIG_PM
2181         if (pm_blacklist) {
2182                 const struct snd_pci_quirk *q;
2183
2184                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2185                 if (q && val) {
2186                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2187                                  q->subvendor, q->subdevice);
2188                         val = 0;
2189                 }
2190         }
2191 #endif /* CONFIG_PM */
2192         snd_hda_set_power_save(&chip->bus, val * 1000);
2193 }
2194
2195 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2196 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2197         [AZX_DRIVER_NVIDIA] = 8,
2198         [AZX_DRIVER_TERA] = 1,
2199 };
2200
2201 static int azx_probe_continue(struct azx *chip)
2202 {
2203         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2204         struct hdac_bus *bus = azx_bus(chip);
2205         struct pci_dev *pci = chip->pci;
2206         int dev = chip->dev_index;
2207         int err;
2208
2209         hda->probe_continued = 1;
2210
2211         /* bind with i915 if needed */
2212         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2213                 err = snd_hdac_i915_init(bus);
2214                 if (err < 0) {
2215                         /* if the controller is bound only with HDMI/DP
2216                          * (for HSW and BDW), we need to abort the probe;
2217                          * for other chips, still continue probing as other
2218                          * codecs can be on the same link.
2219                          */
2220                         if (CONTROLLER_IN_GPU(pci)) {
2221                                 dev_err(chip->card->dev,
2222                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2223                                 goto out_free;
2224                         } else {
2225                                 /* don't bother any longer */
2226                                 chip->driver_caps &=
2227                                         ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2228                         }
2229                 }
2230         }
2231
2232         /* Request display power well for the HDA controller or codec. For
2233          * Haswell/Broadwell, both the display HDA controller and codec need
2234          * this power. For other platforms, like Baytrail/Braswell, only the
2235          * display codec needs the power and it can be released after probe.
2236          */
2237         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2238                 /* HSW/BDW controllers need this power */
2239                 if (CONTROLLER_IN_GPU(pci))
2240                         hda->need_i915_power = 1;
2241
2242                 err = snd_hdac_display_power(bus, true);
2243                 if (err < 0) {
2244                         dev_err(chip->card->dev,
2245                                 "Cannot turn on display power on i915\n");
2246                         goto i915_power_fail;
2247                 }
2248         }
2249
2250         err = azx_first_init(chip);
2251         if (err < 0)
2252                 goto out_free;
2253
2254 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2255         chip->beep_mode = beep_mode[dev];
2256 #endif
2257
2258         /* create codec instances */
2259         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2260         if (err < 0)
2261                 goto out_free;
2262
2263 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2264         if (chip->fw) {
2265                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2266                                          chip->fw->data);
2267                 if (err < 0)
2268                         goto out_free;
2269 #ifndef CONFIG_PM
2270                 release_firmware(chip->fw); /* no longer needed */
2271                 chip->fw = NULL;
2272 #endif
2273         }
2274 #endif
2275         if ((probe_only[dev] & 1) == 0) {
2276                 err = azx_codec_configure(chip);
2277                 if (err < 0)
2278                         goto out_free;
2279         }
2280
2281         err = snd_card_register(chip->card);
2282         if (err < 0)
2283                 goto out_free;
2284
2285         setup_vga_switcheroo_runtime_pm(chip);
2286
2287         chip->running = 1;
2288         azx_add_card_list(chip);
2289
2290         set_default_power_save(chip);
2291
2292         if (azx_has_pm_runtime(chip))
2293                 pm_runtime_put_autosuspend(&pci->dev);
2294
2295 out_free:
2296         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2297                 && !hda->need_i915_power)
2298                 snd_hdac_display_power(bus, false);
2299
2300 i915_power_fail:
2301         if (err < 0)
2302                 hda->init_failed = 1;
2303         complete_all(&hda->probe_wait);
2304         return err;
2305 }
2306
2307 static void azx_remove(struct pci_dev *pci)
2308 {
2309         struct snd_card *card = pci_get_drvdata(pci);
2310         struct azx *chip;
2311         struct hda_intel *hda;
2312
2313         if (card) {
2314                 /* cancel the pending probing work */
2315                 chip = card->private_data;
2316                 hda = container_of(chip, struct hda_intel, chip);
2317                 /* FIXME: below is an ugly workaround.
2318                  * Both device_release_driver() and driver_probe_device()
2319                  * take *both* the device's and its parent's lock before
2320                  * calling the remove() and probe() callbacks.  The codec
2321                  * probe takes the locks of both the codec itself and its
2322                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2323                  * the PCI controller is unbound, it takes its lock, too
2324                  * ==> ouch, a deadlock!
2325                  * As a workaround, we unlock temporarily here the controller
2326                  * device during cancel_work_sync() call.
2327                  */
2328                 device_unlock(&pci->dev);
2329                 cancel_work_sync(&hda->probe_work);
2330                 device_lock(&pci->dev);
2331
2332                 snd_card_free(card);
2333         }
2334 }
2335
2336 static void azx_shutdown(struct pci_dev *pci)
2337 {
2338         struct snd_card *card = pci_get_drvdata(pci);
2339         struct azx *chip;
2340
2341         if (!card)
2342                 return;
2343         chip = card->private_data;
2344         if (chip && chip->running)
2345                 azx_stop_chip(chip);
2346 }
2347
2348 /* PCI IDs */
2349 static const struct pci_device_id azx_ids[] = {
2350         /* CPT */
2351         { PCI_DEVICE(0x8086, 0x1c20),
2352           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2353         /* PBG */
2354         { PCI_DEVICE(0x8086, 0x1d20),
2355           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2356         /* Panther Point */
2357         { PCI_DEVICE(0x8086, 0x1e20),
2358           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2359         /* Lynx Point */
2360         { PCI_DEVICE(0x8086, 0x8c20),
2361           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2362         /* 9 Series */
2363         { PCI_DEVICE(0x8086, 0x8ca0),
2364           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2365         /* Wellsburg */
2366         { PCI_DEVICE(0x8086, 0x8d20),
2367           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2368         { PCI_DEVICE(0x8086, 0x8d21),
2369           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2370         /* Lewisburg */
2371         { PCI_DEVICE(0x8086, 0xa1f0),
2372           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2373         { PCI_DEVICE(0x8086, 0xa270),
2374           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2375         /* Lynx Point-LP */
2376         { PCI_DEVICE(0x8086, 0x9c20),
2377           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2378         /* Lynx Point-LP */
2379         { PCI_DEVICE(0x8086, 0x9c21),
2380           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2381         /* Wildcat Point-LP */
2382         { PCI_DEVICE(0x8086, 0x9ca0),
2383           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2384         /* Sunrise Point */
2385         { PCI_DEVICE(0x8086, 0xa170),
2386           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2387         /* Sunrise Point-LP */
2388         { PCI_DEVICE(0x8086, 0x9d70),
2389           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2390         /* Kabylake */
2391         { PCI_DEVICE(0x8086, 0xa171),
2392           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2393         /* Kabylake-LP */
2394         { PCI_DEVICE(0x8086, 0x9d71),
2395           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2396         /* Kabylake-H */
2397         { PCI_DEVICE(0x8086, 0xa2f0),
2398           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2399         /* Coffelake */
2400         { PCI_DEVICE(0x8086, 0xa348),
2401           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2402         /* Cannonlake */
2403         { PCI_DEVICE(0x8086, 0x9dc8),
2404           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2405         /* Icelake */
2406         { PCI_DEVICE(0x8086, 0x34c8),
2407           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2408         /* Broxton-P(Apollolake) */
2409         { PCI_DEVICE(0x8086, 0x5a98),
2410           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2411         /* Broxton-T */
2412         { PCI_DEVICE(0x8086, 0x1a98),
2413           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2414         /* Gemini-Lake */
2415         { PCI_DEVICE(0x8086, 0x3198),
2416           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2417         /* Haswell */
2418         { PCI_DEVICE(0x8086, 0x0a0c),
2419           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2420         { PCI_DEVICE(0x8086, 0x0c0c),
2421           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2422         { PCI_DEVICE(0x8086, 0x0d0c),
2423           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2424         /* Broadwell */
2425         { PCI_DEVICE(0x8086, 0x160c),
2426           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2427         /* 5 Series/3400 */
2428         { PCI_DEVICE(0x8086, 0x3b56),
2429           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2430         /* Poulsbo */
2431         { PCI_DEVICE(0x8086, 0x811b),
2432           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2433         /* Oaktrail */
2434         { PCI_DEVICE(0x8086, 0x080a),
2435           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2436         /* BayTrail */
2437         { PCI_DEVICE(0x8086, 0x0f04),
2438           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2439         /* Braswell */
2440         { PCI_DEVICE(0x8086, 0x2284),
2441           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2442         /* ICH6 */
2443         { PCI_DEVICE(0x8086, 0x2668),
2444           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2445         /* ICH7 */
2446         { PCI_DEVICE(0x8086, 0x27d8),
2447           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2448         /* ESB2 */
2449         { PCI_DEVICE(0x8086, 0x269a),
2450           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2451         /* ICH8 */
2452         { PCI_DEVICE(0x8086, 0x284b),
2453           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2454         /* ICH9 */
2455         { PCI_DEVICE(0x8086, 0x293e),
2456           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2457         /* ICH9 */
2458         { PCI_DEVICE(0x8086, 0x293f),
2459           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2460         /* ICH10 */
2461         { PCI_DEVICE(0x8086, 0x3a3e),
2462           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2463         /* ICH10 */
2464         { PCI_DEVICE(0x8086, 0x3a6e),
2465           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2466         /* Generic Intel */
2467         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2468           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2469           .class_mask = 0xffffff,
2470           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2471         /* ATI SB 450/600/700/800/900 */
2472         { PCI_DEVICE(0x1002, 0x437b),
2473           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2474         { PCI_DEVICE(0x1002, 0x4383),
2475           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2476         /* AMD Hudson */
2477         { PCI_DEVICE(0x1022, 0x780d),
2478           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2479         /* AMD Stoney */
2480         { PCI_DEVICE(0x1022, 0x157a),
2481           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2482                          AZX_DCAPS_PM_RUNTIME },
2483         /* AMD Raven */
2484         { PCI_DEVICE(0x1022, 0x15e3),
2485           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2486                          AZX_DCAPS_PM_RUNTIME },
2487         /* ATI HDMI */
2488         { PCI_DEVICE(0x1002, 0x0002),
2489           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2490         { PCI_DEVICE(0x1002, 0x1308),
2491           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2492         { PCI_DEVICE(0x1002, 0x157a),
2493           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2494         { PCI_DEVICE(0x1002, 0x15b3),
2495           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2496         { PCI_DEVICE(0x1002, 0x793b),
2497           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498         { PCI_DEVICE(0x1002, 0x7919),
2499           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500         { PCI_DEVICE(0x1002, 0x960f),
2501           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502         { PCI_DEVICE(0x1002, 0x970f),
2503           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504         { PCI_DEVICE(0x1002, 0x9840),
2505           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2506         { PCI_DEVICE(0x1002, 0xaa00),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0xaa08),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0xaa10),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0xaa18),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0xaa20),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa28),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa30),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa38),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa40),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa48),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa50),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa58),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa60),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa68),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa80),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa88),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa90),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa98),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0x9902),
2543           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544         { PCI_DEVICE(0x1002, 0xaaa0),
2545           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2546         { PCI_DEVICE(0x1002, 0xaaa8),
2547           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2548         { PCI_DEVICE(0x1002, 0xaab0),
2549           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2550         { PCI_DEVICE(0x1002, 0xaac0),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaac8),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaad8),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaae8),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaae0),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaaf0),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         /* VIA VT8251/VT8237A */
2563         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2564         /* VIA GFX VT7122/VX900 */
2565         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2566         /* VIA GFX VT6122/VX11 */
2567         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2568         /* SIS966 */
2569         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2570         /* ULI M5461 */
2571         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2572         /* NVIDIA MCP */
2573         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2574           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2575           .class_mask = 0xffffff,
2576           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2577         /* Teradici */
2578         { PCI_DEVICE(0x6549, 0x1200),
2579           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2580         { PCI_DEVICE(0x6549, 0x2200),
2581           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2582         /* Creative X-Fi (CA0110-IBG) */
2583         /* CTHDA chips */
2584         { PCI_DEVICE(0x1102, 0x0010),
2585           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2586         { PCI_DEVICE(0x1102, 0x0012),
2587           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2588 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2589         /* the following entry conflicts with snd-ctxfi driver,
2590          * as ctxfi driver mutates from HD-audio to native mode with
2591          * a special command sequence.
2592          */
2593         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2594           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2595           .class_mask = 0xffffff,
2596           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2597           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2598 #else
2599         /* this entry seems still valid -- i.e. without emu20kx chip */
2600         { PCI_DEVICE(0x1102, 0x0009),
2601           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2602           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2603 #endif
2604         /* CM8888 */
2605         { PCI_DEVICE(0x13f6, 0x5011),
2606           .driver_data = AZX_DRIVER_CMEDIA |
2607           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2608         /* Vortex86MX */
2609         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2610         /* VMware HDAudio */
2611         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2612         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2613         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2614           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2615           .class_mask = 0xffffff,
2616           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2617         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2618           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2619           .class_mask = 0xffffff,
2620           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2621         { 0, }
2622 };
2623 MODULE_DEVICE_TABLE(pci, azx_ids);
2624
2625 /* pci_driver definition */
2626 static struct pci_driver azx_driver = {
2627         .name = KBUILD_MODNAME,
2628         .id_table = azx_ids,
2629         .probe = azx_probe,
2630         .remove = azx_remove,
2631         .shutdown = azx_shutdown,
2632         .driver = {
2633                 .pm = AZX_PM_OPS,
2634         },
2635 };
2636
2637 module_pci_driver(azx_driver);