sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include <sound/hda_codec.h>
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175 static int skl_pci_binding;
 176 module_param_named(pci_binding, skl_pci_binding, int, 0444);
 177 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
 178
 179 #ifdef CONFIG_PM
 180 static int param_set_xint(const char *val, const struct kernel_param *kp);
 181 static const struct kernel_param_ops param_ops_xint = {
 182         .set = param_set_xint,
 183         .get = param_get_int,
 184 };
 185 #define param_check_xint param_check_int
 186
 187 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 188 module_param(power_save, xint, 0644);
 189 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 190                  "(in second, 0 = disable).");
 191
 192 static bool pm_blacklist = true;
 193 module_param(pm_blacklist, bool, 0644);
 194 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 195
 196 /* reset the HD-audio controller in power save mode.
 197  * this may give more power-saving, but will take longer time to
 198  * wake up.
 199  */
 200 static bool power_save_controller = 1;
 201 module_param(power_save_controller, bool, 0644);
 202 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 203 #else
 204 #define power_save      0
 205 #endif /* CONFIG_PM */
 206
 207 static int align_buffer_size = -1;
 208 module_param(align_buffer_size, bint, 0644);
 209 MODULE_PARM_DESC(align_buffer_size,
 210                 "Force buffer and period sizes to be multiple of 128 bytes.");
 211
 212 #ifdef CONFIG_X86
 213 static int hda_snoop = -1;
 214 module_param_named(snoop, hda_snoop, bint, 0444);
 215 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 216 #else
 217 #define hda_snoop               true
 218 #endif
 219
 220
 221 MODULE_LICENSE("GPL");
 222 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 223                          "{Intel, ICH6M},"
 224                          "{Intel, ICH7},"
 225                          "{Intel, ESB2},"
 226                          "{Intel, ICH8},"
 227                          "{Intel, ICH9},"
 228                          "{Intel, ICH10},"
 229                          "{Intel, PCH},"
 230                          "{Intel, CPT},"
 231                          "{Intel, PPT},"
 232                          "{Intel, LPT},"
 233                          "{Intel, LPT_LP},"
 234                          "{Intel, WPT_LP},"
 235                          "{Intel, SPT},"
 236                          "{Intel, SPT_LP},"
 237                          "{Intel, HPT},"
 238                          "{Intel, PBG},"
 239                          "{Intel, SCH},"
 240                          "{ATI, SB450},"
 241                          "{ATI, SB600},"
 242                          "{ATI, RS600},"
 243                          "{ATI, RS690},"
 244                          "{ATI, RS780},"
 245                          "{ATI, R600},"
 246                          "{ATI, RV630},"
 247                          "{ATI, RV610},"
 248                          "{ATI, RV670},"
 249                          "{ATI, RV635},"
 250                          "{ATI, RV620},"
 251                          "{ATI, RV770},"
 252                          "{VIA, VT8251},"
 253                          "{VIA, VT8237A},"
 254                          "{SiS, SIS966},"
 255                          "{ULI, M5461}}");
 256 MODULE_DESCRIPTION("Intel HDA driver");
 257
 258 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 259 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 260 #define SUPPORT_VGA_SWITCHEROO
 261 #endif
 262 #endif
 263
 264
 265 /*
 266  */
 267
 268 /* driver types */
 269 enum {
 270         AZX_DRIVER_ICH,
 271         AZX_DRIVER_PCH,
 272         AZX_DRIVER_SCH,
 273         AZX_DRIVER_SKL,
 274         AZX_DRIVER_HDMI,
 275         AZX_DRIVER_ATI,
 276         AZX_DRIVER_ATIHDMI,
 277         AZX_DRIVER_ATIHDMI_NS,
 278         AZX_DRIVER_VIA,
 279         AZX_DRIVER_SIS,
 280         AZX_DRIVER_ULI,
 281         AZX_DRIVER_NVIDIA,
 282         AZX_DRIVER_TERA,
 283         AZX_DRIVER_CTX,
 284         AZX_DRIVER_CTHDA,
 285         AZX_DRIVER_CMEDIA,
 286         AZX_DRIVER_GENERIC,
 287         AZX_NUM_DRIVERS, /* keep this as last entry */
 288 };
 289
 290 #define azx_get_snoop_type(chip) \
 291         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 292 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 293
 294 /* quirks for old Intel chipsets */
 295 #define AZX_DCAPS_INTEL_ICH \
 296         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 297
 298 /* quirks for Intel PCH */
 299 #define AZX_DCAPS_INTEL_PCH_BASE \
 300         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 301          AZX_DCAPS_SNOOP_TYPE(SCH))
 302
 303 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 304 #define AZX_DCAPS_INTEL_PCH_NOPM \
 305         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 306
 307 /* PCH for HSW/BDW; with runtime PM */
 308 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 309 #define AZX_DCAPS_INTEL_PCH \
 310         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 311
 312 /* HSW HDMI */
 313 #define AZX_DCAPS_INTEL_HASWELL \
 314         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 315          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 316          AZX_DCAPS_SNOOP_TYPE(SCH))
 317
 318 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 319 #define AZX_DCAPS_INTEL_BROADWELL \
 320         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 321          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 322          AZX_DCAPS_SNOOP_TYPE(SCH))
 323
 324 #define AZX_DCAPS_INTEL_BAYTRAIL \
 325         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 326
 327 #define AZX_DCAPS_INTEL_BRASWELL \
 328         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 329          AZX_DCAPS_I915_COMPONENT)
 330
 331 #define AZX_DCAPS_INTEL_SKYLAKE \
 332         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 333          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 334
 335 #define AZX_DCAPS_INTEL_BROXTON \
 336         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 337          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 338
 339 /* quirks for ATI SB / AMD Hudson */
 340 #define AZX_DCAPS_PRESET_ATI_SB \
 341         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 342          AZX_DCAPS_SNOOP_TYPE(ATI))
 343
 344 /* quirks for ATI/AMD HDMI */
 345 #define AZX_DCAPS_PRESET_ATI_HDMI \
 346         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 347          AZX_DCAPS_NO_MSI64)
 348
 349 /* quirks for ATI HDMI with snoop off */
 350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 351         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 352
 353 /* quirks for Nvidia */
 354 #define AZX_DCAPS_PRESET_NVIDIA \
 355         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 356          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 357
 358 #define AZX_DCAPS_PRESET_CTHDA \
 359         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 360          AZX_DCAPS_NO_64BIT |\
 361          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 362
 363 #define AZX_DCAPS_INTEL_DSP_DETECTION(conf) (IS_ENABLED(CONFIG_SND_HDA_INTEL_DSP_DETECTION_##conf) ? AZX_DCAPS_INTEL_SHARED : 0)
 364 /*
 365  * vga_switcheroo support
 366  */
 367 #ifdef SUPPORT_VGA_SWITCHEROO
 368 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 369 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 370 #else
 371 #define use_vga_switcheroo(chip)        0
 372 #define needs_eld_notify_link(chip)     false
 373 #endif
 374
 375 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 376                                         ((pci)->device == 0x0c0c) || \
 377                                         ((pci)->device == 0x0d0c) || \
 378                                         ((pci)->device == 0x160c))
 379
 380 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 381 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 382
 383 static char *driver_short_names[] = {
 384         [AZX_DRIVER_ICH] = "HDA Intel",
 385         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 386         [AZX_DRIVER_SCH] = "HDA Intel MID",
 387         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 388         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 389         [AZX_DRIVER_ATI] = "HDA ATI SB",
 390         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 391         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 392         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 393         [AZX_DRIVER_SIS] = "HDA SIS966",
 394         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 395         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 396         [AZX_DRIVER_TERA] = "HDA Teradici",
 397         [AZX_DRIVER_CTX] = "HDA Creative",
 398         [AZX_DRIVER_CTHDA] = "HDA Creative",
 399         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 400         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 401 };
 402
 403 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 404 static void set_default_power_save(struct azx *chip);
 405
 406 /*
 407  * initialize the PCI registers
 408  */
 409 /* update bits in a PCI register byte */
 410 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 411                             unsigned char mask, unsigned char val)
 412 {
 413         unsigned char data;
 414
 415         pci_read_config_byte(pci, reg, &data);
 416         data &= ~mask;
 417         data |= (val & mask);
 418         pci_write_config_byte(pci, reg, data);
 419 }
 420
 421 static void azx_init_pci(struct azx *chip)
 422 {
 423         int snoop_type = azx_get_snoop_type(chip);
 424
 425         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 426          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 427          * Ensuring these bits are 0 clears playback static on some HD Audio
 428          * codecs.
 429          * The PCI register TCSEL is defined in the Intel manuals.
 430          */
 431         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 432                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 433                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 434         }
 435
 436         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 437          * we need to enable snoop.
 438          */
 439         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 440                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 441                         azx_snoop(chip));
 442                 update_pci_byte(chip->pci,
 443                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 444                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 445         }
 446
 447         /* For NVIDIA HDA, enable snoop */
 448         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 449                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 450                         azx_snoop(chip));
 451                 update_pci_byte(chip->pci,
 452                                 NVIDIA_HDA_TRANSREG_ADDR,
 453                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 454                 update_pci_byte(chip->pci,
 455                                 NVIDIA_HDA_ISTRM_COH,
 456                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 457                 update_pci_byte(chip->pci,
 458                                 NVIDIA_HDA_OSTRM_COH,
 459                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 460         }
 461
 462         /* Enable SCH/PCH snoop if needed */
 463         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 464                 unsigned short snoop;
 465                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 466                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 467                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 468                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 469                         if (!azx_snoop(chip))
 470                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 471                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 472                         pci_read_config_word(chip->pci,
 473                                 INTEL_SCH_HDA_DEVC, &snoop);
 474                 }
 475                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 476                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 477                         "Disabled" : "Enabled");
 478         }
 479 }
 480
 481 /*
 482  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 483  * and makes an audio stream sensitive to system latencies when
 484  * 24/32 bits are playing.
 485  * Adjusting threshold of DMA fifo to force the DMA request
 486  * sooner to improve latency tolerance at the expense of power.
 487  */
 488 static void bxt_reduce_dma_latency(struct azx *chip)
 489 {
 490         u32 val;
 491
 492         val = azx_readl(chip, VS_EM4L);
 493         val &= (0x3 << 20);
 494         azx_writel(chip, VS_EM4L, val);
 495 }
 496
 497 /*
 498  * ML_LCAP bits:
 499  *  bit 0: 6 MHz Supported
 500  *  bit 1: 12 MHz Supported
 501  *  bit 2: 24 MHz Supported
 502  *  bit 3: 48 MHz Supported
 503  *  bit 4: 96 MHz Supported
 504  *  bit 5: 192 MHz Supported
 505  */
 506 static int intel_get_lctl_scf(struct azx *chip)
 507 {
 508         struct hdac_bus *bus = azx_bus(chip);
 509         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 510         u32 val, t;
 511         int i;
 512
 513         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 514
 515         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 516                 t = preferred_bits[i];
 517                 if (val & (1 << t))
 518                         return t;
 519         }
 520
 521         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 522         return 0;
 523 }
 524
 525 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 526 {
 527         struct hdac_bus *bus = azx_bus(chip);
 528         u32 val;
 529         int timeout;
 530
 531         /*
 532          * the codecs are sharing the first link setting by default
 533          * If other links are enabled for stream, they need similar fix
 534          */
 535         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 536         val &= ~AZX_MLCTL_SPA;
 537         val |= state << AZX_MLCTL_SPA_SHIFT;
 538         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 539         /* wait for CPA */
 540         timeout = 50;
 541         while (timeout) {
 542                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 543                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 544                         return 0;
 545                 timeout--;
 546                 udelay(10);
 547         }
 548
 549         return -1;
 550 }
 551
 552 static void intel_init_lctl(struct azx *chip)
 553 {
 554         struct hdac_bus *bus = azx_bus(chip);
 555         u32 val;
 556         int ret;
 557
 558         /* 0. check lctl register value is correct or not */
 559         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 560         /* if SCF is already set, let's use it */
 561         if ((val & ML_LCTL_SCF_MASK) != 0)
 562                 return;
 563
 564         /*
 565          * Before operating on SPA, CPA must match SPA.
 566          * Any deviation may result in undefined behavior.
 567          */
 568         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 569                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 570                 return;
 571
 572         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 573         ret = intel_ml_lctl_set_power(chip, 0);
 574         udelay(100);
 575         if (ret)
 576                 goto set_spa;
 577
 578         /* 2. update SCF to select a properly audio clock*/
 579         val &= ~ML_LCTL_SCF_MASK;
 580         val |= intel_get_lctl_scf(chip);
 581         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 582
 583 set_spa:
 584         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 585         intel_ml_lctl_set_power(chip, 1);
 586         udelay(100);
 587 }
 588
 589 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 590 {
 591         struct hdac_bus *bus = azx_bus(chip);
 592         struct pci_dev *pci = chip->pci;
 593         u32 val;
 594
 595         snd_hdac_set_codec_wakeup(bus, true);
 596         if (chip->driver_type == AZX_DRIVER_SKL) {
 597                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 598                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 599                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 600         }
 601         azx_init_chip(chip, full_reset);
 602         if (chip->driver_type == AZX_DRIVER_SKL) {
 603                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 604                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 605                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 606         }
 607
 608         snd_hdac_set_codec_wakeup(bus, false);
 609
 610         /* reduce dma latency to avoid noise */
 611         if (IS_BXT(pci))
 612                 bxt_reduce_dma_latency(chip);
 613
 614         if (bus->mlcap != NULL)
 615                 intel_init_lctl(chip);
 616 }
 617
 618 /* calculate runtime delay from LPIB */
 619 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 620                                    unsigned int pos)
 621 {
 622         struct snd_pcm_substream *substream = azx_dev->core.substream;
 623         int stream = substream->stream;
 624         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 625         int delay;
 626
 627         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 628                 delay = pos - lpib_pos;
 629         else
 630                 delay = lpib_pos - pos;
 631         if (delay < 0) {
 632                 if (delay >= azx_dev->core.delay_negative_threshold)
 633                         delay = 0;
 634                 else
 635                         delay += azx_dev->core.bufsize;
 636         }
 637
 638         if (delay >= azx_dev->core.period_bytes) {
 639                 dev_info(chip->card->dev,
 640                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 641                          delay, azx_dev->core.period_bytes);
 642                 delay = 0;
 643                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 644                 chip->get_delay[stream] = NULL;
 645         }
 646
 647         return bytes_to_frames(substream->runtime, delay);
 648 }
 649
 650 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 651
 652 /* called from IRQ */
 653 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 654 {
 655         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 656         int ok;
 657
 658         ok = azx_position_ok(chip, azx_dev);
 659         if (ok == 1) {
 660                 azx_dev->irq_pending = 0;
 661                 return ok;
 662         } else if (ok == 0) {
 663                 /* bogus IRQ, process it later */
 664                 azx_dev->irq_pending = 1;
 665                 schedule_work(&hda->irq_pending_work);
 666         }
 667         return 0;
 668 }
 669
 670 #define display_power(chip, enable) \
 671         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 672
 673 /*
 674  * Check whether the current DMA position is acceptable for updating
 675  * periods.  Returns non-zero if it's OK.
 676  *
 677  * Many HD-audio controllers appear pretty inaccurate about
 678  * the update-IRQ timing.  The IRQ is issued before actually the
 679  * data is processed.  So, we need to process it afterwords in a
 680  * workqueue.
 681  */
 682 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 683 {
 684         struct snd_pcm_substream *substream = azx_dev->core.substream;
 685         int stream = substream->stream;
 686         u32 wallclk;
 687         unsigned int pos;
 688
 689         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 690         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 691                 return -1;      /* bogus (too early) interrupt */
 692
 693         if (chip->get_position[stream])
 694                 pos = chip->get_position[stream](chip, azx_dev);
 695         else { /* use the position buffer as default */
 696                 pos = azx_get_pos_posbuf(chip, azx_dev);
 697                 if (!pos || pos == (u32)-1) {
 698                         dev_info(chip->card->dev,
 699                                  "Invalid position buffer, using LPIB read method instead.\n");
 700                         chip->get_position[stream] = azx_get_pos_lpib;
 701                         if (chip->get_position[0] == azx_get_pos_lpib &&
 702                             chip->get_position[1] == azx_get_pos_lpib)
 703                                 azx_bus(chip)->use_posbuf = false;
 704                         pos = azx_get_pos_lpib(chip, azx_dev);
 705                         chip->get_delay[stream] = NULL;
 706                 } else {
 707                         chip->get_position[stream] = azx_get_pos_posbuf;
 708                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 709                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 710                 }
 711         }
 712
 713         if (pos >= azx_dev->core.bufsize)
 714                 pos = 0;
 715
 716         if (WARN_ONCE(!azx_dev->core.period_bytes,
 717                       "hda-intel: zero azx_dev->period_bytes"))
 718                 return -1; /* this shouldn't happen! */
 719         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 720             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 721                 /* NG - it's below the first next period boundary */
 722                 return chip->bdl_pos_adj ? 0 : -1;
 723         azx_dev->core.start_wallclk += wallclk;
 724         return 1; /* OK, it's fine */
 725 }
 726
 727 /*
 728  * The work for pending PCM period updates.
 729  */
 730 static void azx_irq_pending_work(struct work_struct *work)
 731 {
 732         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 733         struct azx *chip = &hda->chip;
 734         struct hdac_bus *bus = azx_bus(chip);
 735         struct hdac_stream *s;
 736         int pending, ok;
 737
 738         if (!hda->irq_pending_warned) {
 739                 dev_info(chip->card->dev,
 740                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 741                          chip->card->number);
 742                 hda->irq_pending_warned = 1;
 743         }
 744
 745         for (;;) {
 746                 pending = 0;
 747                 spin_lock_irq(&bus->reg_lock);
 748                 list_for_each_entry(s, &bus->stream_list, list) {
 749                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 750                         if (!azx_dev->irq_pending ||
 751                             !s->substream ||
 752                             !s->running)
 753                                 continue;
 754                         ok = azx_position_ok(chip, azx_dev);
 755                         if (ok > 0) {
 756                                 azx_dev->irq_pending = 0;
 757                                 spin_unlock(&bus->reg_lock);
 758                                 snd_pcm_period_elapsed(s->substream);
 759                                 spin_lock(&bus->reg_lock);
 760                         } else if (ok < 0) {
 761                                 pending = 0;    /* too early */
 762                         } else
 763                                 pending++;
 764                 }
 765                 spin_unlock_irq(&bus->reg_lock);
 766                 if (!pending)
 767                         return;
 768                 msleep(1);
 769         }
 770 }
 771
 772 /* clear irq_pending flags and assure no on-going workq */
 773 static void azx_clear_irq_pending(struct azx *chip)
 774 {
 775         struct hdac_bus *bus = azx_bus(chip);
 776         struct hdac_stream *s;
 777
 778         spin_lock_irq(&bus->reg_lock);
 779         list_for_each_entry(s, &bus->stream_list, list) {
 780                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 781                 azx_dev->irq_pending = 0;
 782         }
 783         spin_unlock_irq(&bus->reg_lock);
 784 }
 785
 786 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 787 {
 788         struct hdac_bus *bus = azx_bus(chip);
 789
 790         if (request_irq(chip->pci->irq, azx_interrupt,
 791                         chip->msi ? 0 : IRQF_SHARED,
 792                         chip->card->irq_descr, chip)) {
 793                 dev_err(chip->card->dev,
 794                         "unable to grab IRQ %d, disabling device\n",
 795                         chip->pci->irq);
 796                 if (do_disconnect)
 797                         snd_card_disconnect(chip->card);
 798                 return -1;
 799         }
 800         bus->irq = chip->pci->irq;
 801         pci_intx(chip->pci, !chip->msi);
 802         return 0;
 803 }
 804
 805 /* get the current DMA position with correction on VIA chips */
 806 static unsigned int azx_via_get_position(struct azx *chip,
 807                                          struct azx_dev *azx_dev)
 808 {
 809         unsigned int link_pos, mini_pos, bound_pos;
 810         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 811         unsigned int fifo_size;
 812
 813         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 814         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 815                 /* Playback, no problem using link position */
 816                 return link_pos;
 817         }
 818
 819         /* Capture */
 820         /* For new chipset,
 821          * use mod to get the DMA position just like old chipset
 822          */
 823         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 824         mod_dma_pos %= azx_dev->core.period_bytes;
 825
 826         /* azx_dev->fifo_size can't get FIFO size of in stream.
 827          * Get from base address + offset.
 828          */
 829         fifo_size = readw(azx_bus(chip)->remap_addr +
 830                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 831
 832         if (azx_dev->insufficient) {
 833                 /* Link position never gather than FIFO size */
 834                 if (link_pos <= fifo_size)
 835                         return 0;
 836
 837                 azx_dev->insufficient = 0;
 838         }
 839
 840         if (link_pos <= fifo_size)
 841                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 842         else
 843                 mini_pos = link_pos - fifo_size;
 844
 845         /* Find nearest previous boudary */
 846         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 847         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 848         if (mod_link_pos >= fifo_size)
 849                 bound_pos = link_pos - mod_link_pos;
 850         else if (mod_dma_pos >= mod_mini_pos)
 851                 bound_pos = mini_pos - mod_mini_pos;
 852         else {
 853                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 854                 if (bound_pos >= azx_dev->core.bufsize)
 855                         bound_pos = 0;
 856         }
 857
 858         /* Calculate real DMA position we want */
 859         return bound_pos + mod_dma_pos;
 860 }
 861
 862 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 863                                          struct azx_dev *azx_dev)
 864 {
 865         return _snd_hdac_chip_readl(azx_bus(chip),
 866                                     AZX_REG_VS_SDXDPIB_XBASE +
 867                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 868                                      azx_dev->core.index));
 869 }
 870
 871 /* get the current DMA position with correction on SKL+ chips */
 872 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 873 {
 874         /* DPIB register gives a more accurate position for playback */
 875         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 876                 return azx_skl_get_dpib_pos(chip, azx_dev);
 877
 878         /* For capture, we need to read posbuf, but it requires a delay
 879          * for the possible boundary overlap; the read of DPIB fetches the
 880          * actual posbuf
 881          */
 882         udelay(20);
 883         azx_skl_get_dpib_pos(chip, azx_dev);
 884         return azx_get_pos_posbuf(chip, azx_dev);
 885 }
 886
 887 #ifdef CONFIG_PM
 888 static DEFINE_MUTEX(card_list_lock);
 889 static LIST_HEAD(card_list);
 890
 891 static void azx_add_card_list(struct azx *chip)
 892 {
 893         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 894         mutex_lock(&card_list_lock);
 895         list_add(&hda->list, &card_list);
 896         mutex_unlock(&card_list_lock);
 897 }
 898
 899 static void azx_del_card_list(struct azx *chip)
 900 {
 901         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 902         mutex_lock(&card_list_lock);
 903         list_del_init(&hda->list);
 904         mutex_unlock(&card_list_lock);
 905 }
 906
 907 /* trigger power-save check at writing parameter */
 908 static int param_set_xint(const char *val, const struct kernel_param *kp)
 909 {
 910         struct hda_intel *hda;
 911         struct azx *chip;
 912         int prev = power_save;
 913         int ret = param_set_int(val, kp);
 914
 915         if (ret || prev == power_save)
 916                 return ret;
 917
 918         mutex_lock(&card_list_lock);
 919         list_for_each_entry(hda, &card_list, list) {
 920                 chip = &hda->chip;
 921                 if (!hda->probe_continued || chip->disabled)
 922                         continue;
 923                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 924         }
 925         mutex_unlock(&card_list_lock);
 926         return 0;
 927 }
 928
 929 /*
 930  * power management
 931  */
 932 static bool azx_is_pm_ready(struct snd_card *card)
 933 {
 934         struct azx *chip;
 935         struct hda_intel *hda;
 936
 937         if (!card)
 938                 return false;
 939         chip = card->private_data;
 940         hda = container_of(chip, struct hda_intel, chip);
 941         if (chip->disabled || hda->init_failed || !chip->running)
 942                 return false;
 943         return true;
 944 }
 945
 946 static void __azx_runtime_suspend(struct azx *chip)
 947 {
 948         azx_stop_chip(chip);
 949         azx_enter_link_reset(chip);
 950         azx_clear_irq_pending(chip);
 951         display_power(chip, false);
 952 }
 953
 954 static void __azx_runtime_resume(struct azx *chip)
 955 {
 956         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 957         struct hdac_bus *bus = azx_bus(chip);
 958         struct hda_codec *codec;
 959         int status;
 960
 961         display_power(chip, true);
 962         if (hda->need_i915_power)
 963                 snd_hdac_i915_set_bclk(bus);
 964
 965         /* Read STATESTS before controller reset */
 966         status = azx_readw(chip, STATESTS);
 967
 968         azx_init_pci(chip);
 969         hda_intel_init_chip(chip, true);
 970
 971         if (status) {
 972                 list_for_each_codec(codec, &chip->bus)
 973                         if (status & (1 << codec->addr))
 974                                 schedule_delayed_work(&codec->jackpoll_work,
 975                                                       codec->jackpoll_interval);
 976         }
 977
 978         /* power down again for link-controlled chips */
 979         if (!hda->need_i915_power)
 980                 display_power(chip, false);
 981 }
 982
 983 #ifdef CONFIG_PM_SLEEP
 984 static int azx_suspend(struct device *dev)
 985 {
 986         struct snd_card *card = dev_get_drvdata(dev);
 987         struct azx *chip;
 988         struct hdac_bus *bus;
 989
 990         if (!azx_is_pm_ready(card))
 991                 return 0;
 992
 993         chip = card->private_data;
 994         bus = azx_bus(chip);
 995         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 996         __azx_runtime_suspend(chip);
 997         if (bus->irq >= 0) {
 998                 free_irq(bus->irq, chip);
 999                 bus->irq = -1;
1000         }
1001
1002         if (chip->msi)
1003                 pci_disable_msi(chip->pci);
1004
1005         trace_azx_suspend(chip);
1006         return 0;
1007 }
1008
1009 static int azx_resume(struct device *dev)
1010 {
1011         struct snd_card *card = dev_get_drvdata(dev);
1012         struct azx *chip;
1013
1014         if (!azx_is_pm_ready(card))
1015                 return 0;
1016
1017         chip = card->private_data;
1018         if (chip->msi)
1019                 if (pci_enable_msi(chip->pci) < 0)
1020                         chip->msi = 0;
1021         if (azx_acquire_irq(chip, 1) < 0)
1022                 return -EIO;
1023         __azx_runtime_resume(chip);
1024         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1025
1026         trace_azx_resume(chip);
1027         return 0;
1028 }
1029
1030 /* put codec down to D3 at hibernation for Intel SKL+;
1031  * otherwise BIOS may still access the codec and screw up the driver
1032  */
1033 static int azx_freeze_noirq(struct device *dev)
1034 {
1035         struct snd_card *card = dev_get_drvdata(dev);
1036         struct azx *chip = card->private_data;
1037         struct pci_dev *pci = to_pci_dev(dev);
1038
1039         if (chip->driver_type == AZX_DRIVER_SKL)
1040                 pci_set_power_state(pci, PCI_D3hot);
1041
1042         return 0;
1043 }
1044
1045 static int azx_thaw_noirq(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip = card->private_data;
1049         struct pci_dev *pci = to_pci_dev(dev);
1050
1051         if (chip->driver_type == AZX_DRIVER_SKL)
1052                 pci_set_power_state(pci, PCI_D0);
1053
1054         return 0;
1055 }
1056 #endif /* CONFIG_PM_SLEEP */
1057
1058 static int azx_runtime_suspend(struct device *dev)
1059 {
1060         struct snd_card *card = dev_get_drvdata(dev);
1061         struct azx *chip;
1062
1063         if (!azx_is_pm_ready(card))
1064                 return 0;
1065         chip = card->private_data;
1066         if (!azx_has_pm_runtime(chip))
1067                 return 0;
1068
1069         /* enable controller wake up event */
1070         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1071                   STATESTS_INT_MASK);
1072
1073         __azx_runtime_suspend(chip);
1074         trace_azx_runtime_suspend(chip);
1075         return 0;
1076 }
1077
1078 static int azx_runtime_resume(struct device *dev)
1079 {
1080         struct snd_card *card = dev_get_drvdata(dev);
1081         struct azx *chip;
1082
1083         if (!azx_is_pm_ready(card))
1084                 return 0;
1085         chip = card->private_data;
1086         if (!azx_has_pm_runtime(chip))
1087                 return 0;
1088         __azx_runtime_resume(chip);
1089
1090         /* disable controller Wake Up event*/
1091         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1092                         ~STATESTS_INT_MASK);
1093
1094         trace_azx_runtime_resume(chip);
1095         return 0;
1096 }
1097
1098 static int azx_runtime_idle(struct device *dev)
1099 {
1100         struct snd_card *card = dev_get_drvdata(dev);
1101         struct azx *chip;
1102         struct hda_intel *hda;
1103
1104         if (!card)
1105                 return 0;
1106
1107         chip = card->private_data;
1108         hda = container_of(chip, struct hda_intel, chip);
1109         if (chip->disabled || hda->init_failed)
1110                 return 0;
1111
1112         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1113             azx_bus(chip)->codec_powered || !chip->running)
1114                 return -EBUSY;
1115
1116         /* ELD notification gets broken when HD-audio bus is off */
1117         if (needs_eld_notify_link(hda))
1118                 return -EBUSY;
1119
1120         return 0;
1121 }
1122
1123 static const struct dev_pm_ops azx_pm = {
1124         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1125 #ifdef CONFIG_PM_SLEEP
1126         .freeze_noirq = azx_freeze_noirq,
1127         .thaw_noirq = azx_thaw_noirq,
1128 #endif
1129         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1130 };
1131
1132 #define AZX_PM_OPS      &azx_pm
1133 #else
1134 #define azx_add_card_list(chip) /* NOP */
1135 #define azx_del_card_list(chip) /* NOP */
1136 #define AZX_PM_OPS      NULL
1137 #endif /* CONFIG_PM */
1138
1139
1140 static int azx_probe_continue(struct azx *chip);
1141
1142 #ifdef SUPPORT_VGA_SWITCHEROO
1143 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1144
1145 static void azx_vs_set_state(struct pci_dev *pci,
1146                              enum vga_switcheroo_state state)
1147 {
1148         struct snd_card *card = pci_get_drvdata(pci);
1149         struct azx *chip = card->private_data;
1150         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1151         struct hda_codec *codec;
1152         bool disabled;
1153
1154         wait_for_completion(&hda->probe_wait);
1155         if (hda->init_failed)
1156                 return;
1157
1158         disabled = (state == VGA_SWITCHEROO_OFF);
1159         if (chip->disabled == disabled)
1160                 return;
1161
1162         if (!hda->probe_continued) {
1163                 chip->disabled = disabled;
1164                 if (!disabled) {
1165                         dev_info(chip->card->dev,
1166                                  "Start delayed initialization\n");
1167                         if (azx_probe_continue(chip) < 0) {
1168                                 dev_err(chip->card->dev, "initialization error\n");
1169                                 hda->init_failed = true;
1170                         }
1171                 }
1172         } else {
1173                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1174                          disabled ? "Disabling" : "Enabling");
1175                 if (disabled) {
1176                         list_for_each_codec(codec, &chip->bus) {
1177                                 pm_runtime_suspend(hda_codec_dev(codec));
1178                                 pm_runtime_disable(hda_codec_dev(codec));
1179                         }
1180                         pm_runtime_suspend(card->dev);
1181                         pm_runtime_disable(card->dev);
1182                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1183                          * however we have no ACPI handle, so pci/acpi can't put us there,
1184                          * put ourselves there */
1185                         pci->current_state = PCI_D3cold;
1186                         chip->disabled = true;
1187                         if (snd_hda_lock_devices(&chip->bus))
1188                                 dev_warn(chip->card->dev,
1189                                          "Cannot lock devices!\n");
1190                 } else {
1191                         snd_hda_unlock_devices(&chip->bus);
1192                         chip->disabled = false;
1193                         pm_runtime_enable(card->dev);
1194                         list_for_each_codec(codec, &chip->bus) {
1195                                 pm_runtime_enable(hda_codec_dev(codec));
1196                                 pm_runtime_resume(hda_codec_dev(codec));
1197                         }
1198                 }
1199         }
1200 }
1201
1202 static bool azx_vs_can_switch(struct pci_dev *pci)
1203 {
1204         struct snd_card *card = pci_get_drvdata(pci);
1205         struct azx *chip = card->private_data;
1206         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1207
1208         wait_for_completion(&hda->probe_wait);
1209         if (hda->init_failed)
1210                 return false;
1211         if (chip->disabled || !hda->probe_continued)
1212                 return true;
1213         if (snd_hda_lock_devices(&chip->bus))
1214                 return false;
1215         snd_hda_unlock_devices(&chip->bus);
1216         return true;
1217 }
1218
1219 /*
1220  * The discrete GPU cannot power down unless the HDA controller runtime
1221  * suspends, so activate runtime PM on codecs even if power_save == 0.
1222  */
1223 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1224 {
1225         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1226         struct hda_codec *codec;
1227
1228         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1229                 list_for_each_codec(codec, &chip->bus)
1230                         codec->auto_runtime_pm = 1;
1231                 /* reset the power save setup */
1232                 if (chip->running)
1233                         set_default_power_save(chip);
1234         }
1235 }
1236
1237 static void azx_vs_gpu_bound(struct pci_dev *pci,
1238                              enum vga_switcheroo_client_id client_id)
1239 {
1240         struct snd_card *card = pci_get_drvdata(pci);
1241         struct azx *chip = card->private_data;
1242         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1243
1244         if (client_id == VGA_SWITCHEROO_DIS)
1245                 hda->need_eld_notify_link = 0;
1246         setup_vga_switcheroo_runtime_pm(chip);
1247 }
1248
1249 static void init_vga_switcheroo(struct azx *chip)
1250 {
1251         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1252         struct pci_dev *p = get_bound_vga(chip->pci);
1253         if (p) {
1254                 dev_info(chip->card->dev,
1255                          "Handle vga_switcheroo audio client\n");
1256                 hda->use_vga_switcheroo = 1;
1257                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1258                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1259                 pci_dev_put(p);
1260         }
1261 }
1262
1263 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1264         .set_gpu_state = azx_vs_set_state,
1265         .can_switch = azx_vs_can_switch,
1266         .gpu_bound = azx_vs_gpu_bound,
1267 };
1268
1269 static int register_vga_switcheroo(struct azx *chip)
1270 {
1271         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1272         struct pci_dev *p;
1273         int err;
1274
1275         if (!hda->use_vga_switcheroo)
1276                 return 0;
1277
1278         p = get_bound_vga(chip->pci);
1279         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1280         pci_dev_put(p);
1281
1282         if (err < 0)
1283                 return err;
1284         hda->vga_switcheroo_registered = 1;
1285
1286         return 0;
1287 }
1288 #else
1289 #define init_vga_switcheroo(chip)               /* NOP */
1290 #define register_vga_switcheroo(chip)           0
1291 #define check_hdmi_disabled(pci)        false
1292 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1293 #endif /* SUPPORT_VGA_SWITCHER */
1294
1295 /*
1296  * destructor
1297  */
1298 static int azx_free(struct azx *chip)
1299 {
1300         struct pci_dev *pci = chip->pci;
1301         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1302         struct hdac_bus *bus = azx_bus(chip);
1303
1304         if (azx_has_pm_runtime(chip) && chip->running)
1305                 pm_runtime_get_noresume(&pci->dev);
1306         chip->running = 0;
1307
1308         azx_del_card_list(chip);
1309
1310         hda->init_failed = 1; /* to be sure */
1311         complete_all(&hda->probe_wait);
1312
1313         if (use_vga_switcheroo(hda)) {
1314                 if (chip->disabled && hda->probe_continued)
1315                         snd_hda_unlock_devices(&chip->bus);
1316                 if (hda->vga_switcheroo_registered)
1317                         vga_switcheroo_unregister_client(chip->pci);
1318         }
1319
1320         if (bus->chip_init) {
1321                 azx_clear_irq_pending(chip);
1322                 azx_stop_all_streams(chip);
1323                 azx_stop_chip(chip);
1324         }
1325
1326         if (bus->irq >= 0)
1327                 free_irq(bus->irq, (void*)chip);
1328         if (chip->msi)
1329                 pci_disable_msi(chip->pci);
1330         iounmap(bus->remap_addr);
1331
1332         azx_free_stream_pages(chip);
1333         azx_free_streams(chip);
1334         snd_hdac_bus_exit(bus);
1335
1336         if (chip->region_requested)
1337                 pci_release_regions(chip->pci);
1338
1339         pci_disable_device(chip->pci);
1340 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1341         release_firmware(chip->fw);
1342 #endif
1343         display_power(chip, false);
1344
1345         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1346                 snd_hdac_i915_exit(bus);
1347         kfree(hda);
1348
1349         return 0;
1350 }
1351
1352 static int azx_dev_disconnect(struct snd_device *device)
1353 {
1354         struct azx *chip = device->device_data;
1355
1356         chip->bus.shutdown = 1;
1357         return 0;
1358 }
1359
1360 static int azx_dev_free(struct snd_device *device)
1361 {
1362         return azx_free(device->device_data);
1363 }
1364
1365 #ifdef SUPPORT_VGA_SWITCHEROO
1366 /*
1367  * Check of disabled HDMI controller by vga_switcheroo
1368  */
1369 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1370 {
1371         struct pci_dev *p;
1372
1373         /* check only discrete GPU */
1374         switch (pci->vendor) {
1375         case PCI_VENDOR_ID_ATI:
1376         case PCI_VENDOR_ID_AMD:
1377         case PCI_VENDOR_ID_NVIDIA:
1378                 if (pci->devfn == 1) {
1379                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1380                                                         pci->bus->number, 0);
1381                         if (p) {
1382                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1383                                         return p;
1384                                 pci_dev_put(p);
1385                         }
1386                 }
1387                 break;
1388         }
1389         return NULL;
1390 }
1391
1392 static bool check_hdmi_disabled(struct pci_dev *pci)
1393 {
1394         bool vga_inactive = false;
1395         struct pci_dev *p = get_bound_vga(pci);
1396
1397         if (p) {
1398                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1399                         vga_inactive = true;
1400                 pci_dev_put(p);
1401         }
1402         return vga_inactive;
1403 }
1404 #endif /* SUPPORT_VGA_SWITCHEROO */
1405
1406 /*
1407  * white/black-listing for position_fix
1408  */
1409 static struct snd_pci_quirk position_fix_list[] = {
1410         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1411         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1412         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1413         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1414         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1415         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1416         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1417         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1418         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1419         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1420         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1421         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1422         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1423         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1424         {}
1425 };
1426
1427 static int check_position_fix(struct azx *chip, int fix)
1428 {
1429         const struct snd_pci_quirk *q;
1430
1431         switch (fix) {
1432         case POS_FIX_AUTO:
1433         case POS_FIX_LPIB:
1434         case POS_FIX_POSBUF:
1435         case POS_FIX_VIACOMBO:
1436         case POS_FIX_COMBO:
1437         case POS_FIX_SKL:
1438                 return fix;
1439         }
1440
1441         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1442         if (q) {
1443                 dev_info(chip->card->dev,
1444                          "position_fix set to %d for device %04x:%04x\n",
1445                          q->value, q->subvendor, q->subdevice);
1446                 return q->value;
1447         }
1448
1449         /* Check VIA/ATI HD Audio Controller exist */
1450         if (chip->driver_type == AZX_DRIVER_VIA) {
1451                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1452                 return POS_FIX_VIACOMBO;
1453         }
1454         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1455                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1456                 return POS_FIX_LPIB;
1457         }
1458         if (chip->driver_type == AZX_DRIVER_SKL) {
1459                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1460                 return POS_FIX_SKL;
1461         }
1462         return POS_FIX_AUTO;
1463 }
1464
1465 static void assign_position_fix(struct azx *chip, int fix)
1466 {
1467         static azx_get_pos_callback_t callbacks[] = {
1468                 [POS_FIX_AUTO] = NULL,
1469                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1470                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1471                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1472                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1473                 [POS_FIX_SKL] = azx_get_pos_skl,
1474         };
1475
1476         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1477
1478         /* combo mode uses LPIB only for playback */
1479         if (fix == POS_FIX_COMBO)
1480                 chip->get_position[1] = NULL;
1481
1482         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1483             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1484                 chip->get_delay[0] = chip->get_delay[1] =
1485                         azx_get_delay_from_lpib;
1486         }
1487
1488 }
1489
1490 /*
1491  * black-lists for probe_mask
1492  */
1493 static struct snd_pci_quirk probe_mask_list[] = {
1494         /* Thinkpad often breaks the controller communication when accessing
1495          * to the non-working (or non-existing) modem codec slot.
1496          */
1497         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1498         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1499         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1500         /* broken BIOS */
1501         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1502         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1503         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1504         /* forced codec slots */
1505         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1506         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1507         /* WinFast VP200 H (Teradici) user reported broken communication */
1508         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1509         {}
1510 };
1511
1512 #define AZX_FORCE_CODEC_MASK    0x100
1513
1514 static void check_probe_mask(struct azx *chip, int dev)
1515 {
1516         const struct snd_pci_quirk *q;
1517
1518         chip->codec_probe_mask = probe_mask[dev];
1519         if (chip->codec_probe_mask == -1) {
1520                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1521                 if (q) {
1522                         dev_info(chip->card->dev,
1523                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1524                                  q->value, q->subvendor, q->subdevice);
1525                         chip->codec_probe_mask = q->value;
1526                 }
1527         }
1528
1529         /* check forced option */
1530         if (chip->codec_probe_mask != -1 &&
1531             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1532                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1533                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1534                          (int)azx_bus(chip)->codec_mask);
1535         }
1536 }
1537
1538 /*
1539  * white/black-list for enable_msi
1540  */
1541 static struct snd_pci_quirk msi_black_list[] = {
1542         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1543         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1544         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1545         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1546         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1547         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1548         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1549         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1550         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1551         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1552         {}
1553 };
1554
1555 static void check_msi(struct azx *chip)
1556 {
1557         const struct snd_pci_quirk *q;
1558
1559         if (enable_msi >= 0) {
1560                 chip->msi = !!enable_msi;
1561                 return;
1562         }
1563         chip->msi = 1;  /* enable MSI as default */
1564         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1565         if (q) {
1566                 dev_info(chip->card->dev,
1567                          "msi for device %04x:%04x set to %d\n",
1568                          q->subvendor, q->subdevice, q->value);
1569                 chip->msi = q->value;
1570                 return;
1571         }
1572
1573         /* NVidia chipsets seem to cause troubles with MSI */
1574         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1575                 dev_info(chip->card->dev, "Disabling MSI\n");
1576                 chip->msi = 0;
1577         }
1578 }
1579
1580 /* check the snoop mode availability */
1581 static void azx_check_snoop_available(struct azx *chip)
1582 {
1583         int snoop = hda_snoop;
1584
1585         if (snoop >= 0) {
1586                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1587                          snoop ? "snoop" : "non-snoop");
1588                 chip->snoop = snoop;
1589                 chip->uc_buffer = !snoop;
1590                 return;
1591         }
1592
1593         snoop = true;
1594         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1595             chip->driver_type == AZX_DRIVER_VIA) {
1596                 /* force to non-snoop mode for a new VIA controller
1597                  * when BIOS is set
1598                  */
1599                 u8 val;
1600                 pci_read_config_byte(chip->pci, 0x42, &val);
1601                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1602                                       chip->pci->revision == 0x20))
1603                         snoop = false;
1604         }
1605
1606         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1607                 snoop = false;
1608
1609         chip->snoop = snoop;
1610         if (!snoop) {
1611                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1612                 /* C-Media requires non-cached pages only for CORB/RIRB */
1613                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1614                         chip->uc_buffer = true;
1615         }
1616 }
1617
1618 static void azx_probe_work(struct work_struct *work)
1619 {
1620         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1621         azx_probe_continue(&hda->chip);
1622 }
1623
1624 static int default_bdl_pos_adj(struct azx *chip)
1625 {
1626         /* some exceptions: Atoms seem problematic with value 1 */
1627         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1628                 switch (chip->pci->device) {
1629                 case 0x0f04: /* Baytrail */
1630                 case 0x2284: /* Braswell */
1631                         return 32;
1632                 }
1633         }
1634
1635         switch (chip->driver_type) {
1636         case AZX_DRIVER_ICH:
1637         case AZX_DRIVER_PCH:
1638                 return 1;
1639         default:
1640                 return 32;
1641         }
1642 }
1643
1644 /*
1645  * constructor
1646  */
1647 static const struct hdac_io_ops pci_hda_io_ops;
1648 static const struct hda_controller_ops pci_hda_ops;
1649
1650 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1651                       int dev, unsigned int driver_caps,
1652                       struct azx **rchip)
1653 {
1654         static struct snd_device_ops ops = {
1655                 .dev_disconnect = azx_dev_disconnect,
1656                 .dev_free = azx_dev_free,
1657         };
1658         struct hda_intel *hda;
1659         struct azx *chip;
1660         int err;
1661
1662         *rchip = NULL;
1663
1664         err = pci_enable_device(pci);
1665         if (err < 0)
1666                 return err;
1667
1668         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1669         if (!hda) {
1670                 pci_disable_device(pci);
1671                 return -ENOMEM;
1672         }
1673
1674         chip = &hda->chip;
1675         mutex_init(&chip->open_mutex);
1676         chip->card = card;
1677         chip->pci = pci;
1678         chip->ops = &pci_hda_ops;
1679         chip->driver_caps = driver_caps;
1680         chip->driver_type = driver_caps & 0xff;
1681         check_msi(chip);
1682         chip->dev_index = dev;
1683         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1684                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1685         INIT_LIST_HEAD(&chip->pcm_list);
1686         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1687         INIT_LIST_HEAD(&hda->list);
1688         init_vga_switcheroo(chip);
1689         init_completion(&hda->probe_wait);
1690
1691         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1692
1693         check_probe_mask(chip, dev);
1694
1695         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1696                 chip->fallback_to_single_cmd = 1;
1697         else /* explicitly set to single_cmd or not */
1698                 chip->single_cmd = single_cmd;
1699
1700         azx_check_snoop_available(chip);
1701
1702         if (bdl_pos_adj[dev] < 0)
1703                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1704         else
1705                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1706
1707         /* Workaround for a communication error on CFL (bko#199007) */
1708         if (IS_CFL(pci))
1709                 chip->polling_mode = 1;
1710
1711         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1712         if (err < 0) {
1713                 kfree(hda);
1714                 pci_disable_device(pci);
1715                 return err;
1716         }
1717
1718         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1719                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1720                 chip->bus.needs_damn_long_delay = 1;
1721         }
1722
1723         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1724         if (err < 0) {
1725                 dev_err(card->dev, "Error creating device [card]!\n");
1726                 azx_free(chip);
1727                 return err;
1728         }
1729
1730         /* continue probing in work context as may trigger request module */
1731         INIT_WORK(&hda->probe_work, azx_probe_work);
1732
1733         *rchip = chip;
1734
1735         return 0;
1736 }
1737
1738 static int azx_first_init(struct azx *chip)
1739 {
1740         int dev = chip->dev_index;
1741         struct pci_dev *pci = chip->pci;
1742         struct snd_card *card = chip->card;
1743         struct hdac_bus *bus = azx_bus(chip);
1744         int err;
1745         unsigned short gcap;
1746         unsigned int dma_bits = 64;
1747
1748 #if BITS_PER_LONG != 64
1749         /* Fix up base address on ULI M5461 */
1750         if (chip->driver_type == AZX_DRIVER_ULI) {
1751                 u16 tmp3;
1752                 pci_read_config_word(pci, 0x40, &tmp3);
1753                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1754                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1755         }
1756 #endif
1757
1758         err = pci_request_regions(pci, "ICH HD audio");
1759         if (err < 0)
1760                 return err;
1761         chip->region_requested = 1;
1762
1763         bus->addr = pci_resource_start(pci, 0);
1764         bus->remap_addr = pci_ioremap_bar(pci, 0);
1765         if (bus->remap_addr == NULL) {
1766                 dev_err(card->dev, "ioremap error\n");
1767                 return -ENXIO;
1768         }
1769
1770         if (chip->driver_type == AZX_DRIVER_SKL)
1771                 snd_hdac_bus_parse_capabilities(bus);
1772
1773         /*
1774          * Some Intel CPUs has always running timer (ART) feature and
1775          * controller may have Global time sync reporting capability, so
1776          * check both of these before declaring synchronized time reporting
1777          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1778          */
1779         chip->gts_present = false;
1780
1781 #ifdef CONFIG_X86
1782         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1783                 chip->gts_present = true;
1784 #endif
1785
1786         if (chip->msi) {
1787                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1788                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1789                         pci->no_64bit_msi = true;
1790                 }
1791                 if (pci_enable_msi(pci) < 0)
1792                         chip->msi = 0;
1793         }
1794
1795         if (azx_acquire_irq(chip, 0) < 0)
1796                 return -EBUSY;
1797
1798         pci_set_master(pci);
1799         synchronize_irq(bus->irq);
1800
1801         gcap = azx_readw(chip, GCAP);
1802         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1803
1804         /* AMD devices support 40 or 48bit DMA, take the safe one */
1805         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1806                 dma_bits = 40;
1807
1808         /* disable SB600 64bit support for safety */
1809         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1810                 struct pci_dev *p_smbus;
1811                 dma_bits = 40;
1812                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1813                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1814                                          NULL);
1815                 if (p_smbus) {
1816                         if (p_smbus->revision < 0x30)
1817                                 gcap &= ~AZX_GCAP_64OK;
1818                         pci_dev_put(p_smbus);
1819                 }
1820         }
1821
1822         /* NVidia hardware normally only supports up to 40 bits of DMA */
1823         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1824                 dma_bits = 40;
1825
1826         /* disable 64bit DMA address on some devices */
1827         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1828                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1829                 gcap &= ~AZX_GCAP_64OK;
1830         }
1831
1832         /* disable buffer size rounding to 128-byte multiples if supported */
1833         if (align_buffer_size >= 0)
1834                 chip->align_buffer_size = !!align_buffer_size;
1835         else {
1836                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1837                         chip->align_buffer_size = 0;
1838                 else
1839                         chip->align_buffer_size = 1;
1840         }
1841
1842         /* allow 64bit DMA address if supported by H/W */
1843         if (!(gcap & AZX_GCAP_64OK))
1844                 dma_bits = 32;
1845         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1846                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1847         } else {
1848                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1849                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1850         }
1851
1852         /* read number of streams from GCAP register instead of using
1853          * hardcoded value
1854          */
1855         chip->capture_streams = (gcap >> 8) & 0x0f;
1856         chip->playback_streams = (gcap >> 12) & 0x0f;
1857         if (!chip->playback_streams && !chip->capture_streams) {
1858                 /* gcap didn't give any info, switching to old method */
1859
1860                 switch (chip->driver_type) {
1861                 case AZX_DRIVER_ULI:
1862                         chip->playback_streams = ULI_NUM_PLAYBACK;
1863                         chip->capture_streams = ULI_NUM_CAPTURE;
1864                         break;
1865                 case AZX_DRIVER_ATIHDMI:
1866                 case AZX_DRIVER_ATIHDMI_NS:
1867                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1868                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1869                         break;
1870                 case AZX_DRIVER_GENERIC:
1871                 default:
1872                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1873                         chip->capture_streams = ICH6_NUM_CAPTURE;
1874                         break;
1875                 }
1876         }
1877         chip->capture_index_offset = 0;
1878         chip->playback_index_offset = chip->capture_streams;
1879         chip->num_streams = chip->playback_streams + chip->capture_streams;
1880
1881         /* sanity check for the SDxCTL.STRM field overflow */
1882         if (chip->num_streams > 15 &&
1883             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1884                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1885                          "forcing separate stream tags", chip->num_streams);
1886                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1887         }
1888
1889         /* initialize streams */
1890         err = azx_init_streams(chip);
1891         if (err < 0)
1892                 return err;
1893
1894         err = azx_alloc_stream_pages(chip);
1895         if (err < 0)
1896                 return err;
1897
1898         /* initialize chip */
1899         azx_init_pci(chip);
1900
1901         snd_hdac_i915_set_bclk(bus);
1902
1903         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1904
1905         /* codec detection */
1906         if (!azx_bus(chip)->codec_mask) {
1907                 dev_err(card->dev, "no codecs found!\n");
1908                 return -ENODEV;
1909         }
1910
1911         strcpy(card->driver, "HDA-Intel");
1912         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1913                 sizeof(card->shortname));
1914         snprintf(card->longname, sizeof(card->longname),
1915                  "%s at 0x%lx irq %i",
1916                  card->shortname, bus->addr, bus->irq);
1917
1918         return 0;
1919 }
1920
1921 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1922 /* callback from request_firmware_nowait() */
1923 static void azx_firmware_cb(const struct firmware *fw, void *context)
1924 {
1925         struct snd_card *card = context;
1926         struct azx *chip = card->private_data;
1927         struct pci_dev *pci = chip->pci;
1928
1929         if (!fw) {
1930                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1931                 goto error;
1932         }
1933
1934         chip->fw = fw;
1935         if (!chip->disabled) {
1936                 /* continue probing */
1937                 if (azx_probe_continue(chip))
1938                         goto error;
1939         }
1940         return; /* OK */
1941
1942  error:
1943         snd_card_free(card);
1944         pci_set_drvdata(pci, NULL);
1945 }
1946 #endif
1947
1948 /*
1949  * HDA controller ops.
1950  */
1951
1952 /* PCI register access. */
1953 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1954 {
1955         writel(value, addr);
1956 }
1957
1958 static u32 pci_azx_readl(u32 __iomem *addr)
1959 {
1960         return readl(addr);
1961 }
1962
1963 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1964 {
1965         writew(value, addr);
1966 }
1967
1968 static u16 pci_azx_readw(u16 __iomem *addr)
1969 {
1970         return readw(addr);
1971 }
1972
1973 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1974 {
1975         writeb(value, addr);
1976 }
1977
1978 static u8 pci_azx_readb(u8 __iomem *addr)
1979 {
1980         return readb(addr);
1981 }
1982
1983 static int disable_msi_reset_irq(struct azx *chip)
1984 {
1985         struct hdac_bus *bus = azx_bus(chip);
1986         int err;
1987
1988         free_irq(bus->irq, chip);
1989         bus->irq = -1;
1990         pci_disable_msi(chip->pci);
1991         chip->msi = 0;
1992         err = azx_acquire_irq(chip, 1);
1993         if (err < 0)
1994                 return err;
1995
1996         return 0;
1997 }
1998
1999 /* DMA page allocation helpers.  */
2000 static int dma_alloc_pages(struct hdac_bus *bus,
2001                            int type,
2002                            size_t size,
2003                            struct snd_dma_buffer *buf)
2004 {
2005         struct azx *chip = bus_to_azx(bus);
2006
2007         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2008                 type = SNDRV_DMA_TYPE_DEV_UC;
2009         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2010 }
2011
2012 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2013 {
2014         snd_dma_free_pages(buf);
2015 }
2016
2017 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2018                              struct vm_area_struct *area)
2019 {
2020 #ifdef CONFIG_X86
2021         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2022         struct azx *chip = apcm->chip;
2023         if (chip->uc_buffer)
2024                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2025 #endif
2026 }
2027
2028 static const struct hdac_io_ops pci_hda_io_ops = {
2029         .reg_writel = pci_azx_writel,
2030         .reg_readl = pci_azx_readl,
2031         .reg_writew = pci_azx_writew,
2032         .reg_readw = pci_azx_readw,
2033         .reg_writeb = pci_azx_writeb,
2034         .reg_readb = pci_azx_readb,
2035         .dma_alloc_pages = dma_alloc_pages,
2036         .dma_free_pages = dma_free_pages,
2037 };
2038
2039 static const struct hda_controller_ops pci_hda_ops = {
2040         .disable_msi_reset_irq = disable_msi_reset_irq,
2041         .pcm_mmap_prepare = pcm_mmap_prepare,
2042         .position_check = azx_position_check,
2043 };
2044
2045 static int azx_probe(struct pci_dev *pci,
2046                      const struct pci_device_id *pci_id)
2047 {
2048         static int dev;
2049         struct snd_card *card;
2050         struct hda_intel *hda;
2051         struct azx *chip;
2052         bool schedule_probe;
2053         int err;
2054
2055         /* check if this driver can be used on SKL+ Intel platforms */
2056         if (pci_id->driver_data & AZX_DCAPS_INTEL_SHARED) {
2057                 switch (skl_pci_binding) {
2058                 case SND_SKL_PCI_BIND_AUTO:
2059                         if (pci->class != 0x040300) {
2060                                 dev_info(&pci->dev, "The DSP is enabled on this platform, aborting probe\n");
2061                                 return -ENODEV;
2062                         }
2063                         dev_info(&pci->dev, "No DSP detected, continuing HDaudio legacy probe\n");
2064                         break;
2065                 case SND_SKL_PCI_BIND_LEGACY:
2066                         dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, bypassed detection logic\n");
2067                         break;
2068                 case SND_SKL_PCI_BIND_ASOC:
2069                         dev_info(&pci->dev, "Module parameter forced binding with SKL+ ASoC driver, aborting probe\n");
2070                         return -ENODEV;
2071                 default:
2072                         dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
2073                         break;
2074                 }
2075         }
2076
2077         if (dev >= SNDRV_CARDS)
2078                 return -ENODEV;
2079         if (!enable[dev]) {
2080                 dev++;
2081                 return -ENOENT;
2082         }
2083
2084         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2085                            0, &card);
2086         if (err < 0) {
2087                 dev_err(&pci->dev, "Error creating card!\n");
2088                 return err;
2089         }
2090
2091         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2092         if (err < 0)
2093                 goto out_free;
2094         card->private_data = chip;
2095         hda = container_of(chip, struct hda_intel, chip);
2096
2097         pci_set_drvdata(pci, card);
2098
2099         err = register_vga_switcheroo(chip);
2100         if (err < 0) {
2101                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2102                 goto out_free;
2103         }
2104
2105         if (check_hdmi_disabled(pci)) {
2106                 dev_info(card->dev, "VGA controller is disabled\n");
2107                 dev_info(card->dev, "Delaying initialization\n");
2108                 chip->disabled = true;
2109         }
2110
2111         schedule_probe = !chip->disabled;
2112
2113 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2114         if (patch[dev] && *patch[dev]) {
2115                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2116                          patch[dev]);
2117                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2118                                               &pci->dev, GFP_KERNEL, card,
2119                                               azx_firmware_cb);
2120                 if (err < 0)
2121                         goto out_free;
2122                 schedule_probe = false; /* continued in azx_firmware_cb() */
2123         }
2124 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2125
2126 #ifndef CONFIG_SND_HDA_I915
2127         if (CONTROLLER_IN_GPU(pci))
2128                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2129 #endif
2130
2131         if (schedule_probe)
2132                 schedule_work(&hda->probe_work);
2133
2134         dev++;
2135         if (chip->disabled)
2136                 complete_all(&hda->probe_wait);
2137         return 0;
2138
2139 out_free:
2140         snd_card_free(card);
2141         return err;
2142 }
2143
2144 #ifdef CONFIG_PM
2145 /* On some boards setting power_save to a non 0 value leads to clicking /
2146  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2147  * figure out how to avoid these sounds, but that is not always feasible.
2148  * So we keep a list of devices where we disable powersaving as its known
2149  * to causes problems on these devices.
2150  */
2151 static struct snd_pci_quirk power_save_blacklist[] = {
2152         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2153         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2154         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2155         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2156         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2157         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2158         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2159         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2160         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2161         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2162         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2163         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2164         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2165         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2166         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2167         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2168         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2169         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2170         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2171         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2172         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2173         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2174         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2175         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2176         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2177         {}
2178 };
2179 #endif /* CONFIG_PM */
2180
2181 static void set_default_power_save(struct azx *chip)
2182 {
2183         int val = power_save;
2184
2185 #ifdef CONFIG_PM
2186         if (pm_blacklist) {
2187                 const struct snd_pci_quirk *q;
2188
2189                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2190                 if (q && val) {
2191                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2192                                  q->subvendor, q->subdevice);
2193                         val = 0;
2194                 }
2195         }
2196 #endif /* CONFIG_PM */
2197         snd_hda_set_power_save(&chip->bus, val * 1000);
2198 }
2199
2200 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2201 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2202         [AZX_DRIVER_NVIDIA] = 8,
2203         [AZX_DRIVER_TERA] = 1,
2204 };
2205
2206 static int azx_probe_continue(struct azx *chip)
2207 {
2208         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2209         struct hdac_bus *bus = azx_bus(chip);
2210         struct pci_dev *pci = chip->pci;
2211         int dev = chip->dev_index;
2212         int err;
2213
2214         hda->probe_continued = 1;
2215
2216         /* bind with i915 if needed */
2217         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2218                 err = snd_hdac_i915_init(bus);
2219                 if (err < 0) {
2220                         /* if the controller is bound only with HDMI/DP
2221                          * (for HSW and BDW), we need to abort the probe;
2222                          * for other chips, still continue probing as other
2223                          * codecs can be on the same link.
2224                          */
2225                         if (CONTROLLER_IN_GPU(pci)) {
2226                                 dev_err(chip->card->dev,
2227                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2228                                 goto out_free;
2229                         } else {
2230                                 /* don't bother any longer */
2231                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2232                         }
2233                 }
2234
2235                 /* HSW/BDW controllers need this power */
2236                 if (CONTROLLER_IN_GPU(pci))
2237                         hda->need_i915_power = 1;
2238         }
2239
2240         /* Request display power well for the HDA controller or codec. For
2241          * Haswell/Broadwell, both the display HDA controller and codec need
2242          * this power. For other platforms, like Baytrail/Braswell, only the
2243          * display codec needs the power and it can be released after probe.
2244          */
2245         display_power(chip, true);
2246
2247         err = azx_first_init(chip);
2248         if (err < 0)
2249                 goto out_free;
2250
2251 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2252         chip->beep_mode = beep_mode[dev];
2253 #endif
2254
2255         /* create codec instances */
2256         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2257         if (err < 0)
2258                 goto out_free;
2259
2260 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2261         if (chip->fw) {
2262                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2263                                          chip->fw->data);
2264                 if (err < 0)
2265                         goto out_free;
2266 #ifndef CONFIG_PM
2267                 release_firmware(chip->fw); /* no longer needed */
2268                 chip->fw = NULL;
2269 #endif
2270         }
2271 #endif
2272         if ((probe_only[dev] & 1) == 0) {
2273                 err = azx_codec_configure(chip);
2274                 if (err < 0)
2275                         goto out_free;
2276         }
2277
2278         err = snd_card_register(chip->card);
2279         if (err < 0)
2280                 goto out_free;
2281
2282         setup_vga_switcheroo_runtime_pm(chip);
2283
2284         chip->running = 1;
2285         azx_add_card_list(chip);
2286
2287         set_default_power_save(chip);
2288
2289         if (azx_has_pm_runtime(chip))
2290                 pm_runtime_put_autosuspend(&pci->dev);
2291
2292 out_free:
2293         if (err < 0 || !hda->need_i915_power)
2294                 display_power(chip, false);
2295         if (err < 0)
2296                 hda->init_failed = 1;
2297         complete_all(&hda->probe_wait);
2298         return err;
2299 }
2300
2301 static void azx_remove(struct pci_dev *pci)
2302 {
2303         struct snd_card *card = pci_get_drvdata(pci);
2304         struct azx *chip;
2305         struct hda_intel *hda;
2306
2307         if (card) {
2308                 /* cancel the pending probing work */
2309                 chip = card->private_data;
2310                 hda = container_of(chip, struct hda_intel, chip);
2311                 /* FIXME: below is an ugly workaround.
2312                  * Both device_release_driver() and driver_probe_device()
2313                  * take *both* the device's and its parent's lock before
2314                  * calling the remove() and probe() callbacks.  The codec
2315                  * probe takes the locks of both the codec itself and its
2316                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2317                  * the PCI controller is unbound, it takes its lock, too
2318                  * ==> ouch, a deadlock!
2319                  * As a workaround, we unlock temporarily here the controller
2320                  * device during cancel_work_sync() call.
2321                  */
2322                 device_unlock(&pci->dev);
2323                 cancel_work_sync(&hda->probe_work);
2324                 device_lock(&pci->dev);
2325
2326                 snd_card_free(card);
2327         }
2328 }
2329
2330 static void azx_shutdown(struct pci_dev *pci)
2331 {
2332         struct snd_card *card = pci_get_drvdata(pci);
2333         struct azx *chip;
2334
2335         if (!card)
2336                 return;
2337         chip = card->private_data;
2338         if (chip && chip->running)
2339                 azx_stop_chip(chip);
2340 }
2341
2342 /* PCI IDs */
2343 static const struct pci_device_id azx_ids[] = {
2344         /* CPT */
2345         { PCI_DEVICE(0x8086, 0x1c20),
2346           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2347         /* PBG */
2348         { PCI_DEVICE(0x8086, 0x1d20),
2349           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2350         /* Panther Point */
2351         { PCI_DEVICE(0x8086, 0x1e20),
2352           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2353         /* Lynx Point */
2354         { PCI_DEVICE(0x8086, 0x8c20),
2355           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2356         /* 9 Series */
2357         { PCI_DEVICE(0x8086, 0x8ca0),
2358           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2359         /* Wellsburg */
2360         { PCI_DEVICE(0x8086, 0x8d20),
2361           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2362         { PCI_DEVICE(0x8086, 0x8d21),
2363           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2364         /* Lewisburg */
2365         { PCI_DEVICE(0x8086, 0xa1f0),
2366           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2367         { PCI_DEVICE(0x8086, 0xa270),
2368           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2369         /* Lynx Point-LP */
2370         { PCI_DEVICE(0x8086, 0x9c20),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2372         /* Lynx Point-LP */
2373         { PCI_DEVICE(0x8086, 0x9c21),
2374           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2375         /* Wildcat Point-LP */
2376         { PCI_DEVICE(0x8086, 0x9ca0),
2377           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2378         /* Sunrise Point */
2379         { PCI_DEVICE(0x8086, 0xa170),
2380           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2381         /* Sunrise Point-LP */
2382         { PCI_DEVICE(0x8086, 0x9d70),
2383           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE |
2384           AZX_DCAPS_INTEL_DSP_DETECTION(SKL)
2385         },
2386         /* Kabylake */
2387         { PCI_DEVICE(0x8086, 0xa171),
2388           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2389         /* Kabylake-LP */
2390         { PCI_DEVICE(0x8086, 0x9d71),
2391           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE |
2392           AZX_DCAPS_INTEL_DSP_DETECTION(KBL)
2393         },
2394         /* Kabylake-H */
2395         { PCI_DEVICE(0x8086, 0xa2f0),
2396           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2397         /* Coffelake */
2398         { PCI_DEVICE(0x8086, 0xa348),
2399           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE |
2400           AZX_DCAPS_INTEL_DSP_DETECTION(CFL)
2401         },
2402         /* Cannonlake */
2403         { PCI_DEVICE(0x8086, 0x9dc8),
2404           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE |
2405           AZX_DCAPS_INTEL_DSP_DETECTION(CNL)
2406         },
2407         /* Icelake */
2408         { PCI_DEVICE(0x8086, 0x34c8),
2409           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE |
2410           AZX_DCAPS_INTEL_DSP_DETECTION(ICL)
2411         },
2412         /* Broxton-P(Apollolake) */
2413         { PCI_DEVICE(0x8086, 0x5a98),
2414           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON |
2415           AZX_DCAPS_INTEL_DSP_DETECTION(APL)
2416         },
2417         /* Broxton-T */
2418         { PCI_DEVICE(0x8086, 0x1a98),
2419           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2420         /* Gemini-Lake */
2421         { PCI_DEVICE(0x8086, 0x3198),
2422           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON |
2423           AZX_DCAPS_INTEL_DSP_DETECTION(GLK)
2424         },
2425         /* Haswell */
2426         { PCI_DEVICE(0x8086, 0x0a0c),
2427           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2428         { PCI_DEVICE(0x8086, 0x0c0c),
2429           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2430         { PCI_DEVICE(0x8086, 0x0d0c),
2431           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2432         /* Broadwell */
2433         { PCI_DEVICE(0x8086, 0x160c),
2434           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2435         /* 5 Series/3400 */
2436         { PCI_DEVICE(0x8086, 0x3b56),
2437           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2438         /* Poulsbo */
2439         { PCI_DEVICE(0x8086, 0x811b),
2440           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2441         /* Oaktrail */
2442         { PCI_DEVICE(0x8086, 0x080a),
2443           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2444         /* BayTrail */
2445         { PCI_DEVICE(0x8086, 0x0f04),
2446           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2447         /* Braswell */
2448         { PCI_DEVICE(0x8086, 0x2284),
2449           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2450         /* ICH6 */
2451         { PCI_DEVICE(0x8086, 0x2668),
2452           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453         /* ICH7 */
2454         { PCI_DEVICE(0x8086, 0x27d8),
2455           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2456         /* ESB2 */
2457         { PCI_DEVICE(0x8086, 0x269a),
2458           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2459         /* ICH8 */
2460         { PCI_DEVICE(0x8086, 0x284b),
2461           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2462         /* ICH9 */
2463         { PCI_DEVICE(0x8086, 0x293e),
2464           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2465         /* ICH9 */
2466         { PCI_DEVICE(0x8086, 0x293f),
2467           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2468         /* ICH10 */
2469         { PCI_DEVICE(0x8086, 0x3a3e),
2470           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2471         /* ICH10 */
2472         { PCI_DEVICE(0x8086, 0x3a6e),
2473           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2474         /* Generic Intel */
2475         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2476           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2477           .class_mask = 0xffffff,
2478           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2479         /* ATI SB 450/600/700/800/900 */
2480         { PCI_DEVICE(0x1002, 0x437b),
2481           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2482         { PCI_DEVICE(0x1002, 0x4383),
2483           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2484         /* AMD Hudson */
2485         { PCI_DEVICE(0x1022, 0x780d),
2486           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2487         /* AMD Stoney */
2488         { PCI_DEVICE(0x1022, 0x157a),
2489           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2490                          AZX_DCAPS_PM_RUNTIME },
2491         /* AMD Raven */
2492         { PCI_DEVICE(0x1022, 0x15e3),
2493           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2494                          AZX_DCAPS_PM_RUNTIME },
2495         /* ATI HDMI */
2496         { PCI_DEVICE(0x1002, 0x0002),
2497           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2498         { PCI_DEVICE(0x1002, 0x1308),
2499           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2500         { PCI_DEVICE(0x1002, 0x157a),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x15b3),
2503           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2504         { PCI_DEVICE(0x1002, 0x793b),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0x7919),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0x960f),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x970f),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0x9840),
2513           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2514         { PCI_DEVICE(0x1002, 0xaa00),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa08),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa10),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa18),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa20),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa28),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa30),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa38),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa40),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa48),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa50),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa58),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa60),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa68),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa80),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa88),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa90),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa98),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0x9902),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaaa0),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaaa8),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaab0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaac0),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaac8),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaad8),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaae8),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaae0),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         { PCI_DEVICE(0x1002, 0xaaf0),
2569           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2570         /* VIA VT8251/VT8237A */
2571         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2572         /* VIA GFX VT7122/VX900 */
2573         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2574         /* VIA GFX VT6122/VX11 */
2575         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2576         /* SIS966 */
2577         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2578         /* ULI M5461 */
2579         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2580         /* NVIDIA MCP */
2581         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2582           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2583           .class_mask = 0xffffff,
2584           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2585         /* Teradici */
2586         { PCI_DEVICE(0x6549, 0x1200),
2587           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2588         { PCI_DEVICE(0x6549, 0x2200),
2589           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2590         /* Creative X-Fi (CA0110-IBG) */
2591         /* CTHDA chips */
2592         { PCI_DEVICE(0x1102, 0x0010),
2593           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2594         { PCI_DEVICE(0x1102, 0x0012),
2595           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2596 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2597         /* the following entry conflicts with snd-ctxfi driver,
2598          * as ctxfi driver mutates from HD-audio to native mode with
2599          * a special command sequence.
2600          */
2601         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2602           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2603           .class_mask = 0xffffff,
2604           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2605           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2606 #else
2607         /* this entry seems still valid -- i.e. without emu20kx chip */
2608         { PCI_DEVICE(0x1102, 0x0009),
2609           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2610           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2611 #endif
2612         /* CM8888 */
2613         { PCI_DEVICE(0x13f6, 0x5011),
2614           .driver_data = AZX_DRIVER_CMEDIA |
2615           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2616         /* Vortex86MX */
2617         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2618         /* VMware HDAudio */
2619         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2620         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2621         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2622           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2623           .class_mask = 0xffffff,
2624           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2626           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2627           .class_mask = 0xffffff,
2628           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2629         { 0, }
2630 };
2631 MODULE_DEVICE_TABLE(pci, azx_ids);
2632
2633 /* pci_driver definition */
2634 static struct pci_driver azx_driver = {
2635         .name = KBUILD_MODNAME,
2636         .id_table = azx_ids,
2637         .probe = azx_probe,
2638         .remove = azx_remove,
2639         .shutdown = azx_shutdown,
2640         .driver = {
2641                 .pm = AZX_PM_OPS,
2642         },
2643 };
2644
2645 module_pci_driver(azx_driver);