1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * hda_intel.c - Implementation of primary alsa driver code base
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
40 /* for snoop control */
41 #include <asm/pgtable.h>
42 #include <asm/set_memory.h>
43 #include <asm/cpufeature.h>
45 #include <sound/core.h>
46 #include <sound/initval.h>
47 #include <sound/hdaudio.h>
48 #include <sound/hda_i915.h>
49 #include <linux/vgaarb.h>
50 #include <linux/vga_switcheroo.h>
51 #include <linux/firmware.h>
52 #include <sound/hda_codec.h>
53 #include "hda_controller.h"
54 #include "hda_intel.h"
56 #define CREATE_TRACE_POINTS
57 #include "hda_intel_trace.h"
59 /* position fix mode */
69 /* Defines for ATI HD Audio support in SB450 south bridge */
70 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
71 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
73 /* Defines for Nvidia HDA support */
74 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
75 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
76 #define NVIDIA_HDA_ISTRM_COH 0x4d
77 #define NVIDIA_HDA_OSTRM_COH 0x4c
78 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
80 /* Defines for Intel SCH HDA snoop control */
81 #define INTEL_HDA_CGCTL 0x48
82 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
83 #define INTEL_SCH_HDA_DEVC 0x78
84 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
86 /* Define IN stream 0 FIFO size offset in VIA controller */
87 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
88 /* Define VIA HD Audio Device ID*/
89 #define VIA_HDAC_DEVICE_ID 0x3288
91 /* max number of SDs */
92 /* ICH, ATI and VIA have 4 playback and 4 capture */
93 #define ICH6_NUM_CAPTURE 4
94 #define ICH6_NUM_PLAYBACK 4
96 /* ULI has 6 playback and 5 capture */
97 #define ULI_NUM_CAPTURE 5
98 #define ULI_NUM_PLAYBACK 6
100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
101 #define ATIHDMI_NUM_CAPTURE 0
102 #define ATIHDMI_NUM_PLAYBACK 8
104 /* TERA has 4 playback and 3 capture */
105 #define TERA_NUM_CAPTURE 3
106 #define TERA_NUM_PLAYBACK 4
109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
112 static char *model[SNDRV_CARDS];
113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_only[SNDRV_CARDS];
117 static int jackpoll_ms[SNDRV_CARDS];
118 static int single_cmd = -1;
119 static int enable_msi = -1;
120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
121 static char *patch[SNDRV_CARDS];
123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
125 CONFIG_SND_HDA_INPUT_BEEP_MODE};
128 module_param_array(index, int, NULL, 0444);
129 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
130 module_param_array(id, charp, NULL, 0444);
131 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
132 module_param_array(enable, bool, NULL, 0444);
133 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
134 module_param_array(model, charp, NULL, 0444);
135 MODULE_PARM_DESC(model, "Use the given board model.");
136 module_param_array(position_fix, int, NULL, 0444);
137 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
138 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
139 module_param_array(bdl_pos_adj, int, NULL, 0644);
140 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
141 module_param_array(probe_mask, int, NULL, 0444);
142 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
143 module_param_array(probe_only, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
145 module_param_array(jackpoll_ms, int, NULL, 0444);
146 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
147 module_param(single_cmd, bint, 0444);
148 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
149 "(for debugging only).");
150 module_param(enable_msi, bint, 0444);
151 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
152 #ifdef CONFIG_SND_HDA_PATCH_LOADER
153 module_param_array(patch, charp, NULL, 0444);
154 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
156 #ifdef CONFIG_SND_HDA_INPUT_BEEP
157 module_param_array(beep_mode, bool, NULL, 0444);
158 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
159 "(0=off, 1=on) (default=1).");
163 static int param_set_xint(const char *val, const struct kernel_param *kp);
164 static const struct kernel_param_ops param_ops_xint = {
165 .set = param_set_xint,
166 .get = param_get_int,
168 #define param_check_xint param_check_int
170 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
171 module_param(power_save, xint, 0644);
172 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
173 "(in second, 0 = disable).");
175 static bool pm_blacklist = true;
176 module_param(pm_blacklist, bool, 0644);
177 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
179 /* reset the HD-audio controller in power save mode.
180 * this may give more power-saving, but will take longer time to
183 static bool power_save_controller = 1;
184 module_param(power_save_controller, bool, 0644);
185 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
188 #endif /* CONFIG_PM */
190 static int align_buffer_size = -1;
191 module_param(align_buffer_size, bint, 0644);
192 MODULE_PARM_DESC(align_buffer_size,
193 "Force buffer and period sizes to be multiple of 128 bytes.");
196 static int hda_snoop = -1;
197 module_param_named(snoop, hda_snoop, bint, 0444);
198 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
200 #define hda_snoop true
204 MODULE_LICENSE("GPL");
205 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
239 MODULE_DESCRIPTION("Intel HDA driver");
241 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
242 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
243 #define SUPPORT_VGA_SWITCHEROO
260 AZX_DRIVER_ATIHDMI_NS,
270 AZX_NUM_DRIVERS, /* keep this as last entry */
273 #define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
277 /* quirks for old Intel chipsets */
278 #define AZX_DCAPS_INTEL_ICH \
279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
281 /* quirks for Intel PCH */
282 #define AZX_DCAPS_INTEL_PCH_BASE \
283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
284 AZX_DCAPS_SNOOP_TYPE(SCH))
286 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
287 #define AZX_DCAPS_INTEL_PCH_NOPM \
288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
290 /* PCH for HSW/BDW; with runtime PM */
291 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
292 #define AZX_DCAPS_INTEL_PCH \
293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
296 #define AZX_DCAPS_INTEL_HASWELL \
297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
299 AZX_DCAPS_SNOOP_TYPE(SCH))
301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
302 #define AZX_DCAPS_INTEL_BROADWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
307 #define AZX_DCAPS_INTEL_BAYTRAIL \
308 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
310 #define AZX_DCAPS_INTEL_BRASWELL \
311 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
312 AZX_DCAPS_I915_COMPONENT)
314 #define AZX_DCAPS_INTEL_SKYLAKE \
315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
316 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
318 #define AZX_DCAPS_INTEL_BROXTON \
319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
320 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
322 /* quirks for ATI SB / AMD Hudson */
323 #define AZX_DCAPS_PRESET_ATI_SB \
324 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
325 AZX_DCAPS_SNOOP_TYPE(ATI))
327 /* quirks for ATI/AMD HDMI */
328 #define AZX_DCAPS_PRESET_ATI_HDMI \
329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
332 /* quirks for ATI HDMI with snoop off */
333 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
334 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
336 /* quirks for Nvidia */
337 #define AZX_DCAPS_PRESET_NVIDIA \
338 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
339 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
341 #define AZX_DCAPS_PRESET_CTHDA \
342 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
343 AZX_DCAPS_NO_64BIT |\
344 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
347 * vga_switcheroo support
349 #ifdef SUPPORT_VGA_SWITCHEROO
350 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
351 #define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link)
353 #define use_vga_switcheroo(chip) 0
354 #define needs_eld_notify_link(chip) false
357 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
358 ((pci)->device == 0x0c0c) || \
359 ((pci)->device == 0x0d0c) || \
360 ((pci)->device == 0x160c))
362 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
363 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
364 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
366 static char *driver_short_names[] = {
367 [AZX_DRIVER_ICH] = "HDA Intel",
368 [AZX_DRIVER_PCH] = "HDA Intel PCH",
369 [AZX_DRIVER_SCH] = "HDA Intel MID",
370 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
371 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
372 [AZX_DRIVER_ATI] = "HDA ATI SB",
373 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
374 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
375 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
376 [AZX_DRIVER_SIS] = "HDA SIS966",
377 [AZX_DRIVER_ULI] = "HDA ULI M5461",
378 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
379 [AZX_DRIVER_TERA] = "HDA Teradici",
380 [AZX_DRIVER_CTX] = "HDA Creative",
381 [AZX_DRIVER_CTHDA] = "HDA Creative",
382 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
383 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
386 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
387 static void set_default_power_save(struct azx *chip);
390 * initialize the PCI registers
392 /* update bits in a PCI register byte */
393 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
394 unsigned char mask, unsigned char val)
398 pci_read_config_byte(pci, reg, &data);
400 data |= (val & mask);
401 pci_write_config_byte(pci, reg, data);
404 static void azx_init_pci(struct azx *chip)
406 int snoop_type = azx_get_snoop_type(chip);
408 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
409 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
410 * Ensuring these bits are 0 clears playback static on some HD Audio
412 * The PCI register TCSEL is defined in the Intel manuals.
414 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
415 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
416 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
419 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
420 * we need to enable snoop.
422 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
423 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
425 update_pci_byte(chip->pci,
426 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
427 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
430 /* For NVIDIA HDA, enable snoop */
431 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
432 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
434 update_pci_byte(chip->pci,
435 NVIDIA_HDA_TRANSREG_ADDR,
436 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
437 update_pci_byte(chip->pci,
438 NVIDIA_HDA_ISTRM_COH,
439 0x01, NVIDIA_HDA_ENABLE_COHBIT);
440 update_pci_byte(chip->pci,
441 NVIDIA_HDA_OSTRM_COH,
442 0x01, NVIDIA_HDA_ENABLE_COHBIT);
445 /* Enable SCH/PCH snoop if needed */
446 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
447 unsigned short snoop;
448 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
449 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
450 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
451 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
452 if (!azx_snoop(chip))
453 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
454 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
455 pci_read_config_word(chip->pci,
456 INTEL_SCH_HDA_DEVC, &snoop);
458 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
459 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
460 "Disabled" : "Enabled");
465 * In BXT-P A0, HD-Audio DMA requests is later than expected,
466 * and makes an audio stream sensitive to system latencies when
467 * 24/32 bits are playing.
468 * Adjusting threshold of DMA fifo to force the DMA request
469 * sooner to improve latency tolerance at the expense of power.
471 static void bxt_reduce_dma_latency(struct azx *chip)
475 val = azx_readl(chip, VS_EM4L);
477 azx_writel(chip, VS_EM4L, val);
482 * bit 0: 6 MHz Supported
483 * bit 1: 12 MHz Supported
484 * bit 2: 24 MHz Supported
485 * bit 3: 48 MHz Supported
486 * bit 4: 96 MHz Supported
487 * bit 5: 192 MHz Supported
489 static int intel_get_lctl_scf(struct azx *chip)
491 struct hdac_bus *bus = azx_bus(chip);
492 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
496 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
498 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
499 t = preferred_bits[i];
504 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
508 static int intel_ml_lctl_set_power(struct azx *chip, int state)
510 struct hdac_bus *bus = azx_bus(chip);
515 * the codecs are sharing the first link setting by default
516 * If other links are enabled for stream, they need similar fix
518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
519 val &= ~AZX_MLCTL_SPA;
520 val |= state << AZX_MLCTL_SPA_SHIFT;
521 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
525 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
526 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
535 static void intel_init_lctl(struct azx *chip)
537 struct hdac_bus *bus = azx_bus(chip);
541 /* 0. check lctl register value is correct or not */
542 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
543 /* if SCF is already set, let's use it */
544 if ((val & ML_LCTL_SCF_MASK) != 0)
548 * Before operating on SPA, CPA must match SPA.
549 * Any deviation may result in undefined behavior.
551 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
552 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
555 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
556 ret = intel_ml_lctl_set_power(chip, 0);
561 /* 2. update SCF to select a properly audio clock*/
562 val &= ~ML_LCTL_SCF_MASK;
563 val |= intel_get_lctl_scf(chip);
564 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
567 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
568 intel_ml_lctl_set_power(chip, 1);
572 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
574 struct hdac_bus *bus = azx_bus(chip);
575 struct pci_dev *pci = chip->pci;
578 snd_hdac_set_codec_wakeup(bus, true);
579 if (chip->driver_type == AZX_DRIVER_SKL) {
580 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
581 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
582 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
584 azx_init_chip(chip, full_reset);
585 if (chip->driver_type == AZX_DRIVER_SKL) {
586 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
587 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
588 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
591 snd_hdac_set_codec_wakeup(bus, false);
593 /* reduce dma latency to avoid noise */
595 bxt_reduce_dma_latency(chip);
597 if (bus->mlcap != NULL)
598 intel_init_lctl(chip);
601 /* calculate runtime delay from LPIB */
602 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
605 struct snd_pcm_substream *substream = azx_dev->core.substream;
606 int stream = substream->stream;
607 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
610 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
611 delay = pos - lpib_pos;
613 delay = lpib_pos - pos;
615 if (delay >= azx_dev->core.delay_negative_threshold)
618 delay += azx_dev->core.bufsize;
621 if (delay >= azx_dev->core.period_bytes) {
622 dev_info(chip->card->dev,
623 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
624 delay, azx_dev->core.period_bytes);
626 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
627 chip->get_delay[stream] = NULL;
630 return bytes_to_frames(substream->runtime, delay);
633 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
635 /* called from IRQ */
636 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
638 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
641 ok = azx_position_ok(chip, azx_dev);
643 azx_dev->irq_pending = 0;
645 } else if (ok == 0) {
646 /* bogus IRQ, process it later */
647 azx_dev->irq_pending = 1;
648 schedule_work(&hda->irq_pending_work);
653 #define display_power(chip, enable) \
654 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
657 * Check whether the current DMA position is acceptable for updating
658 * periods. Returns non-zero if it's OK.
660 * Many HD-audio controllers appear pretty inaccurate about
661 * the update-IRQ timing. The IRQ is issued before actually the
662 * data is processed. So, we need to process it afterwords in a
665 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
667 struct snd_pcm_substream *substream = azx_dev->core.substream;
668 int stream = substream->stream;
672 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
673 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
674 return -1; /* bogus (too early) interrupt */
676 if (chip->get_position[stream])
677 pos = chip->get_position[stream](chip, azx_dev);
678 else { /* use the position buffer as default */
679 pos = azx_get_pos_posbuf(chip, azx_dev);
680 if (!pos || pos == (u32)-1) {
681 dev_info(chip->card->dev,
682 "Invalid position buffer, using LPIB read method instead.\n");
683 chip->get_position[stream] = azx_get_pos_lpib;
684 if (chip->get_position[0] == azx_get_pos_lpib &&
685 chip->get_position[1] == azx_get_pos_lpib)
686 azx_bus(chip)->use_posbuf = false;
687 pos = azx_get_pos_lpib(chip, azx_dev);
688 chip->get_delay[stream] = NULL;
690 chip->get_position[stream] = azx_get_pos_posbuf;
691 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
692 chip->get_delay[stream] = azx_get_delay_from_lpib;
696 if (pos >= azx_dev->core.bufsize)
699 if (WARN_ONCE(!azx_dev->core.period_bytes,
700 "hda-intel: zero azx_dev->period_bytes"))
701 return -1; /* this shouldn't happen! */
702 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
703 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
704 /* NG - it's below the first next period boundary */
705 return chip->bdl_pos_adj ? 0 : -1;
706 azx_dev->core.start_wallclk += wallclk;
707 return 1; /* OK, it's fine */
711 * The work for pending PCM period updates.
713 static void azx_irq_pending_work(struct work_struct *work)
715 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
716 struct azx *chip = &hda->chip;
717 struct hdac_bus *bus = azx_bus(chip);
718 struct hdac_stream *s;
721 if (!hda->irq_pending_warned) {
722 dev_info(chip->card->dev,
723 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
725 hda->irq_pending_warned = 1;
730 spin_lock_irq(&bus->reg_lock);
731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
733 if (!azx_dev->irq_pending ||
737 ok = azx_position_ok(chip, azx_dev);
739 azx_dev->irq_pending = 0;
740 spin_unlock(&bus->reg_lock);
741 snd_pcm_period_elapsed(s->substream);
742 spin_lock(&bus->reg_lock);
744 pending = 0; /* too early */
748 spin_unlock_irq(&bus->reg_lock);
755 /* clear irq_pending flags and assure no on-going workq */
756 static void azx_clear_irq_pending(struct azx *chip)
758 struct hdac_bus *bus = azx_bus(chip);
759 struct hdac_stream *s;
761 spin_lock_irq(&bus->reg_lock);
762 list_for_each_entry(s, &bus->stream_list, list) {
763 struct azx_dev *azx_dev = stream_to_azx_dev(s);
764 azx_dev->irq_pending = 0;
766 spin_unlock_irq(&bus->reg_lock);
769 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
771 struct hdac_bus *bus = azx_bus(chip);
773 if (request_irq(chip->pci->irq, azx_interrupt,
774 chip->msi ? 0 : IRQF_SHARED,
775 chip->card->irq_descr, chip)) {
776 dev_err(chip->card->dev,
777 "unable to grab IRQ %d, disabling device\n",
780 snd_card_disconnect(chip->card);
783 bus->irq = chip->pci->irq;
784 pci_intx(chip->pci, !chip->msi);
788 /* get the current DMA position with correction on VIA chips */
789 static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
798 /* Playback, no problem using link position */
804 * use mod to get the DMA position just like old chipset
806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
809 /* azx_dev->fifo_size can't get FIFO size of in stream.
810 * Get from base address + offset.
812 fifo_size = readw(azx_bus(chip)->remap_addr +
813 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
815 if (azx_dev->insufficient) {
816 /* Link position never gather than FIFO size */
817 if (link_pos <= fifo_size)
820 azx_dev->insufficient = 0;
823 if (link_pos <= fifo_size)
824 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
826 mini_pos = link_pos - fifo_size;
828 /* Find nearest previous boudary */
829 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
830 mod_link_pos = link_pos % azx_dev->core.period_bytes;
831 if (mod_link_pos >= fifo_size)
832 bound_pos = link_pos - mod_link_pos;
833 else if (mod_dma_pos >= mod_mini_pos)
834 bound_pos = mini_pos - mod_mini_pos;
836 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
837 if (bound_pos >= azx_dev->core.bufsize)
841 /* Calculate real DMA position we want */
842 return bound_pos + mod_dma_pos;
845 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
846 struct azx_dev *azx_dev)
848 return _snd_hdac_chip_readl(azx_bus(chip),
849 AZX_REG_VS_SDXDPIB_XBASE +
850 (AZX_REG_VS_SDXDPIB_XINTERVAL *
851 azx_dev->core.index));
854 /* get the current DMA position with correction on SKL+ chips */
855 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
857 /* DPIB register gives a more accurate position for playback */
858 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
859 return azx_skl_get_dpib_pos(chip, azx_dev);
861 /* For capture, we need to read posbuf, but it requires a delay
862 * for the possible boundary overlap; the read of DPIB fetches the
866 azx_skl_get_dpib_pos(chip, azx_dev);
867 return azx_get_pos_posbuf(chip, azx_dev);
871 static DEFINE_MUTEX(card_list_lock);
872 static LIST_HEAD(card_list);
874 static void azx_add_card_list(struct azx *chip)
876 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
877 mutex_lock(&card_list_lock);
878 list_add(&hda->list, &card_list);
879 mutex_unlock(&card_list_lock);
882 static void azx_del_card_list(struct azx *chip)
884 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
885 mutex_lock(&card_list_lock);
886 list_del_init(&hda->list);
887 mutex_unlock(&card_list_lock);
890 /* trigger power-save check at writing parameter */
891 static int param_set_xint(const char *val, const struct kernel_param *kp)
893 struct hda_intel *hda;
895 int prev = power_save;
896 int ret = param_set_int(val, kp);
898 if (ret || prev == power_save)
901 mutex_lock(&card_list_lock);
902 list_for_each_entry(hda, &card_list, list) {
904 if (!hda->probe_continued || chip->disabled)
906 snd_hda_set_power_save(&chip->bus, power_save * 1000);
908 mutex_unlock(&card_list_lock);
915 static bool azx_is_pm_ready(struct snd_card *card)
918 struct hda_intel *hda;
922 chip = card->private_data;
923 hda = container_of(chip, struct hda_intel, chip);
924 if (chip->disabled || hda->init_failed || !chip->running)
929 static void __azx_runtime_suspend(struct azx *chip)
932 azx_enter_link_reset(chip);
933 azx_clear_irq_pending(chip);
934 display_power(chip, false);
937 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
939 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
940 struct hdac_bus *bus = azx_bus(chip);
941 struct hda_codec *codec;
944 display_power(chip, true);
945 if (hda->need_i915_power)
946 snd_hdac_i915_set_bclk(bus);
948 /* Read STATESTS before controller reset */
949 status = azx_readw(chip, STATESTS);
952 hda_intel_init_chip(chip, true);
954 if (status && from_rt) {
955 list_for_each_codec(codec, &chip->bus)
956 if (status & (1 << codec->addr))
957 schedule_delayed_work(&codec->jackpoll_work,
958 codec->jackpoll_interval);
961 /* power down again for link-controlled chips */
962 if (!hda->need_i915_power)
963 display_power(chip, false);
966 #ifdef CONFIG_PM_SLEEP
967 static int azx_suspend(struct device *dev)
969 struct snd_card *card = dev_get_drvdata(dev);
971 struct hdac_bus *bus;
973 if (!azx_is_pm_ready(card))
976 chip = card->private_data;
978 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
979 __azx_runtime_suspend(chip);
981 free_irq(bus->irq, chip);
986 pci_disable_msi(chip->pci);
988 trace_azx_suspend(chip);
992 static int azx_resume(struct device *dev)
994 struct snd_card *card = dev_get_drvdata(dev);
997 if (!azx_is_pm_ready(card))
1000 chip = card->private_data;
1002 if (pci_enable_msi(chip->pci) < 0)
1004 if (azx_acquire_irq(chip, 1) < 0)
1006 __azx_runtime_resume(chip, false);
1007 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1009 trace_azx_resume(chip);
1013 /* put codec down to D3 at hibernation for Intel SKL+;
1014 * otherwise BIOS may still access the codec and screw up the driver
1016 static int azx_freeze_noirq(struct device *dev)
1018 struct snd_card *card = dev_get_drvdata(dev);
1019 struct azx *chip = card->private_data;
1020 struct pci_dev *pci = to_pci_dev(dev);
1022 if (chip->driver_type == AZX_DRIVER_SKL)
1023 pci_set_power_state(pci, PCI_D3hot);
1028 static int azx_thaw_noirq(struct device *dev)
1030 struct snd_card *card = dev_get_drvdata(dev);
1031 struct azx *chip = card->private_data;
1032 struct pci_dev *pci = to_pci_dev(dev);
1034 if (chip->driver_type == AZX_DRIVER_SKL)
1035 pci_set_power_state(pci, PCI_D0);
1039 #endif /* CONFIG_PM_SLEEP */
1041 static int azx_runtime_suspend(struct device *dev)
1043 struct snd_card *card = dev_get_drvdata(dev);
1046 if (!azx_is_pm_ready(card))
1048 chip = card->private_data;
1049 if (!azx_has_pm_runtime(chip))
1052 /* enable controller wake up event */
1053 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1056 __azx_runtime_suspend(chip);
1057 trace_azx_runtime_suspend(chip);
1061 static int azx_runtime_resume(struct device *dev)
1063 struct snd_card *card = dev_get_drvdata(dev);
1066 if (!azx_is_pm_ready(card))
1068 chip = card->private_data;
1069 if (!azx_has_pm_runtime(chip))
1071 __azx_runtime_resume(chip, true);
1073 /* disable controller Wake Up event*/
1074 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1075 ~STATESTS_INT_MASK);
1077 trace_azx_runtime_resume(chip);
1081 static int azx_runtime_idle(struct device *dev)
1083 struct snd_card *card = dev_get_drvdata(dev);
1085 struct hda_intel *hda;
1090 chip = card->private_data;
1091 hda = container_of(chip, struct hda_intel, chip);
1092 if (chip->disabled || hda->init_failed)
1095 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1096 azx_bus(chip)->codec_powered || !chip->running)
1099 /* ELD notification gets broken when HD-audio bus is off */
1100 if (needs_eld_notify_link(hda))
1106 static const struct dev_pm_ops azx_pm = {
1107 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1108 #ifdef CONFIG_PM_SLEEP
1109 .freeze_noirq = azx_freeze_noirq,
1110 .thaw_noirq = azx_thaw_noirq,
1112 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1115 #define AZX_PM_OPS &azx_pm
1117 #define azx_add_card_list(chip) /* NOP */
1118 #define azx_del_card_list(chip) /* NOP */
1119 #define AZX_PM_OPS NULL
1120 #endif /* CONFIG_PM */
1123 static int azx_probe_continue(struct azx *chip);
1125 #ifdef SUPPORT_VGA_SWITCHEROO
1126 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1128 static void azx_vs_set_state(struct pci_dev *pci,
1129 enum vga_switcheroo_state state)
1131 struct snd_card *card = pci_get_drvdata(pci);
1132 struct azx *chip = card->private_data;
1133 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1134 struct hda_codec *codec;
1137 wait_for_completion(&hda->probe_wait);
1138 if (hda->init_failed)
1141 disabled = (state == VGA_SWITCHEROO_OFF);
1142 if (chip->disabled == disabled)
1145 if (!hda->probe_continued) {
1146 chip->disabled = disabled;
1148 dev_info(chip->card->dev,
1149 "Start delayed initialization\n");
1150 if (azx_probe_continue(chip) < 0) {
1151 dev_err(chip->card->dev, "initialization error\n");
1152 hda->init_failed = true;
1156 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1157 disabled ? "Disabling" : "Enabling");
1159 list_for_each_codec(codec, &chip->bus) {
1160 pm_runtime_suspend(hda_codec_dev(codec));
1161 pm_runtime_disable(hda_codec_dev(codec));
1163 pm_runtime_suspend(card->dev);
1164 pm_runtime_disable(card->dev);
1165 /* when we get suspended by vga_switcheroo we end up in D3cold,
1166 * however we have no ACPI handle, so pci/acpi can't put us there,
1167 * put ourselves there */
1168 pci->current_state = PCI_D3cold;
1169 chip->disabled = true;
1170 if (snd_hda_lock_devices(&chip->bus))
1171 dev_warn(chip->card->dev,
1172 "Cannot lock devices!\n");
1174 snd_hda_unlock_devices(&chip->bus);
1175 chip->disabled = false;
1176 pm_runtime_enable(card->dev);
1177 list_for_each_codec(codec, &chip->bus) {
1178 pm_runtime_enable(hda_codec_dev(codec));
1179 pm_runtime_resume(hda_codec_dev(codec));
1185 static bool azx_vs_can_switch(struct pci_dev *pci)
1187 struct snd_card *card = pci_get_drvdata(pci);
1188 struct azx *chip = card->private_data;
1189 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191 wait_for_completion(&hda->probe_wait);
1192 if (hda->init_failed)
1194 if (chip->disabled || !hda->probe_continued)
1196 if (snd_hda_lock_devices(&chip->bus))
1198 snd_hda_unlock_devices(&chip->bus);
1203 * The discrete GPU cannot power down unless the HDA controller runtime
1204 * suspends, so activate runtime PM on codecs even if power_save == 0.
1206 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1208 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1209 struct hda_codec *codec;
1211 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1212 list_for_each_codec(codec, &chip->bus)
1213 codec->auto_runtime_pm = 1;
1214 /* reset the power save setup */
1216 set_default_power_save(chip);
1220 static void azx_vs_gpu_bound(struct pci_dev *pci,
1221 enum vga_switcheroo_client_id client_id)
1223 struct snd_card *card = pci_get_drvdata(pci);
1224 struct azx *chip = card->private_data;
1225 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1227 if (client_id == VGA_SWITCHEROO_DIS)
1228 hda->need_eld_notify_link = 0;
1229 setup_vga_switcheroo_runtime_pm(chip);
1232 static void init_vga_switcheroo(struct azx *chip)
1234 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1235 struct pci_dev *p = get_bound_vga(chip->pci);
1237 dev_info(chip->card->dev,
1238 "Handle vga_switcheroo audio client\n");
1239 hda->use_vga_switcheroo = 1;
1240 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1241 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1246 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1247 .set_gpu_state = azx_vs_set_state,
1248 .can_switch = azx_vs_can_switch,
1249 .gpu_bound = azx_vs_gpu_bound,
1252 static int register_vga_switcheroo(struct azx *chip)
1254 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1258 if (!hda->use_vga_switcheroo)
1261 p = get_bound_vga(chip->pci);
1262 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1267 hda->vga_switcheroo_registered = 1;
1272 #define init_vga_switcheroo(chip) /* NOP */
1273 #define register_vga_switcheroo(chip) 0
1274 #define check_hdmi_disabled(pci) false
1275 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1276 #endif /* SUPPORT_VGA_SWITCHER */
1281 static int azx_free(struct azx *chip)
1283 struct pci_dev *pci = chip->pci;
1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285 struct hdac_bus *bus = azx_bus(chip);
1287 if (azx_has_pm_runtime(chip) && chip->running)
1288 pm_runtime_get_noresume(&pci->dev);
1291 azx_del_card_list(chip);
1293 hda->init_failed = 1; /* to be sure */
1294 complete_all(&hda->probe_wait);
1296 if (use_vga_switcheroo(hda)) {
1297 if (chip->disabled && hda->probe_continued)
1298 snd_hda_unlock_devices(&chip->bus);
1299 if (hda->vga_switcheroo_registered)
1300 vga_switcheroo_unregister_client(chip->pci);
1303 if (bus->chip_init) {
1304 azx_clear_irq_pending(chip);
1305 azx_stop_all_streams(chip);
1306 azx_stop_chip(chip);
1310 free_irq(bus->irq, (void*)chip);
1312 pci_disable_msi(chip->pci);
1313 iounmap(bus->remap_addr);
1315 azx_free_stream_pages(chip);
1316 azx_free_streams(chip);
1317 snd_hdac_bus_exit(bus);
1319 if (chip->region_requested)
1320 pci_release_regions(chip->pci);
1322 pci_disable_device(chip->pci);
1323 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1324 release_firmware(chip->fw);
1326 display_power(chip, false);
1328 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1329 snd_hdac_i915_exit(bus);
1335 static int azx_dev_disconnect(struct snd_device *device)
1337 struct azx *chip = device->device_data;
1339 chip->bus.shutdown = 1;
1343 static int azx_dev_free(struct snd_device *device)
1345 return azx_free(device->device_data);
1348 #ifdef SUPPORT_VGA_SWITCHEROO
1350 * Check of disabled HDMI controller by vga_switcheroo
1352 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1356 /* check only discrete GPU */
1357 switch (pci->vendor) {
1358 case PCI_VENDOR_ID_ATI:
1359 case PCI_VENDOR_ID_AMD:
1360 case PCI_VENDOR_ID_NVIDIA:
1361 if (pci->devfn == 1) {
1362 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1363 pci->bus->number, 0);
1365 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1375 static bool check_hdmi_disabled(struct pci_dev *pci)
1377 bool vga_inactive = false;
1378 struct pci_dev *p = get_bound_vga(pci);
1381 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1382 vga_inactive = true;
1385 return vga_inactive;
1387 #endif /* SUPPORT_VGA_SWITCHEROO */
1390 * white/black-listing for position_fix
1392 static struct snd_pci_quirk position_fix_list[] = {
1393 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1394 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1395 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1396 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1397 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1398 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1399 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1400 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1401 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1402 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1403 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1404 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1405 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1406 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1410 static int check_position_fix(struct azx *chip, int fix)
1412 const struct snd_pci_quirk *q;
1417 case POS_FIX_POSBUF:
1418 case POS_FIX_VIACOMBO:
1424 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1426 dev_info(chip->card->dev,
1427 "position_fix set to %d for device %04x:%04x\n",
1428 q->value, q->subvendor, q->subdevice);
1432 /* Check VIA/ATI HD Audio Controller exist */
1433 if (chip->driver_type == AZX_DRIVER_VIA) {
1434 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1435 return POS_FIX_VIACOMBO;
1437 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1438 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1439 return POS_FIX_LPIB;
1441 if (chip->driver_type == AZX_DRIVER_SKL) {
1442 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1445 return POS_FIX_AUTO;
1448 static void assign_position_fix(struct azx *chip, int fix)
1450 static azx_get_pos_callback_t callbacks[] = {
1451 [POS_FIX_AUTO] = NULL,
1452 [POS_FIX_LPIB] = azx_get_pos_lpib,
1453 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1454 [POS_FIX_VIACOMBO] = azx_via_get_position,
1455 [POS_FIX_COMBO] = azx_get_pos_lpib,
1456 [POS_FIX_SKL] = azx_get_pos_skl,
1459 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1461 /* combo mode uses LPIB only for playback */
1462 if (fix == POS_FIX_COMBO)
1463 chip->get_position[1] = NULL;
1465 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1466 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1467 chip->get_delay[0] = chip->get_delay[1] =
1468 azx_get_delay_from_lpib;
1474 * black-lists for probe_mask
1476 static struct snd_pci_quirk probe_mask_list[] = {
1477 /* Thinkpad often breaks the controller communication when accessing
1478 * to the non-working (or non-existing) modem codec slot.
1480 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1481 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1482 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1484 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1485 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1486 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1487 /* forced codec slots */
1488 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1489 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1490 /* WinFast VP200 H (Teradici) user reported broken communication */
1491 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1495 #define AZX_FORCE_CODEC_MASK 0x100
1497 static void check_probe_mask(struct azx *chip, int dev)
1499 const struct snd_pci_quirk *q;
1501 chip->codec_probe_mask = probe_mask[dev];
1502 if (chip->codec_probe_mask == -1) {
1503 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1505 dev_info(chip->card->dev,
1506 "probe_mask set to 0x%x for device %04x:%04x\n",
1507 q->value, q->subvendor, q->subdevice);
1508 chip->codec_probe_mask = q->value;
1512 /* check forced option */
1513 if (chip->codec_probe_mask != -1 &&
1514 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1515 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1516 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1517 (int)azx_bus(chip)->codec_mask);
1522 * white/black-list for enable_msi
1524 static struct snd_pci_quirk msi_black_list[] = {
1525 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1526 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1527 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1528 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1529 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1530 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1531 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1532 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1533 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1534 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1538 static void check_msi(struct azx *chip)
1540 const struct snd_pci_quirk *q;
1542 if (enable_msi >= 0) {
1543 chip->msi = !!enable_msi;
1546 chip->msi = 1; /* enable MSI as default */
1547 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1549 dev_info(chip->card->dev,
1550 "msi for device %04x:%04x set to %d\n",
1551 q->subvendor, q->subdevice, q->value);
1552 chip->msi = q->value;
1556 /* NVidia chipsets seem to cause troubles with MSI */
1557 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1558 dev_info(chip->card->dev, "Disabling MSI\n");
1563 /* check the snoop mode availability */
1564 static void azx_check_snoop_available(struct azx *chip)
1566 int snoop = hda_snoop;
1569 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1570 snoop ? "snoop" : "non-snoop");
1571 chip->snoop = snoop;
1572 chip->uc_buffer = !snoop;
1577 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1578 chip->driver_type == AZX_DRIVER_VIA) {
1579 /* force to non-snoop mode for a new VIA controller
1583 pci_read_config_byte(chip->pci, 0x42, &val);
1584 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1585 chip->pci->revision == 0x20))
1589 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1592 chip->snoop = snoop;
1594 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1595 /* C-Media requires non-cached pages only for CORB/RIRB */
1596 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1597 chip->uc_buffer = true;
1601 static void azx_probe_work(struct work_struct *work)
1603 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1604 azx_probe_continue(&hda->chip);
1607 static int default_bdl_pos_adj(struct azx *chip)
1609 /* some exceptions: Atoms seem problematic with value 1 */
1610 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1611 switch (chip->pci->device) {
1612 case 0x0f04: /* Baytrail */
1613 case 0x2284: /* Braswell */
1618 switch (chip->driver_type) {
1619 case AZX_DRIVER_ICH:
1620 case AZX_DRIVER_PCH:
1630 static const struct hdac_io_ops pci_hda_io_ops;
1631 static const struct hda_controller_ops pci_hda_ops;
1633 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1634 int dev, unsigned int driver_caps,
1637 static struct snd_device_ops ops = {
1638 .dev_disconnect = azx_dev_disconnect,
1639 .dev_free = azx_dev_free,
1641 struct hda_intel *hda;
1647 err = pci_enable_device(pci);
1651 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1653 pci_disable_device(pci);
1658 mutex_init(&chip->open_mutex);
1661 chip->ops = &pci_hda_ops;
1662 chip->driver_caps = driver_caps;
1663 chip->driver_type = driver_caps & 0xff;
1665 chip->dev_index = dev;
1666 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1667 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1668 INIT_LIST_HEAD(&chip->pcm_list);
1669 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1670 INIT_LIST_HEAD(&hda->list);
1671 init_vga_switcheroo(chip);
1672 init_completion(&hda->probe_wait);
1674 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1676 check_probe_mask(chip, dev);
1678 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1679 chip->fallback_to_single_cmd = 1;
1680 else /* explicitly set to single_cmd or not */
1681 chip->single_cmd = single_cmd;
1683 azx_check_snoop_available(chip);
1685 if (bdl_pos_adj[dev] < 0)
1686 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1688 chip->bdl_pos_adj = bdl_pos_adj[dev];
1690 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1691 if (IS_CFL(pci) || IS_CNL(pci))
1692 chip->polling_mode = 1;
1694 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1697 pci_disable_device(pci);
1701 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1702 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1703 chip->bus.needs_damn_long_delay = 1;
1706 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1708 dev_err(card->dev, "Error creating device [card]!\n");
1713 /* continue probing in work context as may trigger request module */
1714 INIT_WORK(&hda->probe_work, azx_probe_work);
1721 static int azx_first_init(struct azx *chip)
1723 int dev = chip->dev_index;
1724 struct pci_dev *pci = chip->pci;
1725 struct snd_card *card = chip->card;
1726 struct hdac_bus *bus = azx_bus(chip);
1728 unsigned short gcap;
1729 unsigned int dma_bits = 64;
1731 #if BITS_PER_LONG != 64
1732 /* Fix up base address on ULI M5461 */
1733 if (chip->driver_type == AZX_DRIVER_ULI) {
1735 pci_read_config_word(pci, 0x40, &tmp3);
1736 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1737 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1741 err = pci_request_regions(pci, "ICH HD audio");
1744 chip->region_requested = 1;
1746 bus->addr = pci_resource_start(pci, 0);
1747 bus->remap_addr = pci_ioremap_bar(pci, 0);
1748 if (bus->remap_addr == NULL) {
1749 dev_err(card->dev, "ioremap error\n");
1753 if (chip->driver_type == AZX_DRIVER_SKL)
1754 snd_hdac_bus_parse_capabilities(bus);
1757 * Some Intel CPUs has always running timer (ART) feature and
1758 * controller may have Global time sync reporting capability, so
1759 * check both of these before declaring synchronized time reporting
1760 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1762 chip->gts_present = false;
1765 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1766 chip->gts_present = true;
1770 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1771 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1772 pci->no_64bit_msi = true;
1774 if (pci_enable_msi(pci) < 0)
1778 pci_set_master(pci);
1779 synchronize_irq(bus->irq);
1781 gcap = azx_readw(chip, GCAP);
1782 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1784 /* AMD devices support 40 or 48bit DMA, take the safe one */
1785 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1788 /* disable SB600 64bit support for safety */
1789 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1790 struct pci_dev *p_smbus;
1792 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1793 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1796 if (p_smbus->revision < 0x30)
1797 gcap &= ~AZX_GCAP_64OK;
1798 pci_dev_put(p_smbus);
1802 /* NVidia hardware normally only supports up to 40 bits of DMA */
1803 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1806 /* disable 64bit DMA address on some devices */
1807 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1808 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1809 gcap &= ~AZX_GCAP_64OK;
1812 /* disable buffer size rounding to 128-byte multiples if supported */
1813 if (align_buffer_size >= 0)
1814 chip->align_buffer_size = !!align_buffer_size;
1816 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1817 chip->align_buffer_size = 0;
1819 chip->align_buffer_size = 1;
1822 /* allow 64bit DMA address if supported by H/W */
1823 if (!(gcap & AZX_GCAP_64OK))
1825 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1826 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1828 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1829 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1832 /* read number of streams from GCAP register instead of using
1835 chip->capture_streams = (gcap >> 8) & 0x0f;
1836 chip->playback_streams = (gcap >> 12) & 0x0f;
1837 if (!chip->playback_streams && !chip->capture_streams) {
1838 /* gcap didn't give any info, switching to old method */
1840 switch (chip->driver_type) {
1841 case AZX_DRIVER_ULI:
1842 chip->playback_streams = ULI_NUM_PLAYBACK;
1843 chip->capture_streams = ULI_NUM_CAPTURE;
1845 case AZX_DRIVER_ATIHDMI:
1846 case AZX_DRIVER_ATIHDMI_NS:
1847 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1848 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1850 case AZX_DRIVER_GENERIC:
1852 chip->playback_streams = ICH6_NUM_PLAYBACK;
1853 chip->capture_streams = ICH6_NUM_CAPTURE;
1857 chip->capture_index_offset = 0;
1858 chip->playback_index_offset = chip->capture_streams;
1859 chip->num_streams = chip->playback_streams + chip->capture_streams;
1861 /* sanity check for the SDxCTL.STRM field overflow */
1862 if (chip->num_streams > 15 &&
1863 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1864 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1865 "forcing separate stream tags", chip->num_streams);
1866 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1869 /* initialize streams */
1870 err = azx_init_streams(chip);
1874 err = azx_alloc_stream_pages(chip);
1878 /* initialize chip */
1881 snd_hdac_i915_set_bclk(bus);
1883 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1885 /* codec detection */
1886 if (!azx_bus(chip)->codec_mask) {
1887 dev_err(card->dev, "no codecs found!\n");
1891 if (azx_acquire_irq(chip, 0) < 0)
1894 strcpy(card->driver, "HDA-Intel");
1895 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1896 sizeof(card->shortname));
1897 snprintf(card->longname, sizeof(card->longname),
1898 "%s at 0x%lx irq %i",
1899 card->shortname, bus->addr, bus->irq);
1904 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1905 /* callback from request_firmware_nowait() */
1906 static void azx_firmware_cb(const struct firmware *fw, void *context)
1908 struct snd_card *card = context;
1909 struct azx *chip = card->private_data;
1910 struct pci_dev *pci = chip->pci;
1913 dev_err(card->dev, "Cannot load firmware, aborting\n");
1918 if (!chip->disabled) {
1919 /* continue probing */
1920 if (azx_probe_continue(chip))
1926 snd_card_free(card);
1927 pci_set_drvdata(pci, NULL);
1932 * HDA controller ops.
1935 /* PCI register access. */
1936 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1938 writel(value, addr);
1941 static u32 pci_azx_readl(u32 __iomem *addr)
1946 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1948 writew(value, addr);
1951 static u16 pci_azx_readw(u16 __iomem *addr)
1956 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1958 writeb(value, addr);
1961 static u8 pci_azx_readb(u8 __iomem *addr)
1966 static int disable_msi_reset_irq(struct azx *chip)
1968 struct hdac_bus *bus = azx_bus(chip);
1971 free_irq(bus->irq, chip);
1973 pci_disable_msi(chip->pci);
1975 err = azx_acquire_irq(chip, 1);
1982 /* DMA page allocation helpers. */
1983 static int dma_alloc_pages(struct hdac_bus *bus,
1986 struct snd_dma_buffer *buf)
1988 struct azx *chip = bus_to_azx(bus);
1990 if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
1991 type = SNDRV_DMA_TYPE_DEV_UC;
1992 return snd_dma_alloc_pages(type, bus->dev, size, buf);
1995 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1997 snd_dma_free_pages(buf);
2000 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2001 struct vm_area_struct *area)
2004 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2005 struct azx *chip = apcm->chip;
2006 if (chip->uc_buffer)
2007 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2011 static const struct hdac_io_ops pci_hda_io_ops = {
2012 .reg_writel = pci_azx_writel,
2013 .reg_readl = pci_azx_readl,
2014 .reg_writew = pci_azx_writew,
2015 .reg_readw = pci_azx_readw,
2016 .reg_writeb = pci_azx_writeb,
2017 .reg_readb = pci_azx_readb,
2018 .dma_alloc_pages = dma_alloc_pages,
2019 .dma_free_pages = dma_free_pages,
2022 static const struct hda_controller_ops pci_hda_ops = {
2023 .disable_msi_reset_irq = disable_msi_reset_irq,
2024 .pcm_mmap_prepare = pcm_mmap_prepare,
2025 .position_check = azx_position_check,
2028 static int azx_probe(struct pci_dev *pci,
2029 const struct pci_device_id *pci_id)
2032 struct snd_card *card;
2033 struct hda_intel *hda;
2035 bool schedule_probe;
2038 if (dev >= SNDRV_CARDS)
2045 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2048 dev_err(&pci->dev, "Error creating card!\n");
2052 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2055 card->private_data = chip;
2056 hda = container_of(chip, struct hda_intel, chip);
2058 pci_set_drvdata(pci, card);
2060 err = register_vga_switcheroo(chip);
2062 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2066 if (check_hdmi_disabled(pci)) {
2067 dev_info(card->dev, "VGA controller is disabled\n");
2068 dev_info(card->dev, "Delaying initialization\n");
2069 chip->disabled = true;
2072 schedule_probe = !chip->disabled;
2074 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2075 if (patch[dev] && *patch[dev]) {
2076 dev_info(card->dev, "Applying patch firmware '%s'\n",
2078 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2079 &pci->dev, GFP_KERNEL, card,
2083 schedule_probe = false; /* continued in azx_firmware_cb() */
2085 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2087 #ifndef CONFIG_SND_HDA_I915
2088 if (CONTROLLER_IN_GPU(pci))
2089 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2093 schedule_work(&hda->probe_work);
2097 complete_all(&hda->probe_wait);
2101 snd_card_free(card);
2106 /* On some boards setting power_save to a non 0 value leads to clicking /
2107 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2108 * figure out how to avoid these sounds, but that is not always feasible.
2109 * So we keep a list of devices where we disable powersaving as its known
2110 * to causes problems on these devices.
2112 static struct snd_pci_quirk power_save_blacklist[] = {
2113 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2114 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2115 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2116 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2117 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2118 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2119 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2120 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2121 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2122 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2123 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2124 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2125 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2126 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2127 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2128 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2129 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2130 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2131 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2132 /* https://bugs.launchpad.net/bugs/1821663 */
2133 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2134 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2135 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2136 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2137 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2138 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2139 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2140 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2141 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2142 /* https://bugs.launchpad.net/bugs/1821663 */
2143 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2146 #endif /* CONFIG_PM */
2148 static void set_default_power_save(struct azx *chip)
2150 int val = power_save;
2154 const struct snd_pci_quirk *q;
2156 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2158 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2159 q->subvendor, q->subdevice);
2163 #endif /* CONFIG_PM */
2164 snd_hda_set_power_save(&chip->bus, val * 1000);
2167 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2168 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2169 [AZX_DRIVER_NVIDIA] = 8,
2170 [AZX_DRIVER_TERA] = 1,
2173 static int azx_probe_continue(struct azx *chip)
2175 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2176 struct hdac_bus *bus = azx_bus(chip);
2177 struct pci_dev *pci = chip->pci;
2178 int dev = chip->dev_index;
2181 to_hda_bus(bus)->bus_probing = 1;
2182 hda->probe_continued = 1;
2184 /* bind with i915 if needed */
2185 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2186 err = snd_hdac_i915_init(bus);
2188 /* if the controller is bound only with HDMI/DP
2189 * (for HSW and BDW), we need to abort the probe;
2190 * for other chips, still continue probing as other
2191 * codecs can be on the same link.
2193 if (CONTROLLER_IN_GPU(pci)) {
2194 dev_err(chip->card->dev,
2195 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2198 /* don't bother any longer */
2199 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2203 /* HSW/BDW controllers need this power */
2204 if (CONTROLLER_IN_GPU(pci))
2205 hda->need_i915_power = 1;
2208 /* Request display power well for the HDA controller or codec. For
2209 * Haswell/Broadwell, both the display HDA controller and codec need
2210 * this power. For other platforms, like Baytrail/Braswell, only the
2211 * display codec needs the power and it can be released after probe.
2213 display_power(chip, true);
2215 err = azx_first_init(chip);
2219 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2220 chip->beep_mode = beep_mode[dev];
2223 /* create codec instances */
2224 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2228 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2230 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2235 release_firmware(chip->fw); /* no longer needed */
2240 if ((probe_only[dev] & 1) == 0) {
2241 err = azx_codec_configure(chip);
2246 err = snd_card_register(chip->card);
2250 setup_vga_switcheroo_runtime_pm(chip);
2253 azx_add_card_list(chip);
2255 set_default_power_save(chip);
2257 if (azx_has_pm_runtime(chip))
2258 pm_runtime_put_autosuspend(&pci->dev);
2261 if (err < 0 || !hda->need_i915_power)
2262 display_power(chip, false);
2264 hda->init_failed = 1;
2265 complete_all(&hda->probe_wait);
2266 to_hda_bus(bus)->bus_probing = 0;
2270 static void azx_remove(struct pci_dev *pci)
2272 struct snd_card *card = pci_get_drvdata(pci);
2274 struct hda_intel *hda;
2277 /* cancel the pending probing work */
2278 chip = card->private_data;
2279 hda = container_of(chip, struct hda_intel, chip);
2280 /* FIXME: below is an ugly workaround.
2281 * Both device_release_driver() and driver_probe_device()
2282 * take *both* the device's and its parent's lock before
2283 * calling the remove() and probe() callbacks. The codec
2284 * probe takes the locks of both the codec itself and its
2285 * parent, i.e. the PCI controller dev. Meanwhile, when
2286 * the PCI controller is unbound, it takes its lock, too
2287 * ==> ouch, a deadlock!
2288 * As a workaround, we unlock temporarily here the controller
2289 * device during cancel_work_sync() call.
2291 device_unlock(&pci->dev);
2292 cancel_work_sync(&hda->probe_work);
2293 device_lock(&pci->dev);
2295 snd_card_free(card);
2299 static void azx_shutdown(struct pci_dev *pci)
2301 struct snd_card *card = pci_get_drvdata(pci);
2306 chip = card->private_data;
2307 if (chip && chip->running)
2308 azx_stop_chip(chip);
2312 static const struct pci_device_id azx_ids[] = {
2314 { PCI_DEVICE(0x8086, 0x1c20),
2315 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2317 { PCI_DEVICE(0x8086, 0x1d20),
2318 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2320 { PCI_DEVICE(0x8086, 0x1e20),
2321 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2323 { PCI_DEVICE(0x8086, 0x8c20),
2324 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2326 { PCI_DEVICE(0x8086, 0x8ca0),
2327 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2329 { PCI_DEVICE(0x8086, 0x8d20),
2330 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2331 { PCI_DEVICE(0x8086, 0x8d21),
2332 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2334 { PCI_DEVICE(0x8086, 0xa1f0),
2335 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2336 { PCI_DEVICE(0x8086, 0xa270),
2337 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2339 { PCI_DEVICE(0x8086, 0x9c20),
2340 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2342 { PCI_DEVICE(0x8086, 0x9c21),
2343 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2344 /* Wildcat Point-LP */
2345 { PCI_DEVICE(0x8086, 0x9ca0),
2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2348 { PCI_DEVICE(0x8086, 0xa170),
2349 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2350 /* Sunrise Point-LP */
2351 { PCI_DEVICE(0x8086, 0x9d70),
2352 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2354 { PCI_DEVICE(0x8086, 0xa171),
2355 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2357 { PCI_DEVICE(0x8086, 0x9d71),
2358 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2360 { PCI_DEVICE(0x8086, 0xa2f0),
2361 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2363 { PCI_DEVICE(0x8086, 0xa348),
2364 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2366 { PCI_DEVICE(0x8086, 0x9dc8),
2367 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2369 { PCI_DEVICE(0x8086, 0x02C8),
2370 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2372 { PCI_DEVICE(0x8086, 0x06C8),
2373 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2375 { PCI_DEVICE(0x8086, 0x34c8),
2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2377 /* Broxton-P(Apollolake) */
2378 { PCI_DEVICE(0x8086, 0x5a98),
2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2381 { PCI_DEVICE(0x8086, 0x1a98),
2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2384 { PCI_DEVICE(0x8086, 0x3198),
2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2387 { PCI_DEVICE(0x8086, 0x0a0c),
2388 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2389 { PCI_DEVICE(0x8086, 0x0c0c),
2390 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2391 { PCI_DEVICE(0x8086, 0x0d0c),
2392 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2394 { PCI_DEVICE(0x8086, 0x160c),
2395 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2397 { PCI_DEVICE(0x8086, 0x3b56),
2398 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2400 { PCI_DEVICE(0x8086, 0x811b),
2401 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2403 { PCI_DEVICE(0x8086, 0x080a),
2404 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2406 { PCI_DEVICE(0x8086, 0x0f04),
2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2409 { PCI_DEVICE(0x8086, 0x2284),
2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2412 { PCI_DEVICE(0x8086, 0x2668),
2413 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2415 { PCI_DEVICE(0x8086, 0x27d8),
2416 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2418 { PCI_DEVICE(0x8086, 0x269a),
2419 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2421 { PCI_DEVICE(0x8086, 0x284b),
2422 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2424 { PCI_DEVICE(0x8086, 0x293e),
2425 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2427 { PCI_DEVICE(0x8086, 0x293f),
2428 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2430 { PCI_DEVICE(0x8086, 0x3a3e),
2431 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2433 { PCI_DEVICE(0x8086, 0x3a6e),
2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2436 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2437 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2438 .class_mask = 0xffffff,
2439 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2440 /* ATI SB 450/600/700/800/900 */
2441 { PCI_DEVICE(0x1002, 0x437b),
2442 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2443 { PCI_DEVICE(0x1002, 0x4383),
2444 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2446 { PCI_DEVICE(0x1022, 0x780d),
2447 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2449 { PCI_DEVICE(0x1022, 0x157a),
2450 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2451 AZX_DCAPS_PM_RUNTIME },
2453 { PCI_DEVICE(0x1022, 0x15e3),
2454 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2455 AZX_DCAPS_PM_RUNTIME },
2457 { PCI_DEVICE(0x1002, 0x0002),
2458 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2459 { PCI_DEVICE(0x1002, 0x1308),
2460 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2461 { PCI_DEVICE(0x1002, 0x157a),
2462 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2463 { PCI_DEVICE(0x1002, 0x15b3),
2464 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2465 { PCI_DEVICE(0x1002, 0x793b),
2466 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2467 { PCI_DEVICE(0x1002, 0x7919),
2468 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2469 { PCI_DEVICE(0x1002, 0x960f),
2470 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2471 { PCI_DEVICE(0x1002, 0x970f),
2472 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2473 { PCI_DEVICE(0x1002, 0x9840),
2474 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2475 { PCI_DEVICE(0x1002, 0xaa00),
2476 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2477 { PCI_DEVICE(0x1002, 0xaa08),
2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2479 { PCI_DEVICE(0x1002, 0xaa10),
2480 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2481 { PCI_DEVICE(0x1002, 0xaa18),
2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2483 { PCI_DEVICE(0x1002, 0xaa20),
2484 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2485 { PCI_DEVICE(0x1002, 0xaa28),
2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2487 { PCI_DEVICE(0x1002, 0xaa30),
2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2489 { PCI_DEVICE(0x1002, 0xaa38),
2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2491 { PCI_DEVICE(0x1002, 0xaa40),
2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2493 { PCI_DEVICE(0x1002, 0xaa48),
2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(0x1002, 0xaa50),
2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2497 { PCI_DEVICE(0x1002, 0xaa58),
2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2499 { PCI_DEVICE(0x1002, 0xaa60),
2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2501 { PCI_DEVICE(0x1002, 0xaa68),
2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503 { PCI_DEVICE(0x1002, 0xaa80),
2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505 { PCI_DEVICE(0x1002, 0xaa88),
2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2507 { PCI_DEVICE(0x1002, 0xaa90),
2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2509 { PCI_DEVICE(0x1002, 0xaa98),
2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2511 { PCI_DEVICE(0x1002, 0x9902),
2512 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2513 { PCI_DEVICE(0x1002, 0xaaa0),
2514 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2515 { PCI_DEVICE(0x1002, 0xaaa8),
2516 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2517 { PCI_DEVICE(0x1002, 0xaab0),
2518 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2519 { PCI_DEVICE(0x1002, 0xaac0),
2520 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2521 { PCI_DEVICE(0x1002, 0xaac8),
2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2523 { PCI_DEVICE(0x1002, 0xaad8),
2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2525 { PCI_DEVICE(0x1002, 0xaae8),
2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2527 { PCI_DEVICE(0x1002, 0xaae0),
2528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2529 { PCI_DEVICE(0x1002, 0xaaf0),
2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2531 /* VIA VT8251/VT8237A */
2532 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2533 /* VIA GFX VT7122/VX900 */
2534 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2535 /* VIA GFX VT6122/VX11 */
2536 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2538 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2540 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2542 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2543 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2544 .class_mask = 0xffffff,
2545 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2547 { PCI_DEVICE(0x6549, 0x1200),
2548 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2549 { PCI_DEVICE(0x6549, 0x2200),
2550 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2551 /* Creative X-Fi (CA0110-IBG) */
2553 { PCI_DEVICE(0x1102, 0x0010),
2554 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2555 { PCI_DEVICE(0x1102, 0x0012),
2556 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2557 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2558 /* the following entry conflicts with snd-ctxfi driver,
2559 * as ctxfi driver mutates from HD-audio to native mode with
2560 * a special command sequence.
2562 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2563 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2564 .class_mask = 0xffffff,
2565 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2566 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2568 /* this entry seems still valid -- i.e. without emu20kx chip */
2569 { PCI_DEVICE(0x1102, 0x0009),
2570 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2571 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2574 { PCI_DEVICE(0x13f6, 0x5011),
2575 .driver_data = AZX_DRIVER_CMEDIA |
2576 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2578 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2579 /* VMware HDAudio */
2580 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2581 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2582 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2583 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2584 .class_mask = 0xffffff,
2585 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2586 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2587 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2588 .class_mask = 0xffffff,
2589 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2592 MODULE_DEVICE_TABLE(pci, azx_ids);
2594 /* pci_driver definition */
2595 static struct pci_driver azx_driver = {
2596 .name = KBUILD_MODNAME,
2597 .id_table = azx_ids,
2599 .remove = azx_remove,
2600 .shutdown = azx_shutdown,
2606 module_pci_driver(azx_driver);