3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
57 ((codec)->core.vendor_id == 0x80862800))
58 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
59 || is_skylake(codec) || is_broxton(codec) \
60 || is_kabylake(codec)) || is_geminilake(codec)
62 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
63 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
64 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
66 struct hdmi_spec_per_cvt {
69 unsigned int channels_min;
70 unsigned int channels_max;
76 /* max. connections to a widget */
77 #define HDA_MAX_CONNECTIONS 32
79 struct hdmi_spec_per_pin {
82 /* pin idx, different device entries on the same pin use the same idx */
85 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
89 struct hda_codec *codec;
90 struct hdmi_eld sink_eld;
92 struct delayed_work work;
93 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
94 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
96 bool setup; /* the stream has been set up by prepare callback */
97 int channels; /* current number of channels */
99 bool chmap_set; /* channel-map override by ALSA API? */
100 unsigned char chmap[8]; /* ALSA API channel-map */
101 #ifdef CONFIG_SND_PROC_FS
102 struct snd_info_entry *proc_entry;
106 /* operations used by generic code that can be overridden by patches */
108 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
109 unsigned char *buf, int *eld_size);
111 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int ca, int active_channels, int conn_type);
114 /* enable/disable HBR (HD passthrough) */
115 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
117 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
118 hda_nid_t pin_nid, u32 stream_tag, int format);
120 void (*pin_cvt_fixup)(struct hda_codec *codec,
121 struct hdmi_spec_per_pin *per_pin,
127 struct snd_jack *jack;
128 struct snd_kcontrol *eld_ctl;
133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
134 hda_nid_t cvt_nids[4]; /* only for haswell fix */
137 * num_pins is the number of virtual pins
138 * for example, there are 3 pins, and each pin
139 * has 4 device entries, then the num_pins is 12
143 * num_nids is the number of real pins
144 * In the above example, num_nids is 3
148 * dev_num is the number of device entries
150 * In the above example, dev_num is 4
153 struct snd_array pins; /* struct hdmi_spec_per_pin */
154 struct hdmi_pcm pcm_rec[16];
155 struct mutex pcm_lock;
156 /* pcm_bitmap means which pcms have been assigned to pins*/
157 unsigned long pcm_bitmap;
158 int pcm_used; /* counter of pcm_rec[] */
159 /* bitmap shows whether the pcm is opened in user space
160 * bit 0 means the first playback PCM (PCM3);
161 * bit 1 means the second playback PCM, and so on.
163 unsigned long pcm_in_use;
165 struct hdmi_eld temp_eld;
171 * Non-generic VIA/NVIDIA specific
173 struct hda_multi_out multiout;
174 struct hda_pcm_stream pcm_playback;
176 /* i915/powerwell (Haswell+/Valleyview+) specific */
177 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
178 struct i915_audio_component_audio_ops i915_audio_ops;
180 struct hdac_chmap chmap;
181 hda_nid_t vendor_nid;
184 #ifdef CONFIG_SND_HDA_I915
185 static inline bool codec_has_acomp(struct hda_codec *codec)
187 struct hdmi_spec *spec = codec->spec;
188 return spec->use_acomp_notifier;
191 #define codec_has_acomp(codec) false
194 struct hdmi_audio_infoframe {
201 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
205 u8 LFEPBL01_LSV36_DM_INH7;
208 struct dp_audio_infoframe {
211 u8 ver; /* 0x11 << 2 */
213 u8 CC02_CT47; /* match with HDMI infoframe from this on */
217 u8 LFEPBL01_LSV36_DM_INH7;
220 union audio_infoframe {
221 struct hdmi_audio_infoframe hdmi;
222 struct dp_audio_infoframe dp;
230 #define get_pin(spec, idx) \
231 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
232 #define get_cvt(spec, idx) \
233 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
234 /* obtain hdmi_pcm object assigned to idx */
235 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
236 /* obtain hda_pcm object assigned to idx */
237 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
239 static int pin_id_to_pin_index(struct hda_codec *codec,
240 hda_nid_t pin_nid, int dev_id)
242 struct hdmi_spec *spec = codec->spec;
244 struct hdmi_spec_per_pin *per_pin;
247 * (dev_id == -1) means it is NON-MST pin
248 * return the first virtual pin on this port
253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
254 per_pin = get_pin(spec, pin_idx);
255 if ((per_pin->pin_nid == pin_nid) &&
256 (per_pin->dev_id == dev_id))
260 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
264 static int hinfo_to_pcm_index(struct hda_codec *codec,
265 struct hda_pcm_stream *hinfo)
267 struct hdmi_spec *spec = codec->spec;
270 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
271 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
274 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
278 static int hinfo_to_pin_index(struct hda_codec *codec,
279 struct hda_pcm_stream *hinfo)
281 struct hdmi_spec *spec = codec->spec;
282 struct hdmi_spec_per_pin *per_pin;
285 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
286 per_pin = get_pin(spec, pin_idx);
288 per_pin->pcm->pcm->stream == hinfo)
292 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
296 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
300 struct hdmi_spec_per_pin *per_pin;
302 for (i = 0; i < spec->num_pins; i++) {
303 per_pin = get_pin(spec, i);
304 if (per_pin->pcm_idx == pcm_idx)
310 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
312 struct hdmi_spec *spec = codec->spec;
315 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
316 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
319 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
323 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
324 struct snd_ctl_elem_info *uinfo)
326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
327 struct hdmi_spec *spec = codec->spec;
328 struct hdmi_spec_per_pin *per_pin;
329 struct hdmi_eld *eld;
332 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
334 pcm_idx = kcontrol->private_value;
335 mutex_lock(&spec->pcm_lock);
336 per_pin = pcm_idx_to_pin(spec, pcm_idx);
338 /* no pin is bound to the pcm */
340 mutex_unlock(&spec->pcm_lock);
343 eld = &per_pin->sink_eld;
344 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
345 mutex_unlock(&spec->pcm_lock);
350 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
353 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
354 struct hdmi_spec *spec = codec->spec;
355 struct hdmi_spec_per_pin *per_pin;
356 struct hdmi_eld *eld;
359 pcm_idx = kcontrol->private_value;
360 mutex_lock(&spec->pcm_lock);
361 per_pin = pcm_idx_to_pin(spec, pcm_idx);
363 /* no pin is bound to the pcm */
364 memset(ucontrol->value.bytes.data, 0,
365 ARRAY_SIZE(ucontrol->value.bytes.data));
366 mutex_unlock(&spec->pcm_lock);
369 eld = &per_pin->sink_eld;
371 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
372 eld->eld_size > ELD_MAX_SIZE) {
373 mutex_unlock(&spec->pcm_lock);
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
381 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
383 mutex_unlock(&spec->pcm_lock);
388 static const struct snd_kcontrol_new eld_bytes_ctl = {
389 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
390 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
392 .info = hdmi_eld_ctl_info,
393 .get = hdmi_eld_ctl_get,
396 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
399 struct snd_kcontrol *kctl;
400 struct hdmi_spec *spec = codec->spec;
403 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
406 kctl->private_value = pcm_idx;
407 kctl->id.device = device;
409 /* no pin nid is associated with the kctl now
410 * tbd: associate pin nid to eld ctl later
412 err = snd_hda_ctl_add(codec, 0, kctl);
416 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
421 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
422 int *packet_index, int *byte_index)
426 val = snd_hda_codec_read(codec, pin_nid, 0,
427 AC_VERB_GET_HDMI_DIP_INDEX, 0);
429 *packet_index = val >> 5;
430 *byte_index = val & 0x1f;
434 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
435 int packet_index, int byte_index)
439 val = (packet_index << 5) | (byte_index & 0x1f);
441 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
444 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
450 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
452 struct hdmi_spec *spec = codec->spec;
456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
457 snd_hda_codec_write(codec, pin_nid, 0,
458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
460 if (spec->dyn_pin_out)
461 /* Disable pin out until stream is active */
464 /* Enable pin out: some machines with GM965 gets broken output
465 * when the pin is disabled or changed while using with HDMI
469 snd_hda_codec_write(codec, pin_nid, 0,
470 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
477 #ifdef CONFIG_SND_PROC_FS
478 static void print_eld_info(struct snd_info_entry *entry,
479 struct snd_info_buffer *buffer)
481 struct hdmi_spec_per_pin *per_pin = entry->private_data;
483 mutex_lock(&per_pin->lock);
484 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
485 mutex_unlock(&per_pin->lock);
488 static void write_eld_info(struct snd_info_entry *entry,
489 struct snd_info_buffer *buffer)
491 struct hdmi_spec_per_pin *per_pin = entry->private_data;
493 mutex_lock(&per_pin->lock);
494 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
495 mutex_unlock(&per_pin->lock);
498 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
501 struct hda_codec *codec = per_pin->codec;
502 struct snd_info_entry *entry;
505 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
506 err = snd_card_proc_new(codec->card, name, &entry);
510 snd_info_set_text_ops(entry, per_pin, print_eld_info);
511 entry->c.text.write = write_eld_info;
512 entry->mode |= S_IWUSR;
513 per_pin->proc_entry = entry;
518 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
520 if (!per_pin->codec->bus->shutdown) {
521 snd_info_free_entry(per_pin->proc_entry);
522 per_pin->proc_entry = NULL;
526 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
531 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
537 * Audio InfoFrame routines
541 * Enable Audio InfoFrame Transmission
543 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
546 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
547 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
552 * Disable Audio InfoFrame Transmission
554 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
557 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
558 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
562 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
564 #ifdef CONFIG_SND_DEBUG_VERBOSE
568 size = snd_hdmi_get_eld_size(codec, pin_nid);
569 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
571 for (i = 0; i < 8; i++) {
572 size = snd_hda_codec_read(codec, pin_nid, 0,
573 AC_VERB_GET_HDMI_DIP_SIZE, i);
574 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
579 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
585 for (i = 0; i < 8; i++) {
586 size = snd_hda_codec_read(codec, pin_nid, 0,
587 AC_VERB_GET_HDMI_DIP_SIZE, i);
591 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
592 for (j = 1; j < 1000; j++) {
593 hdmi_write_dip_byte(codec, pin_nid, 0x0);
594 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
596 codec_dbg(codec, "dip index %d: %d != %d\n",
598 if (bi == 0) /* byte index wrapped around */
602 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
608 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
610 u8 *bytes = (u8 *)hdmi_ai;
614 hdmi_ai->checksum = 0;
616 for (i = 0; i < sizeof(*hdmi_ai); i++)
619 hdmi_ai->checksum = -sum;
622 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
628 hdmi_debug_dip_size(codec, pin_nid);
629 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
631 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
632 for (i = 0; i < size; i++)
633 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
636 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
642 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
647 for (i = 0; i < size; i++) {
648 val = snd_hda_codec_read(codec, pin_nid, 0,
649 AC_VERB_GET_HDMI_DIP_DATA, 0);
657 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
659 int ca, int active_channels,
662 union audio_infoframe ai;
664 memset(&ai, 0, sizeof(ai));
665 if (conn_type == 0) { /* HDMI */
666 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
668 hdmi_ai->type = 0x84;
671 hdmi_ai->CC02_CT47 = active_channels - 1;
673 hdmi_checksum_audio_infoframe(hdmi_ai);
674 } else if (conn_type == 1) { /* DisplayPort */
675 struct dp_audio_infoframe *dp_ai = &ai.dp;
679 dp_ai->ver = 0x11 << 2;
680 dp_ai->CC02_CT47 = active_channels - 1;
683 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
689 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
690 * sizeof(*dp_ai) to avoid partial match/update problems when
691 * the user switches between HDMI/DP monitors.
693 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
696 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
698 active_channels, ca);
699 hdmi_stop_infoframe_trans(codec, pin_nid);
700 hdmi_fill_audio_infoframe(codec, pin_nid,
701 ai.bytes, sizeof(ai));
702 hdmi_start_infoframe_trans(codec, pin_nid);
706 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
707 struct hdmi_spec_per_pin *per_pin,
710 struct hdmi_spec *spec = codec->spec;
711 struct hdac_chmap *chmap = &spec->chmap;
712 hda_nid_t pin_nid = per_pin->pin_nid;
713 int channels = per_pin->channels;
715 struct hdmi_eld *eld;
721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
723 snd_hda_codec_write(codec, pin_nid, 0,
724 AC_VERB_SET_AMP_GAIN_MUTE,
727 eld = &per_pin->sink_eld;
729 ca = snd_hdac_channel_allocation(&codec->core,
730 eld->info.spk_alloc, channels,
731 per_pin->chmap_set, non_pcm, per_pin->chmap);
733 active_channels = snd_hdac_get_active_channels(ca);
735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
739 * always configure channel mapping, it may have been changed by the
740 * user in the meantime
742 snd_hdac_setup_channel_mapping(&spec->chmap,
743 pin_nid, non_pcm, ca, channels,
744 per_pin->chmap, per_pin->chmap_set);
746 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
747 eld->info.conn_type);
749 per_pin->non_pcm = non_pcm;
756 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
758 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
761 struct hdmi_spec *spec = codec->spec;
762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
766 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
767 snd_hda_jack_report_sync(codec);
770 static void jack_callback(struct hda_codec *codec,
771 struct hda_jack_callback *jack)
773 /* hda_jack don't support DP MST */
774 check_presence_and_report(codec, jack->nid, 0);
777 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
779 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
780 struct hda_jack_tbl *jack;
781 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
784 * assume DP MST uses dyn_pcm_assign and acomp and
786 * if DP MST supports unsol event, below code need
789 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
792 jack->jack_dirty = 1;
795 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
796 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
797 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
799 /* hda_jack don't support DP MST */
800 check_presence_and_report(codec, jack->nid, 0);
803 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
805 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
806 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
807 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
808 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
826 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
828 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
829 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
831 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
832 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
837 hdmi_intrinsic_event(codec, res);
839 hdmi_non_intrinsic_event(codec, res);
842 static void haswell_verify_D0(struct hda_codec *codec,
843 hda_nid_t cvt_nid, hda_nid_t nid)
847 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
848 * thus pins could only choose converter 0 for use. Make sure the
849 * converters are in correct power state */
850 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
851 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
853 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
854 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
857 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
858 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
859 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
867 /* HBR should be Non-PCM, 8 channels */
868 #define is_hbr_format(format) \
869 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
871 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
874 int pinctl, new_pinctl;
876 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
877 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
878 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
881 return hbr ? -EINVAL : 0;
883 new_pinctl = pinctl & ~AC_PINCTL_EPT;
885 new_pinctl |= AC_PINCTL_EPT_HBR;
887 new_pinctl |= AC_PINCTL_EPT_NATIVE;
890 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
892 pinctl == new_pinctl ? "" : "new-",
895 if (pinctl != new_pinctl)
896 snd_hda_codec_write(codec, pin_nid, 0,
897 AC_VERB_SET_PIN_WIDGET_CONTROL,
905 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
906 hda_nid_t pin_nid, u32 stream_tag, int format)
908 struct hdmi_spec *spec = codec->spec;
912 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
915 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
919 if (is_haswell_plus(codec)) {
922 * on recent platforms IEC Coding Type is required for HBR
923 * support, read current Digital Converter settings and set
924 * ICT bitfield if needed.
926 param = snd_hda_codec_read(codec, cvt_nid, 0,
927 AC_VERB_GET_DIGI_CONVERT_1, 0);
929 param = (param >> 16) & ~(AC_DIG3_ICT);
931 /* on recent platforms ICT mode is required for HBR support */
932 if (is_hbr_format(format))
935 snd_hda_codec_write(codec, cvt_nid, 0,
936 AC_VERB_SET_DIGI_CONVERT_3, param);
939 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
943 /* Try to find an available converter
944 * If pin_idx is less then zero, just try to find an available converter.
945 * Otherwise, try to find an available converter and get the cvt mux index
948 static int hdmi_choose_cvt(struct hda_codec *codec,
949 int pin_idx, int *cvt_id)
951 struct hdmi_spec *spec = codec->spec;
952 struct hdmi_spec_per_pin *per_pin;
953 struct hdmi_spec_per_cvt *per_cvt = NULL;
954 int cvt_idx, mux_idx = 0;
956 /* pin_idx < 0 means no pin will be bound to the converter */
960 per_pin = get_pin(spec, pin_idx);
962 /* Dynamically assign converter to stream */
963 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
964 per_cvt = get_cvt(spec, cvt_idx);
966 /* Must not already be assigned */
967 if (per_cvt->assigned)
971 /* Must be in pin's mux's list of converters */
972 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
973 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
975 /* Not in mux list */
976 if (mux_idx == per_pin->num_mux_nids)
981 /* No free converters */
982 if (cvt_idx == spec->num_cvts)
986 per_pin->mux_idx = mux_idx;
994 /* Assure the pin select the right convetor */
995 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
996 struct hdmi_spec_per_pin *per_pin)
998 hda_nid_t pin_nid = per_pin->pin_nid;
1001 mux_idx = per_pin->mux_idx;
1002 curr = snd_hda_codec_read(codec, pin_nid, 0,
1003 AC_VERB_GET_CONNECT_SEL, 0);
1004 if (curr != mux_idx)
1005 snd_hda_codec_write_cache(codec, pin_nid, 0,
1006 AC_VERB_SET_CONNECT_SEL,
1010 /* get the mux index for the converter of the pins
1011 * converter's mux index is the same for all pins on Intel platform
1013 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1018 for (i = 0; i < spec->num_cvts; i++)
1019 if (spec->cvt_nids[i] == cvt_nid)
1024 /* Intel HDMI workaround to fix audio routing issue:
1025 * For some Intel display codecs, pins share the same connection list.
1026 * So a conveter can be selected by multiple pins and playback on any of these
1027 * pins will generate sound on the external display, because audio flows from
1028 * the same converter to the display pipeline. Also muting one pin may make
1029 * other pins have no sound output.
1030 * So this function assures that an assigned converter for a pin is not selected
1031 * by any other pins.
1033 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1035 int dev_id, int mux_idx)
1037 struct hdmi_spec *spec = codec->spec;
1040 struct hdmi_spec_per_cvt *per_cvt;
1041 struct hdmi_spec_per_pin *per_pin;
1044 /* configure the pins connections */
1045 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1049 per_pin = get_pin(spec, pin_idx);
1051 * pin not connected to monitor
1052 * no need to operate on it
1057 if ((per_pin->pin_nid == pin_nid) &&
1058 (per_pin->dev_id == dev_id))
1062 * if per_pin->dev_id >= dev_num,
1063 * snd_hda_get_dev_select() will fail,
1064 * and the following operation is unpredictable.
1065 * So skip this situation.
1067 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1068 if (per_pin->dev_id >= dev_num)
1071 nid = per_pin->pin_nid;
1074 * Calling this function should not impact
1075 * on the device entry selection
1076 * So let's save the dev id for each pin,
1077 * and restore it when return
1079 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1080 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1081 curr = snd_hda_codec_read(codec, nid, 0,
1082 AC_VERB_GET_CONNECT_SEL, 0);
1083 if (curr != mux_idx) {
1084 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1089 /* choose an unassigned converter. The conveters in the
1090 * connection list are in the same order as in the codec.
1092 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1093 per_cvt = get_cvt(spec, cvt_idx);
1094 if (!per_cvt->assigned) {
1096 "choose cvt %d for pin nid %d\n",
1098 snd_hda_codec_write_cache(codec, nid, 0,
1099 AC_VERB_SET_CONNECT_SEL,
1104 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1108 /* A wrapper of intel_not_share_asigned_cvt() */
1109 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1110 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1113 struct hdmi_spec *spec = codec->spec;
1115 /* On Intel platform, the mapping of converter nid to
1116 * mux index of the pins are always the same.
1117 * The pin nid may be 0, this means all pins will not
1118 * share the converter.
1120 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1122 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1125 /* skeleton caller of pin_cvt_fixup ops */
1126 static void pin_cvt_fixup(struct hda_codec *codec,
1127 struct hdmi_spec_per_pin *per_pin,
1130 struct hdmi_spec *spec = codec->spec;
1132 if (spec->ops.pin_cvt_fixup)
1133 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1136 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1137 * in dyn_pcm_assign mode.
1139 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1140 struct hda_codec *codec,
1141 struct snd_pcm_substream *substream)
1143 struct hdmi_spec *spec = codec->spec;
1144 struct snd_pcm_runtime *runtime = substream->runtime;
1145 int cvt_idx, pcm_idx;
1146 struct hdmi_spec_per_cvt *per_cvt = NULL;
1149 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1153 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1157 per_cvt = get_cvt(spec, cvt_idx);
1158 per_cvt->assigned = 1;
1159 hinfo->nid = per_cvt->cvt_nid;
1161 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1163 set_bit(pcm_idx, &spec->pcm_in_use);
1164 /* todo: setup spdif ctls assign */
1166 /* Initially set the converter's capabilities */
1167 hinfo->channels_min = per_cvt->channels_min;
1168 hinfo->channels_max = per_cvt->channels_max;
1169 hinfo->rates = per_cvt->rates;
1170 hinfo->formats = per_cvt->formats;
1171 hinfo->maxbps = per_cvt->maxbps;
1173 /* Store the updated parameters */
1174 runtime->hw.channels_min = hinfo->channels_min;
1175 runtime->hw.channels_max = hinfo->channels_max;
1176 runtime->hw.formats = hinfo->formats;
1177 runtime->hw.rates = hinfo->rates;
1179 snd_pcm_hw_constraint_step(substream->runtime, 0,
1180 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1187 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1188 struct hda_codec *codec,
1189 struct snd_pcm_substream *substream)
1191 struct hdmi_spec *spec = codec->spec;
1192 struct snd_pcm_runtime *runtime = substream->runtime;
1193 int pin_idx, cvt_idx, pcm_idx;
1194 struct hdmi_spec_per_pin *per_pin;
1195 struct hdmi_eld *eld;
1196 struct hdmi_spec_per_cvt *per_cvt = NULL;
1199 /* Validate hinfo */
1200 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1204 mutex_lock(&spec->pcm_lock);
1205 pin_idx = hinfo_to_pin_index(codec, hinfo);
1206 if (!spec->dyn_pcm_assign) {
1207 if (snd_BUG_ON(pin_idx < 0)) {
1208 mutex_unlock(&spec->pcm_lock);
1212 /* no pin is assigned to the PCM
1213 * PA need pcm open successfully when probe
1216 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1217 mutex_unlock(&spec->pcm_lock);
1222 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1224 mutex_unlock(&spec->pcm_lock);
1228 per_cvt = get_cvt(spec, cvt_idx);
1229 /* Claim converter */
1230 per_cvt->assigned = 1;
1232 set_bit(pcm_idx, &spec->pcm_in_use);
1233 per_pin = get_pin(spec, pin_idx);
1234 per_pin->cvt_nid = per_cvt->cvt_nid;
1235 hinfo->nid = per_cvt->cvt_nid;
1237 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1238 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1239 AC_VERB_SET_CONNECT_SEL,
1242 /* configure unused pins to choose other converters */
1243 pin_cvt_fixup(codec, per_pin, 0);
1245 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1247 /* Initially set the converter's capabilities */
1248 hinfo->channels_min = per_cvt->channels_min;
1249 hinfo->channels_max = per_cvt->channels_max;
1250 hinfo->rates = per_cvt->rates;
1251 hinfo->formats = per_cvt->formats;
1252 hinfo->maxbps = per_cvt->maxbps;
1254 eld = &per_pin->sink_eld;
1255 /* Restrict capabilities by ELD if this isn't disabled */
1256 if (!static_hdmi_pcm && eld->eld_valid) {
1257 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1258 if (hinfo->channels_min > hinfo->channels_max ||
1259 !hinfo->rates || !hinfo->formats) {
1260 per_cvt->assigned = 0;
1262 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1263 mutex_unlock(&spec->pcm_lock);
1268 mutex_unlock(&spec->pcm_lock);
1269 /* Store the updated parameters */
1270 runtime->hw.channels_min = hinfo->channels_min;
1271 runtime->hw.channels_max = hinfo->channels_max;
1272 runtime->hw.formats = hinfo->formats;
1273 runtime->hw.rates = hinfo->rates;
1275 snd_pcm_hw_constraint_step(substream->runtime, 0,
1276 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1281 * HDA/HDMI auto parsing
1283 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1285 struct hdmi_spec *spec = codec->spec;
1286 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1287 hda_nid_t pin_nid = per_pin->pin_nid;
1289 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1291 "HDMI: pin %d wcaps %#x does not support connection list\n",
1292 pin_nid, get_wcaps(codec, pin_nid));
1296 /* all the device entries on the same pin have the same conn list */
1297 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1299 HDA_MAX_CONNECTIONS);
1304 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1305 struct hdmi_spec_per_pin *per_pin)
1309 /* try the prefer PCM */
1310 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1311 return per_pin->pin_nid_idx;
1313 /* have a second try; check the "reserved area" over num_pins */
1314 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1315 if (!test_bit(i, &spec->pcm_bitmap))
1319 /* the last try; check the empty slots in pins */
1320 for (i = 0; i < spec->num_nids; i++) {
1321 if (!test_bit(i, &spec->pcm_bitmap))
1327 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1328 struct hdmi_spec_per_pin *per_pin)
1332 /* pcm already be attached to the pin */
1335 idx = hdmi_find_pcm_slot(spec, per_pin);
1338 per_pin->pcm_idx = idx;
1339 per_pin->pcm = get_hdmi_pcm(spec, idx);
1340 set_bit(idx, &spec->pcm_bitmap);
1343 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1344 struct hdmi_spec_per_pin *per_pin)
1348 /* pcm already be detached from the pin */
1351 idx = per_pin->pcm_idx;
1352 per_pin->pcm_idx = -1;
1353 per_pin->pcm = NULL;
1354 if (idx >= 0 && idx < spec->pcm_used)
1355 clear_bit(idx, &spec->pcm_bitmap);
1358 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1359 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1363 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1364 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1369 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1371 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1372 struct hdmi_spec_per_pin *per_pin)
1374 struct hda_codec *codec = per_pin->codec;
1375 struct hda_pcm *pcm;
1376 struct hda_pcm_stream *hinfo;
1377 struct snd_pcm_substream *substream;
1381 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1382 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1385 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1388 /* hdmi audio only uses playback and one substream */
1389 hinfo = pcm->stream;
1390 substream = pcm->pcm->streams[0].substream;
1392 per_pin->cvt_nid = hinfo->nid;
1394 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1395 if (mux_idx < per_pin->num_mux_nids) {
1396 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1398 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1399 AC_VERB_SET_CONNECT_SEL,
1402 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1404 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1405 if (substream->runtime)
1406 per_pin->channels = substream->runtime->channels;
1407 per_pin->setup = true;
1408 per_pin->mux_idx = mux_idx;
1410 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1413 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1414 struct hdmi_spec_per_pin *per_pin)
1416 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1417 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1419 per_pin->chmap_set = false;
1420 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1422 per_pin->setup = false;
1423 per_pin->channels = 0;
1426 /* update per_pin ELD from the given new ELD;
1427 * setup info frame and notification accordingly
1429 static void update_eld(struct hda_codec *codec,
1430 struct hdmi_spec_per_pin *per_pin,
1431 struct hdmi_eld *eld)
1433 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1434 struct hdmi_spec *spec = codec->spec;
1435 bool old_eld_valid = pin_eld->eld_valid;
1439 /* for monitor disconnection, save pcm_idx firstly */
1440 pcm_idx = per_pin->pcm_idx;
1441 if (spec->dyn_pcm_assign) {
1442 if (eld->eld_valid) {
1443 hdmi_attach_hda_pcm(spec, per_pin);
1444 hdmi_pcm_setup_pin(spec, per_pin);
1446 hdmi_pcm_reset_pin(spec, per_pin);
1447 hdmi_detach_hda_pcm(spec, per_pin);
1450 /* if pcm_idx == -1, it means this is in monitor connection event
1451 * we can get the correct pcm_idx now.
1454 pcm_idx = per_pin->pcm_idx;
1457 snd_hdmi_show_eld(codec, &eld->info);
1459 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1460 if (eld->eld_valid && pin_eld->eld_valid)
1461 if (pin_eld->eld_size != eld->eld_size ||
1462 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1463 eld->eld_size) != 0)
1466 pin_eld->monitor_present = eld->monitor_present;
1467 pin_eld->eld_valid = eld->eld_valid;
1468 pin_eld->eld_size = eld->eld_size;
1470 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1471 pin_eld->info = eld->info;
1474 * Re-setup pin and infoframe. This is needed e.g. when
1475 * - sink is first plugged-in
1476 * - transcoder can change during stream playback on Haswell
1477 * and this can make HW reset converter selection on a pin.
1479 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1480 pin_cvt_fixup(codec, per_pin, 0);
1481 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1484 if (eld_changed && pcm_idx >= 0)
1485 snd_ctl_notify(codec->card,
1486 SNDRV_CTL_EVENT_MASK_VALUE |
1487 SNDRV_CTL_EVENT_MASK_INFO,
1488 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1491 /* update ELD and jack state via HD-audio verbs */
1492 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1495 struct hda_jack_tbl *jack;
1496 struct hda_codec *codec = per_pin->codec;
1497 struct hdmi_spec *spec = codec->spec;
1498 struct hdmi_eld *eld = &spec->temp_eld;
1499 hda_nid_t pin_nid = per_pin->pin_nid;
1501 * Always execute a GetPinSense verb here, even when called from
1502 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1503 * response's PD bit is not the real PD value, but indicates that
1504 * the real PD value changed. An older version of the HD-audio
1505 * specification worked this way. Hence, we just ignore the data in
1506 * the unsolicited response to avoid custom WARs.
1510 bool do_repoll = false;
1512 present = snd_hda_pin_sense(codec, pin_nid);
1514 mutex_lock(&per_pin->lock);
1515 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1516 if (eld->monitor_present)
1517 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1519 eld->eld_valid = false;
1522 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1523 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1525 if (eld->eld_valid) {
1526 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1527 &eld->eld_size) < 0)
1528 eld->eld_valid = false;
1530 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1532 eld->eld_valid = false;
1534 if (!eld->eld_valid && repoll)
1539 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1541 update_eld(codec, per_pin, eld);
1543 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1545 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1547 jack->block_report = !ret;
1549 mutex_unlock(&per_pin->lock);
1553 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1554 struct hdmi_spec_per_pin *per_pin)
1556 struct hdmi_spec *spec = codec->spec;
1557 struct snd_jack *jack = NULL;
1558 struct hda_jack_tbl *jack_tbl;
1560 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1561 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1562 * NULL even after snd_hda_jack_tbl_clear() is called to
1563 * free snd_jack. This may cause access invalid memory
1564 * when calling snd_jack_report
1566 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1567 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1568 else if (!spec->dyn_pcm_assign) {
1570 * jack tbl doesn't support DP MST
1571 * DP MST will use dyn_pcm_assign,
1572 * so DP MST will never come here
1574 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1576 jack = jack_tbl->jack;
1581 /* update ELD and jack state via audio component */
1582 static void sync_eld_via_acomp(struct hda_codec *codec,
1583 struct hdmi_spec_per_pin *per_pin)
1585 struct hdmi_spec *spec = codec->spec;
1586 struct hdmi_eld *eld = &spec->temp_eld;
1587 struct snd_jack *jack = NULL;
1590 mutex_lock(&per_pin->lock);
1591 eld->monitor_present = false;
1592 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1593 per_pin->dev_id, &eld->monitor_present,
1594 eld->eld_buffer, ELD_MAX_SIZE);
1596 size = min(size, ELD_MAX_SIZE);
1597 if (snd_hdmi_parse_eld(codec, &eld->info,
1598 eld->eld_buffer, size) < 0)
1603 eld->eld_valid = true;
1604 eld->eld_size = size;
1606 eld->eld_valid = false;
1610 /* pcm_idx >=0 before update_eld() means it is in monitor
1611 * disconnected event. Jack must be fetched before update_eld()
1613 jack = pin_idx_to_jack(codec, per_pin);
1614 update_eld(codec, per_pin, eld);
1616 jack = pin_idx_to_jack(codec, per_pin);
1619 snd_jack_report(jack,
1620 eld->monitor_present ? SND_JACK_AVOUT : 0);
1622 mutex_unlock(&per_pin->lock);
1625 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1627 struct hda_codec *codec = per_pin->codec;
1628 struct hdmi_spec *spec = codec->spec;
1631 /* no temporary power up/down needed for component notifier */
1632 if (!codec_has_acomp(codec))
1633 snd_hda_power_up_pm(codec);
1635 mutex_lock(&spec->pcm_lock);
1636 if (codec_has_acomp(codec)) {
1637 sync_eld_via_acomp(codec, per_pin);
1638 ret = false; /* don't call snd_hda_jack_report_sync() */
1640 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1642 mutex_unlock(&spec->pcm_lock);
1644 if (!codec_has_acomp(codec))
1645 snd_hda_power_down_pm(codec);
1650 static void hdmi_repoll_eld(struct work_struct *work)
1652 struct hdmi_spec_per_pin *per_pin =
1653 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1655 if (per_pin->repoll_count++ > 6)
1656 per_pin->repoll_count = 0;
1658 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1659 snd_hda_jack_report_sync(per_pin->codec);
1662 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1665 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1667 struct hdmi_spec *spec = codec->spec;
1668 unsigned int caps, config;
1670 struct hdmi_spec_per_pin *per_pin;
1674 caps = snd_hda_query_pin_caps(codec, pin_nid);
1675 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1679 * For DP MST audio, Configuration Default is the same for
1680 * all device entries on the same pin
1682 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1683 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1687 * To simplify the implementation, malloc all
1688 * the virtual pins in the initialization statically
1690 if (is_haswell_plus(codec)) {
1692 * On Intel platforms, device entries number is
1693 * changed dynamically. If there is a DP MST
1694 * hub connected, the device entries number is 3.
1695 * Otherwise, it is 1.
1696 * Here we manually set dev_num to 3, so that
1697 * we can initialize all the device entries when
1698 * bootup statically.
1702 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1703 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1705 * spec->dev_num is the maxinum number of device entries
1706 * among all the pins
1708 spec->dev_num = (spec->dev_num > dev_num) ?
1709 spec->dev_num : dev_num;
1712 * If the platform doesn't support DP MST,
1713 * manually set dev_num to 1. This means
1714 * the pin has only one device entry.
1720 for (i = 0; i < dev_num; i++) {
1721 pin_idx = spec->num_pins;
1722 per_pin = snd_array_new(&spec->pins);
1727 if (spec->dyn_pcm_assign) {
1728 per_pin->pcm = NULL;
1729 per_pin->pcm_idx = -1;
1731 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1732 per_pin->pcm_idx = pin_idx;
1734 per_pin->pin_nid = pin_nid;
1735 per_pin->pin_nid_idx = spec->num_nids;
1736 per_pin->dev_id = i;
1737 per_pin->non_pcm = false;
1738 snd_hda_set_dev_select(codec, pin_nid, i);
1739 if (is_haswell_plus(codec))
1740 intel_haswell_fixup_connect_list(codec, pin_nid);
1741 err = hdmi_read_pin_conn(codec, pin_idx);
1751 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1753 struct hdmi_spec *spec = codec->spec;
1754 struct hdmi_spec_per_cvt *per_cvt;
1758 chans = get_wcaps(codec, cvt_nid);
1759 chans = get_wcaps_channels(chans);
1761 per_cvt = snd_array_new(&spec->cvts);
1765 per_cvt->cvt_nid = cvt_nid;
1766 per_cvt->channels_min = 2;
1768 per_cvt->channels_max = chans;
1769 if (chans > spec->chmap.channels_max)
1770 spec->chmap.channels_max = chans;
1773 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1780 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1781 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1787 static int hdmi_parse_codec(struct hda_codec *codec)
1792 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1793 if (!nid || nodes < 0) {
1794 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1798 for (i = 0; i < nodes; i++, nid++) {
1802 caps = get_wcaps(codec, nid);
1803 type = get_wcaps_type(caps);
1805 if (!(caps & AC_WCAP_DIGITAL))
1809 case AC_WID_AUD_OUT:
1810 hdmi_add_cvt(codec, nid);
1813 hdmi_add_pin(codec, nid);
1823 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1825 struct hda_spdif_out *spdif;
1828 mutex_lock(&codec->spdif_mutex);
1829 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1830 /* Add sanity check to pass klockwork check.
1831 * This should never happen.
1833 if (WARN_ON(spdif == NULL))
1835 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1836 mutex_unlock(&codec->spdif_mutex);
1844 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1845 struct hda_codec *codec,
1846 unsigned int stream_tag,
1847 unsigned int format,
1848 struct snd_pcm_substream *substream)
1850 hda_nid_t cvt_nid = hinfo->nid;
1851 struct hdmi_spec *spec = codec->spec;
1853 struct hdmi_spec_per_pin *per_pin;
1855 struct snd_pcm_runtime *runtime = substream->runtime;
1860 mutex_lock(&spec->pcm_lock);
1861 pin_idx = hinfo_to_pin_index(codec, hinfo);
1862 if (spec->dyn_pcm_assign && pin_idx < 0) {
1863 /* when dyn_pcm_assign and pcm is not bound to a pin
1864 * skip pin setup and return 0 to make audio playback
1867 pin_cvt_fixup(codec, NULL, cvt_nid);
1868 snd_hda_codec_setup_stream(codec, cvt_nid,
1869 stream_tag, 0, format);
1870 mutex_unlock(&spec->pcm_lock);
1874 if (snd_BUG_ON(pin_idx < 0)) {
1875 mutex_unlock(&spec->pcm_lock);
1878 per_pin = get_pin(spec, pin_idx);
1879 pin_nid = per_pin->pin_nid;
1881 /* Verify pin:cvt selections to avoid silent audio after S3.
1882 * After S3, the audio driver restores pin:cvt selections
1883 * but this can happen before gfx is ready and such selection
1884 * is overlooked by HW. Thus multiple pins can share a same
1885 * default convertor and mute control will affect each other,
1886 * which can cause a resumed audio playback become silent
1889 pin_cvt_fixup(codec, per_pin, 0);
1891 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1892 /* Todo: add DP1.2 MST audio support later */
1893 if (codec_has_acomp(codec))
1894 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1897 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1898 mutex_lock(&per_pin->lock);
1899 per_pin->channels = substream->runtime->channels;
1900 per_pin->setup = true;
1902 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1903 mutex_unlock(&per_pin->lock);
1904 if (spec->dyn_pin_out) {
1905 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1906 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1907 snd_hda_codec_write(codec, pin_nid, 0,
1908 AC_VERB_SET_PIN_WIDGET_CONTROL,
1912 /* snd_hda_set_dev_select() has been called before */
1913 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1914 stream_tag, format);
1915 mutex_unlock(&spec->pcm_lock);
1919 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1920 struct hda_codec *codec,
1921 struct snd_pcm_substream *substream)
1923 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1927 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1928 struct hda_codec *codec,
1929 struct snd_pcm_substream *substream)
1931 struct hdmi_spec *spec = codec->spec;
1932 int cvt_idx, pin_idx, pcm_idx;
1933 struct hdmi_spec_per_cvt *per_cvt;
1934 struct hdmi_spec_per_pin *per_pin;
1938 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1939 if (snd_BUG_ON(pcm_idx < 0))
1941 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1942 if (snd_BUG_ON(cvt_idx < 0))
1944 per_cvt = get_cvt(spec, cvt_idx);
1946 snd_BUG_ON(!per_cvt->assigned);
1947 per_cvt->assigned = 0;
1950 mutex_lock(&spec->pcm_lock);
1951 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1952 clear_bit(pcm_idx, &spec->pcm_in_use);
1953 pin_idx = hinfo_to_pin_index(codec, hinfo);
1954 if (spec->dyn_pcm_assign && pin_idx < 0) {
1955 mutex_unlock(&spec->pcm_lock);
1959 if (snd_BUG_ON(pin_idx < 0)) {
1960 mutex_unlock(&spec->pcm_lock);
1963 per_pin = get_pin(spec, pin_idx);
1965 if (spec->dyn_pin_out) {
1966 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1967 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1968 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1969 AC_VERB_SET_PIN_WIDGET_CONTROL,
1973 mutex_lock(&per_pin->lock);
1974 per_pin->chmap_set = false;
1975 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1977 per_pin->setup = false;
1978 per_pin->channels = 0;
1979 mutex_unlock(&per_pin->lock);
1980 mutex_unlock(&spec->pcm_lock);
1986 static const struct hda_pcm_ops generic_ops = {
1987 .open = hdmi_pcm_open,
1988 .close = hdmi_pcm_close,
1989 .prepare = generic_hdmi_playback_pcm_prepare,
1990 .cleanup = generic_hdmi_playback_pcm_cleanup,
1993 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1995 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1996 struct hdmi_spec *spec = codec->spec;
1997 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2002 return per_pin->sink_eld.info.spk_alloc;
2005 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2006 unsigned char *chmap)
2008 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2009 struct hdmi_spec *spec = codec->spec;
2010 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2012 /* chmap is already set to 0 in caller */
2016 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2019 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2020 unsigned char *chmap, int prepared)
2022 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2023 struct hdmi_spec *spec = codec->spec;
2024 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028 mutex_lock(&per_pin->lock);
2029 per_pin->chmap_set = true;
2030 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2032 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2033 mutex_unlock(&per_pin->lock);
2036 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2038 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 struct hdmi_spec *spec = codec->spec;
2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2042 return per_pin ? true:false;
2045 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2047 struct hdmi_spec *spec = codec->spec;
2051 * for non-mst mode, pcm number is the same as before
2052 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2053 * dev_num is the device entry number in a pin
2056 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2057 struct hda_pcm *info;
2058 struct hda_pcm_stream *pstr;
2060 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2064 spec->pcm_rec[idx].pcm = info;
2066 info->pcm_type = HDA_PCM_TYPE_HDMI;
2067 info->own_chmap = true;
2069 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2070 pstr->substreams = 1;
2071 pstr->ops = generic_ops;
2072 /* pcm number is less than 16 */
2073 if (spec->pcm_used >= 16)
2075 /* other pstr fields are set in open */
2081 static void free_hdmi_jack_priv(struct snd_jack *jack)
2083 struct hdmi_pcm *pcm = jack->private_data;
2088 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2089 struct hdmi_spec *spec,
2093 struct snd_jack *jack;
2096 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2101 spec->pcm_rec[pcm_idx].jack = jack;
2102 jack->private_data = &spec->pcm_rec[pcm_idx];
2103 jack->private_free = free_hdmi_jack_priv;
2107 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2109 char hdmi_str[32] = "HDMI/DP";
2110 struct hdmi_spec *spec = codec->spec;
2111 struct hdmi_spec_per_pin *per_pin;
2112 struct hda_jack_tbl *jack;
2113 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2118 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2120 if (spec->dyn_pcm_assign)
2121 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2123 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2124 /* if !dyn_pcm_assign, it must be non-MST mode.
2125 * This means pcms and pins are statically mapped.
2126 * And pcm_idx is pin_idx.
2128 per_pin = get_pin(spec, pcm_idx);
2129 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2131 strncat(hdmi_str, " Phantom",
2132 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2133 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2137 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2140 /* assign jack->jack to pcm_rec[].jack to
2141 * align with dyn_pcm_assign mode
2143 spec->pcm_rec[pcm_idx].jack = jack->jack;
2147 static int generic_hdmi_build_controls(struct hda_codec *codec)
2149 struct hdmi_spec *spec = codec->spec;
2151 int pin_idx, pcm_idx;
2154 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2155 err = generic_hdmi_build_jack(codec, pcm_idx);
2159 /* create the spdif for each pcm
2160 * pin will be bound when monitor is connected
2162 if (spec->dyn_pcm_assign)
2163 err = snd_hda_create_dig_out_ctls(codec,
2164 0, spec->cvt_nids[0],
2167 struct hdmi_spec_per_pin *per_pin =
2168 get_pin(spec, pcm_idx);
2169 err = snd_hda_create_dig_out_ctls(codec,
2171 per_pin->mux_nids[0],
2176 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2178 dev = get_pcm_rec(spec, pcm_idx)->device;
2179 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2180 /* add control for ELD Bytes */
2181 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2187 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2188 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2190 hdmi_present_sense(per_pin, 0);
2193 /* add channel maps */
2194 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2195 struct hda_pcm *pcm;
2197 pcm = get_pcm_rec(spec, pcm_idx);
2198 if (!pcm || !pcm->pcm)
2200 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2208 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2210 struct hdmi_spec *spec = codec->spec;
2213 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2214 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2216 per_pin->codec = codec;
2217 mutex_init(&per_pin->lock);
2218 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2219 eld_proc_new(per_pin, pin_idx);
2224 static int generic_hdmi_init(struct hda_codec *codec)
2226 struct hdmi_spec *spec = codec->spec;
2229 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2230 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2231 hda_nid_t pin_nid = per_pin->pin_nid;
2232 int dev_id = per_pin->dev_id;
2234 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2235 hdmi_init_pin(codec, pin_nid);
2236 if (!codec_has_acomp(codec))
2237 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2238 codec->jackpoll_interval > 0 ?
2239 jack_callback : NULL);
2244 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2246 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2247 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2250 static void hdmi_array_free(struct hdmi_spec *spec)
2252 snd_array_free(&spec->pins);
2253 snd_array_free(&spec->cvts);
2256 static void generic_spec_free(struct hda_codec *codec)
2258 struct hdmi_spec *spec = codec->spec;
2261 hdmi_array_free(spec);
2265 codec->dp_mst = false;
2268 static void generic_hdmi_free(struct hda_codec *codec)
2270 struct hdmi_spec *spec = codec->spec;
2271 int pin_idx, pcm_idx;
2273 if (codec_has_acomp(codec))
2274 snd_hdac_i915_register_notifier(NULL);
2276 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2277 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2278 cancel_delayed_work_sync(&per_pin->work);
2279 eld_proc_free(per_pin);
2282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2283 if (spec->pcm_rec[pcm_idx].jack == NULL)
2285 if (spec->dyn_pcm_assign)
2286 snd_device_free(codec->card,
2287 spec->pcm_rec[pcm_idx].jack);
2289 spec->pcm_rec[pcm_idx].jack = NULL;
2292 generic_spec_free(codec);
2296 static int generic_hdmi_resume(struct hda_codec *codec)
2298 struct hdmi_spec *spec = codec->spec;
2301 codec->patch_ops.init(codec);
2302 regcache_sync(codec->core.regmap);
2304 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2305 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2306 hdmi_present_sense(per_pin, 1);
2312 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2313 .init = generic_hdmi_init,
2314 .free = generic_hdmi_free,
2315 .build_pcms = generic_hdmi_build_pcms,
2316 .build_controls = generic_hdmi_build_controls,
2317 .unsol_event = hdmi_unsol_event,
2319 .resume = generic_hdmi_resume,
2323 static const struct hdmi_ops generic_standard_hdmi_ops = {
2324 .pin_get_eld = snd_hdmi_get_eld,
2325 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2326 .pin_hbr_setup = hdmi_pin_hbr_setup,
2327 .setup_stream = hdmi_setup_stream,
2330 /* allocate codec->spec and assign/initialize generic parser ops */
2331 static int alloc_generic_hdmi(struct hda_codec *codec)
2333 struct hdmi_spec *spec;
2335 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2339 spec->ops = generic_standard_hdmi_ops;
2340 spec->dev_num = 1; /* initialize to 1 */
2341 mutex_init(&spec->pcm_lock);
2342 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2344 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2345 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2346 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2347 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2350 hdmi_array_init(spec, 4);
2352 codec->patch_ops = generic_hdmi_patch_ops;
2357 /* generic HDMI parser */
2358 static int patch_generic_hdmi(struct hda_codec *codec)
2362 err = alloc_generic_hdmi(codec);
2366 err = hdmi_parse_codec(codec);
2368 generic_spec_free(codec);
2372 generic_hdmi_init_per_pins(codec);
2377 * Intel codec parsers and helpers
2380 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2383 struct hdmi_spec *spec = codec->spec;
2387 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2388 if (nconns == spec->num_cvts &&
2389 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2392 /* override pins connection list */
2393 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2394 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2397 #define INTEL_VENDOR_NID 0x08
2398 #define INTEL_GLK_VENDOR_NID 0x0B
2399 #define INTEL_GET_VENDOR_VERB 0xf81
2400 #define INTEL_SET_VENDOR_VERB 0x781
2401 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2402 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2404 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2407 unsigned int vendor_param;
2408 struct hdmi_spec *spec = codec->spec;
2410 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2411 INTEL_GET_VENDOR_VERB, 0);
2412 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2415 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2416 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2417 INTEL_SET_VENDOR_VERB, vendor_param);
2418 if (vendor_param == -1)
2422 snd_hda_codec_update_widgets(codec);
2425 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2427 unsigned int vendor_param;
2428 struct hdmi_spec *spec = codec->spec;
2430 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2431 INTEL_GET_VENDOR_VERB, 0);
2432 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2435 /* enable DP1.2 mode */
2436 vendor_param |= INTEL_EN_DP12;
2437 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2438 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2439 INTEL_SET_VENDOR_VERB, vendor_param);
2442 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2443 * Otherwise you may get severe h/w communication errors.
2445 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2446 unsigned int power_state)
2448 if (power_state == AC_PWRST_D0) {
2449 intel_haswell_enable_all_pins(codec, false);
2450 intel_haswell_fixup_enable_dp12(codec);
2453 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2454 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2457 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2459 struct hda_codec *codec = audio_ptr;
2463 /* we assume only from port-B to port-D */
2464 if (port < 1 || port > 3)
2467 switch (codec->core.vendor_id) {
2468 case 0x80860054: /* ILK */
2469 case 0x80862804: /* ILK */
2470 case 0x80862882: /* VLV */
2471 pin_nid = port + 0x03;
2474 pin_nid = port + 0x04;
2478 /* skip notification during system suspend (but not in runtime PM);
2479 * the state will be updated at resume
2481 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2483 /* ditto during suspend/resume process itself */
2484 if (atomic_read(&(codec)->core.in_pm))
2487 snd_hdac_i915_set_bclk(&codec->bus->core);
2488 check_presence_and_report(codec, pin_nid, dev_id);
2491 /* register i915 component pin_eld_notify callback */
2492 static void register_i915_notifier(struct hda_codec *codec)
2494 struct hdmi_spec *spec = codec->spec;
2496 spec->use_acomp_notifier = true;
2497 spec->i915_audio_ops.audio_ptr = codec;
2498 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2499 * will call pin_eld_notify with using audio_ptr pointer
2500 * We need make sure audio_ptr is really setup
2503 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2504 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2507 /* setup_stream ops override for HSW+ */
2508 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2509 hda_nid_t pin_nid, u32 stream_tag, int format)
2511 haswell_verify_D0(codec, cvt_nid, pin_nid);
2512 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2515 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2516 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2517 struct hdmi_spec_per_pin *per_pin,
2521 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2523 intel_verify_pin_cvt_connect(codec, per_pin);
2524 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2525 per_pin->dev_id, per_pin->mux_idx);
2527 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2531 /* precondition and allocation for Intel codecs */
2532 static int alloc_intel_hdmi(struct hda_codec *codec)
2534 /* requires i915 binding */
2535 if (!codec->bus->core.audio_component) {
2536 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2540 return alloc_generic_hdmi(codec);
2543 /* parse and post-process for Intel codecs */
2544 static int parse_intel_hdmi(struct hda_codec *codec)
2548 err = hdmi_parse_codec(codec);
2550 generic_spec_free(codec);
2554 generic_hdmi_init_per_pins(codec);
2555 register_i915_notifier(codec);
2559 /* Intel Haswell and onwards; audio component with eld notifier */
2560 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2562 struct hdmi_spec *spec;
2565 err = alloc_intel_hdmi(codec);
2569 codec->dp_mst = true;
2570 spec->dyn_pcm_assign = true;
2571 spec->vendor_nid = vendor_nid;
2573 intel_haswell_enable_all_pins(codec, true);
2574 intel_haswell_fixup_enable_dp12(codec);
2576 /* For Haswell/Broadwell, the controller is also in the power well and
2577 * can cover the codec power request, and so need not set this flag.
2579 if (!is_haswell(codec) && !is_broadwell(codec))
2580 codec->core.link_power_control = 1;
2582 codec->patch_ops.set_power_state = haswell_set_power_state;
2583 codec->depop_delay = 0;
2584 codec->auto_runtime_pm = 1;
2586 spec->ops.setup_stream = i915_hsw_setup_stream;
2587 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2589 return parse_intel_hdmi(codec);
2592 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2594 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2597 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2599 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2602 /* Intel Baytrail and Braswell; with eld notifier */
2603 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2605 struct hdmi_spec *spec;
2608 err = alloc_intel_hdmi(codec);
2613 /* For Valleyview/Cherryview, only the display codec is in the display
2614 * power well and can use link_power ops to request/release the power.
2616 codec->core.link_power_control = 1;
2618 codec->depop_delay = 0;
2619 codec->auto_runtime_pm = 1;
2621 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2623 return parse_intel_hdmi(codec);
2626 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2627 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2631 err = alloc_intel_hdmi(codec);
2634 return parse_intel_hdmi(codec);
2638 * Shared non-generic implementations
2641 static int simple_playback_build_pcms(struct hda_codec *codec)
2643 struct hdmi_spec *spec = codec->spec;
2644 struct hda_pcm *info;
2646 struct hda_pcm_stream *pstr;
2647 struct hdmi_spec_per_cvt *per_cvt;
2649 per_cvt = get_cvt(spec, 0);
2650 chans = get_wcaps(codec, per_cvt->cvt_nid);
2651 chans = get_wcaps_channels(chans);
2653 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2656 spec->pcm_rec[0].pcm = info;
2657 info->pcm_type = HDA_PCM_TYPE_HDMI;
2658 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2659 *pstr = spec->pcm_playback;
2660 pstr->nid = per_cvt->cvt_nid;
2661 if (pstr->channels_max <= 2 && chans && chans <= 16)
2662 pstr->channels_max = chans;
2667 /* unsolicited event for jack sensing */
2668 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2671 snd_hda_jack_set_dirty_all(codec);
2672 snd_hda_jack_report_sync(codec);
2675 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2676 * as long as spec->pins[] is set correctly
2678 #define simple_hdmi_build_jack generic_hdmi_build_jack
2680 static int simple_playback_build_controls(struct hda_codec *codec)
2682 struct hdmi_spec *spec = codec->spec;
2683 struct hdmi_spec_per_cvt *per_cvt;
2686 per_cvt = get_cvt(spec, 0);
2687 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2692 return simple_hdmi_build_jack(codec, 0);
2695 static int simple_playback_init(struct hda_codec *codec)
2697 struct hdmi_spec *spec = codec->spec;
2698 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2699 hda_nid_t pin = per_pin->pin_nid;
2701 snd_hda_codec_write(codec, pin, 0,
2702 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2703 /* some codecs require to unmute the pin */
2704 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2705 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2707 snd_hda_jack_detect_enable(codec, pin);
2711 static void simple_playback_free(struct hda_codec *codec)
2713 struct hdmi_spec *spec = codec->spec;
2715 hdmi_array_free(spec);
2720 * Nvidia specific implementations
2723 #define Nv_VERB_SET_Channel_Allocation 0xF79
2724 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2725 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2726 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2728 #define nvhdmi_master_con_nid_7x 0x04
2729 #define nvhdmi_master_pin_nid_7x 0x05
2731 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2732 /*front, rear, clfe, rear_surr */
2736 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2737 /* set audio protect on */
2738 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2739 /* enable digital output on pin widget */
2740 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2744 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2745 /* set audio protect on */
2746 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2747 /* enable digital output on pin widget */
2748 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2749 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2750 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2751 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2752 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2756 #ifdef LIMITED_RATE_FMT_SUPPORT
2757 /* support only the safe format and rate */
2758 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2759 #define SUPPORTED_MAXBPS 16
2760 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2762 /* support all rates and formats */
2763 #define SUPPORTED_RATES \
2764 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2765 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2766 SNDRV_PCM_RATE_192000)
2767 #define SUPPORTED_MAXBPS 24
2768 #define SUPPORTED_FORMATS \
2769 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2772 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2774 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2778 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2780 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2784 static const unsigned int channels_2_6_8[] = {
2788 static const unsigned int channels_2_8[] = {
2792 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2793 .count = ARRAY_SIZE(channels_2_6_8),
2794 .list = channels_2_6_8,
2798 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2799 .count = ARRAY_SIZE(channels_2_8),
2800 .list = channels_2_8,
2804 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2805 struct hda_codec *codec,
2806 struct snd_pcm_substream *substream)
2808 struct hdmi_spec *spec = codec->spec;
2809 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2811 switch (codec->preset->vendor_id) {
2816 hw_constraints_channels = &hw_constraints_2_8_channels;
2819 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2825 if (hw_constraints_channels != NULL) {
2826 snd_pcm_hw_constraint_list(substream->runtime, 0,
2827 SNDRV_PCM_HW_PARAM_CHANNELS,
2828 hw_constraints_channels);
2830 snd_pcm_hw_constraint_step(substream->runtime, 0,
2831 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2834 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2837 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2838 struct hda_codec *codec,
2839 struct snd_pcm_substream *substream)
2841 struct hdmi_spec *spec = codec->spec;
2842 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2845 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2846 struct hda_codec *codec,
2847 unsigned int stream_tag,
2848 unsigned int format,
2849 struct snd_pcm_substream *substream)
2851 struct hdmi_spec *spec = codec->spec;
2852 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2853 stream_tag, format, substream);
2856 static const struct hda_pcm_stream simple_pcm_playback = {
2861 .open = simple_playback_pcm_open,
2862 .close = simple_playback_pcm_close,
2863 .prepare = simple_playback_pcm_prepare
2867 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2868 .build_controls = simple_playback_build_controls,
2869 .build_pcms = simple_playback_build_pcms,
2870 .init = simple_playback_init,
2871 .free = simple_playback_free,
2872 .unsol_event = simple_hdmi_unsol_event,
2875 static int patch_simple_hdmi(struct hda_codec *codec,
2876 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2878 struct hdmi_spec *spec;
2879 struct hdmi_spec_per_cvt *per_cvt;
2880 struct hdmi_spec_per_pin *per_pin;
2882 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2887 hdmi_array_init(spec, 1);
2889 spec->multiout.num_dacs = 0; /* no analog */
2890 spec->multiout.max_channels = 2;
2891 spec->multiout.dig_out_nid = cvt_nid;
2894 per_pin = snd_array_new(&spec->pins);
2895 per_cvt = snd_array_new(&spec->cvts);
2896 if (!per_pin || !per_cvt) {
2897 simple_playback_free(codec);
2900 per_cvt->cvt_nid = cvt_nid;
2901 per_pin->pin_nid = pin_nid;
2902 spec->pcm_playback = simple_pcm_playback;
2904 codec->patch_ops = simple_hdmi_patch_ops;
2909 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2912 unsigned int chanmask;
2913 int chan = channels ? (channels - 1) : 1;
2932 /* Set the audio infoframe channel allocation and checksum fields. The
2933 * channel count is computed implicitly by the hardware. */
2934 snd_hda_codec_write(codec, 0x1, 0,
2935 Nv_VERB_SET_Channel_Allocation, chanmask);
2937 snd_hda_codec_write(codec, 0x1, 0,
2938 Nv_VERB_SET_Info_Frame_Checksum,
2939 (0x71 - chan - chanmask));
2942 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2943 struct hda_codec *codec,
2944 struct snd_pcm_substream *substream)
2946 struct hdmi_spec *spec = codec->spec;
2949 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2950 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2951 for (i = 0; i < 4; i++) {
2952 /* set the stream id */
2953 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2954 AC_VERB_SET_CHANNEL_STREAMID, 0);
2955 /* set the stream format */
2956 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2957 AC_VERB_SET_STREAM_FORMAT, 0);
2960 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2961 * streams are disabled. */
2962 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2964 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2967 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2968 struct hda_codec *codec,
2969 unsigned int stream_tag,
2970 unsigned int format,
2971 struct snd_pcm_substream *substream)
2974 unsigned int dataDCC2, channel_id;
2976 struct hdmi_spec *spec = codec->spec;
2977 struct hda_spdif_out *spdif;
2978 struct hdmi_spec_per_cvt *per_cvt;
2980 mutex_lock(&codec->spdif_mutex);
2981 per_cvt = get_cvt(spec, 0);
2982 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2984 chs = substream->runtime->channels;
2988 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2989 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2990 snd_hda_codec_write(codec,
2991 nvhdmi_master_con_nid_7x,
2993 AC_VERB_SET_DIGI_CONVERT_1,
2994 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2996 /* set the stream id */
2997 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2998 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3000 /* set the stream format */
3001 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3002 AC_VERB_SET_STREAM_FORMAT, format);
3004 /* turn on again (if needed) */
3005 /* enable and set the channel status audio/data flag */
3006 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3007 snd_hda_codec_write(codec,
3008 nvhdmi_master_con_nid_7x,
3010 AC_VERB_SET_DIGI_CONVERT_1,
3011 spdif->ctls & 0xff);
3012 snd_hda_codec_write(codec,
3013 nvhdmi_master_con_nid_7x,
3015 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3018 for (i = 0; i < 4; i++) {
3024 /* turn off SPDIF once;
3025 *otherwise the IEC958 bits won't be updated
3027 if (codec->spdif_status_reset &&
3028 (spdif->ctls & AC_DIG1_ENABLE))
3029 snd_hda_codec_write(codec,
3030 nvhdmi_con_nids_7x[i],
3032 AC_VERB_SET_DIGI_CONVERT_1,
3033 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3034 /* set the stream id */
3035 snd_hda_codec_write(codec,
3036 nvhdmi_con_nids_7x[i],
3038 AC_VERB_SET_CHANNEL_STREAMID,
3039 (stream_tag << 4) | channel_id);
3040 /* set the stream format */
3041 snd_hda_codec_write(codec,
3042 nvhdmi_con_nids_7x[i],
3044 AC_VERB_SET_STREAM_FORMAT,
3046 /* turn on again (if needed) */
3047 /* enable and set the channel status audio/data flag */
3048 if (codec->spdif_status_reset &&
3049 (spdif->ctls & AC_DIG1_ENABLE)) {
3050 snd_hda_codec_write(codec,
3051 nvhdmi_con_nids_7x[i],
3053 AC_VERB_SET_DIGI_CONVERT_1,
3054 spdif->ctls & 0xff);
3055 snd_hda_codec_write(codec,
3056 nvhdmi_con_nids_7x[i],
3058 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3062 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3064 mutex_unlock(&codec->spdif_mutex);
3068 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3072 .nid = nvhdmi_master_con_nid_7x,
3073 .rates = SUPPORTED_RATES,
3074 .maxbps = SUPPORTED_MAXBPS,
3075 .formats = SUPPORTED_FORMATS,
3077 .open = simple_playback_pcm_open,
3078 .close = nvhdmi_8ch_7x_pcm_close,
3079 .prepare = nvhdmi_8ch_7x_pcm_prepare
3083 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3085 struct hdmi_spec *spec;
3086 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3087 nvhdmi_master_pin_nid_7x);
3091 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3092 /* override the PCM rates, etc, as the codec doesn't give full list */
3094 spec->pcm_playback.rates = SUPPORTED_RATES;
3095 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3096 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3100 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3102 struct hdmi_spec *spec = codec->spec;
3103 int err = simple_playback_build_pcms(codec);
3105 struct hda_pcm *info = get_pcm_rec(spec, 0);
3106 info->own_chmap = true;
3111 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3113 struct hdmi_spec *spec = codec->spec;
3114 struct hda_pcm *info;
3115 struct snd_pcm_chmap *chmap;
3118 err = simple_playback_build_controls(codec);
3122 /* add channel maps */
3123 info = get_pcm_rec(spec, 0);
3124 err = snd_pcm_add_chmap_ctls(info->pcm,
3125 SNDRV_PCM_STREAM_PLAYBACK,
3126 snd_pcm_alt_chmaps, 8, 0, &chmap);
3129 switch (codec->preset->vendor_id) {
3134 chmap->channel_mask = (1U << 2) | (1U << 8);
3137 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3142 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3144 struct hdmi_spec *spec;
3145 int err = patch_nvhdmi_2ch(codec);
3149 spec->multiout.max_channels = 8;
3150 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3151 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3152 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3153 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3155 /* Initialize the audio infoframe channel mask and checksum to something
3157 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3163 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3167 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3168 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3170 if (cap->ca_index == 0x00 && channels == 2)
3171 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3173 /* If the speaker allocation matches the channel count, it is OK. */
3174 if (cap->channels != channels)
3177 /* all channels are remappable freely */
3178 return SNDRV_CTL_TLVT_CHMAP_VAR;
3181 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3182 int ca, int chs, unsigned char *map)
3184 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3190 static int patch_nvhdmi(struct hda_codec *codec)
3192 struct hdmi_spec *spec;
3195 err = patch_generic_hdmi(codec);
3200 spec->dyn_pin_out = true;
3202 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3203 nvhdmi_chmap_cea_alloc_validate_get_type;
3204 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3210 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3211 * accessed using vendor-defined verbs. These registers can be used for
3212 * interoperability between the HDA and HDMI drivers.
3215 /* Audio Function Group node */
3216 #define NVIDIA_AFG_NID 0x01
3219 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3220 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3221 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3222 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3223 * additional bit (at position 30) to signal the validity of the format.
3225 * | 31 | 30 | 29 16 | 15 0 |
3226 * +---------+-------+--------+--------+
3227 * | TRIGGER | VALID | UNUSED | FORMAT |
3228 * +-----------------------------------|
3230 * Note that for the trigger bit to take effect it needs to change value
3231 * (i.e. it needs to be toggled).
3233 #define NVIDIA_GET_SCRATCH0 0xfa6
3234 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3235 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3236 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3237 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3238 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3239 #define NVIDIA_SCRATCH_VALID (1 << 6)
3241 #define NVIDIA_GET_SCRATCH1 0xfab
3242 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3243 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3244 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3245 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3248 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3249 * the format is invalidated so that the HDMI codec can be disabled.
3251 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3255 /* bits [31:30] contain the trigger and valid bits */
3256 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3257 NVIDIA_GET_SCRATCH0, 0);
3258 value = (value >> 24) & 0xff;
3260 /* bits [15:0] are used to store the HDA format */
3261 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3262 NVIDIA_SET_SCRATCH0_BYTE0,
3263 (format >> 0) & 0xff);
3264 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3265 NVIDIA_SET_SCRATCH0_BYTE1,
3266 (format >> 8) & 0xff);
3268 /* bits [16:24] are unused */
3269 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3270 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3273 * Bit 30 signals that the data is valid and hence that HDMI audio can
3277 value &= ~NVIDIA_SCRATCH_VALID;
3279 value |= NVIDIA_SCRATCH_VALID;
3282 * Whenever the trigger bit is toggled, an interrupt is raised in the
3283 * HDMI codec. The HDMI driver will use that as trigger to update its
3286 value ^= NVIDIA_SCRATCH_TRIGGER;
3288 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3289 NVIDIA_SET_SCRATCH0_BYTE3, value);
3292 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3293 struct hda_codec *codec,
3294 unsigned int stream_tag,
3295 unsigned int format,
3296 struct snd_pcm_substream *substream)
3300 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3305 /* notify the HDMI codec of the format change */
3306 tegra_hdmi_set_format(codec, format);
3311 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3312 struct hda_codec *codec,
3313 struct snd_pcm_substream *substream)
3315 /* invalidate the format in the HDMI codec */
3316 tegra_hdmi_set_format(codec, 0);
3318 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3321 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3323 struct hdmi_spec *spec = codec->spec;
3326 for (i = 0; i < spec->num_pins; i++) {
3327 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3329 if (pcm->pcm_type == type)
3336 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3338 struct hda_pcm_stream *stream;
3339 struct hda_pcm *pcm;
3342 err = generic_hdmi_build_pcms(codec);
3346 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3351 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3352 * codec about format changes.
3354 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3355 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3356 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3361 static int patch_tegra_hdmi(struct hda_codec *codec)
3365 err = patch_generic_hdmi(codec);
3369 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3375 * ATI/AMD-specific implementations
3378 #define is_amdhdmi_rev3_or_later(codec) \
3379 ((codec)->core.vendor_id == 0x1002aa01 && \
3380 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3381 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3383 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3384 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3385 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3386 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3387 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3388 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3389 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3390 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3391 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3392 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3393 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3394 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3395 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3396 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3397 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3398 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3399 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3400 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3401 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3402 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3403 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3404 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3405 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3406 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3407 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3409 /* AMD specific HDA cvt verbs */
3410 #define ATI_VERB_SET_RAMP_RATE 0x770
3411 #define ATI_VERB_GET_RAMP_RATE 0xf70
3413 #define ATI_OUT_ENABLE 0x1
3415 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3416 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3418 #define ATI_HBR_CAPABLE 0x01
3419 #define ATI_HBR_ENABLE 0x10
3421 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3422 unsigned char *buf, int *eld_size)
3424 /* call hda_eld.c ATI/AMD-specific function */
3425 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3426 is_amdhdmi_rev3_or_later(codec));
3429 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3430 int active_channels, int conn_type)
3432 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3435 static int atihdmi_paired_swap_fc_lfe(int pos)
3438 * ATI/AMD have automatic FC/LFE swap built-in
3439 * when in pairwise mapping mode.
3443 /* see channel_allocations[].speakers[] */
3452 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3453 int ca, int chs, unsigned char *map)
3455 struct hdac_cea_channel_speaker_allocation *cap;
3458 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3460 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3461 for (i = 0; i < chs; ++i) {
3462 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3464 bool companion_ok = false;
3469 for (j = 0 + i % 2; j < 8; j += 2) {
3470 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3471 if (cap->speakers[chan_idx] == mask) {
3472 /* channel is in a supported position */
3475 if (i % 2 == 0 && i + 1 < chs) {
3476 /* even channel, check the odd companion */
3477 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3478 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3479 int comp_mask_act = cap->speakers[comp_chan_idx];
3481 if (comp_mask_req == comp_mask_act)
3482 companion_ok = true;
3494 i++; /* companion channel already checked */
3500 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3501 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3503 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3505 int ati_channel_setup = 0;
3510 if (!has_amd_full_remap_support(codec)) {
3511 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3513 /* In case this is an odd slot but without stream channel, do not
3514 * disable the slot since the corresponding even slot could have a
3515 * channel. In case neither have a channel, the slot pair will be
3516 * disabled when this function is called for the even slot. */
3517 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3520 hdmi_slot -= hdmi_slot % 2;
3522 if (stream_channel != 0xf)
3523 stream_channel -= stream_channel % 2;
3526 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3528 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3530 if (stream_channel != 0xf)
3531 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3533 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3536 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3537 hda_nid_t pin_nid, int asp_slot)
3539 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3540 bool was_odd = false;
3541 int ati_asp_slot = asp_slot;
3543 int ati_channel_setup;
3548 if (!has_amd_full_remap_support(codec)) {
3549 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3550 if (ati_asp_slot % 2 != 0) {
3556 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3558 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3560 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3563 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3566 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3567 struct hdac_chmap *chmap,
3568 struct hdac_cea_channel_speaker_allocation *cap,
3574 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3575 * we need to take that into account (a single channel may take 2
3576 * channel slots if we need to carry a silent channel next to it).
3577 * On Rev3+ AMD codecs this function is not used.
3581 /* We only produce even-numbered channel count TLVs */
3582 if ((channels % 2) != 0)
3585 for (c = 0; c < 7; c += 2) {
3586 if (cap->speakers[c] || cap->speakers[c+1])
3590 if (chanpairs * 2 != channels)
3593 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3596 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3597 struct hdac_cea_channel_speaker_allocation *cap,
3598 unsigned int *chmap, int channels)
3600 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3604 for (c = 7; c >= 0; c--) {
3605 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3606 int spk = cap->speakers[chan];
3608 /* add N/A channel if the companion channel is occupied */
3609 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3610 chmap[count++] = SNDRV_CHMAP_NA;
3615 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3618 WARN_ON(count != channels);
3621 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3624 int hbr_ctl, hbr_ctl_new;
3626 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3627 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3629 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3631 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3634 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3636 hbr_ctl == hbr_ctl_new ? "" : "new-",
3639 if (hbr_ctl != hbr_ctl_new)
3640 snd_hda_codec_write(codec, pin_nid, 0,
3641 ATI_VERB_SET_HBR_CONTROL,
3650 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3651 hda_nid_t pin_nid, u32 stream_tag, int format)
3654 if (is_amdhdmi_rev3_or_later(codec)) {
3655 int ramp_rate = 180; /* default as per AMD spec */
3656 /* disable ramp-up/down for non-pcm as per AMD spec */
3657 if (format & AC_FMT_TYPE_NON_PCM)
3660 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3663 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3667 static int atihdmi_init(struct hda_codec *codec)
3669 struct hdmi_spec *spec = codec->spec;
3672 err = generic_hdmi_init(codec);
3677 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3678 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3680 /* make sure downmix information in infoframe is zero */
3681 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3683 /* enable channel-wise remap mode if supported */
3684 if (has_amd_full_remap_support(codec))
3685 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3686 ATI_VERB_SET_MULTICHANNEL_MODE,
3687 ATI_MULTICHANNEL_MODE_SINGLE);
3693 static int patch_atihdmi(struct hda_codec *codec)
3695 struct hdmi_spec *spec;
3696 struct hdmi_spec_per_cvt *per_cvt;
3699 err = patch_generic_hdmi(codec);
3704 codec->patch_ops.init = atihdmi_init;
3708 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3709 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3710 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3711 spec->ops.setup_stream = atihdmi_setup_stream;
3713 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3714 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3716 if (!has_amd_full_remap_support(codec)) {
3717 /* override to ATI/AMD-specific versions with pairwise mapping */
3718 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3719 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3720 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3721 atihdmi_paired_cea_alloc_to_tlv_chmap;
3722 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3725 /* ATI/AMD converters do not advertise all of their capabilities */
3726 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3727 per_cvt = get_cvt(spec, cvt_idx);
3728 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3729 per_cvt->rates |= SUPPORTED_RATES;
3730 per_cvt->formats |= SUPPORTED_FORMATS;
3731 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3734 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3739 /* VIA HDMI Implementation */
3740 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3741 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3743 static int patch_via_hdmi(struct hda_codec *codec)
3745 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3751 static const struct hda_device_id snd_hda_id_hdmi[] = {
3752 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3753 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3754 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3755 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3756 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3757 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3758 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3759 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3760 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3761 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3762 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3763 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3764 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3765 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3766 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3767 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3768 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3769 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3770 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3771 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3772 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3773 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3774 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3775 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3776 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3777 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3778 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3779 /* 17 is known to be absent */
3780 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3781 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3782 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3783 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3784 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3785 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3786 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3787 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3788 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3789 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3790 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3791 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3792 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3793 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3794 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3795 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3796 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3797 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3798 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3799 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3800 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3801 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3802 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3803 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3804 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3805 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3806 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3807 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3808 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3809 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3810 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3811 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3812 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3813 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3814 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3815 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3816 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3817 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3818 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3819 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3820 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3821 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3822 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3823 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3824 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3825 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3826 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3827 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3828 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3829 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3830 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3831 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3832 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3833 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3834 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3835 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3836 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3837 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3838 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3839 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3840 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3841 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3842 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3843 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3844 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3845 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3846 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3847 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3848 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3849 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3850 /* special ID for generic HDMI */
3851 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3854 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3856 MODULE_LICENSE("GPL");
3857 MODULE_DESCRIPTION("HDMI HD-audio codec");
3858 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3859 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3860 MODULE_ALIAS("snd-hda-codec-atihdmi");
3862 static struct hda_codec_driver hdmi_driver = {
3863 .id = snd_hda_id_hdmi,
3866 module_hda_codec_driver(hdmi_driver);