1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
50 MODULE_FIRMWARE("rpm_firmware.bin");
51 MODULE_FIRMWARE("multiface_firmware.bin");
52 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
53 MODULE_FIRMWARE("digiface_firmware.bin");
54 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
56 #define HDSP_MAX_CHANNELS 26
57 #define HDSP_MAX_DS_CHANNELS 14
58 #define HDSP_MAX_QS_CHANNELS 8
59 #define DIGIFACE_SS_CHANNELS 26
60 #define DIGIFACE_DS_CHANNELS 14
61 #define MULTIFACE_SS_CHANNELS 18
62 #define MULTIFACE_DS_CHANNELS 14
63 #define H9652_SS_CHANNELS 26
64 #define H9652_DS_CHANNELS 14
65 /* This does not include possible Analog Extension Boards
66 AEBs are detected at card initialization
68 #define H9632_SS_CHANNELS 12
69 #define H9632_DS_CHANNELS 8
70 #define H9632_QS_CHANNELS 4
71 #define RPM_CHANNELS 6
73 /* Write registers. These are defined as byte-offsets from the iobase value.
75 #define HDSP_resetPointer 0
76 #define HDSP_freqReg 0
77 #define HDSP_outputBufferAddress 32
78 #define HDSP_inputBufferAddress 36
79 #define HDSP_controlRegister 64
80 #define HDSP_interruptConfirmation 96
81 #define HDSP_outputEnable 128
82 #define HDSP_control2Reg 256
83 #define HDSP_midiDataOut0 352
84 #define HDSP_midiDataOut1 356
85 #define HDSP_fifoData 368
86 #define HDSP_inputEnable 384
88 /* Read registers. These are defined as byte-offsets from the iobase value
91 #define HDSP_statusRegister 0
92 #define HDSP_timecode 128
93 #define HDSP_status2Register 192
94 #define HDSP_midiDataIn0 360
95 #define HDSP_midiDataIn1 364
96 #define HDSP_midiStatusOut0 384
97 #define HDSP_midiStatusOut1 388
98 #define HDSP_midiStatusIn0 392
99 #define HDSP_midiStatusIn1 396
100 #define HDSP_fifoStatus 400
102 /* the meters are regular i/o-mapped registers, but offset
103 considerably from the rest. the peak registers are reset
104 when read; the least-significant 4 bits are full-scale counters;
105 the actual peak value is in the most-significant 24 bits.
108 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
109 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
110 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
111 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
112 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
115 /* This is for H9652 cards
116 Peak values are read downward from the base
117 Rms values are read upward
118 There are rms values for the outputs too
119 26*3 values are read in ss mode
120 14*3 in ds mode, with no gap between values
122 #define HDSP_9652_peakBase 7164
123 #define HDSP_9652_rmsBase 4096
125 /* c.f. the hdsp_9632_meters_t struct */
126 #define HDSP_9632_metersBase 4096
128 #define HDSP_IO_EXTENT 7168
130 /* control2 register bits */
132 #define HDSP_TMS 0x01
133 #define HDSP_TCK 0x02
134 #define HDSP_TDI 0x04
135 #define HDSP_JTAG 0x08
136 #define HDSP_PWDN 0x10
137 #define HDSP_PROGRAM 0x020
138 #define HDSP_CONFIG_MODE_0 0x040
139 #define HDSP_CONFIG_MODE_1 0x080
140 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
141 #define HDSP_BIGENDIAN_MODE 0x200
142 #define HDSP_RD_MULTIPLE 0x400
143 #define HDSP_9652_ENABLE_MIXER 0x800
144 #define HDSP_S200 0x800
145 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
146 #define HDSP_CYCLIC_MODE 0x1000
147 #define HDSP_TDO 0x10000000
149 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
150 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
152 /* Control Register bits */
154 #define HDSP_Start (1<<0) /* start engine */
155 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
156 #define HDSP_Latency1 (1<<2) /* [ see above ] */
157 #define HDSP_Latency2 (1<<3) /* [ see above ] */
158 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
159 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
160 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
161 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
162 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
163 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
164 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
165 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
166 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
167 #define HDSP_SyncRef2 (1<<13)
168 #define HDSP_SPDIFInputSelect0 (1<<14)
169 #define HDSP_SPDIFInputSelect1 (1<<15)
170 #define HDSP_SyncRef0 (1<<16)
171 #define HDSP_SyncRef1 (1<<17)
172 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
173 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
174 #define HDSP_Midi0InterruptEnable (1<<22)
175 #define HDSP_Midi1InterruptEnable (1<<23)
176 #define HDSP_LineOut (1<<24)
177 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
178 #define HDSP_ADGain1 (1<<26)
179 #define HDSP_DAGain0 (1<<27)
180 #define HDSP_DAGain1 (1<<28)
181 #define HDSP_PhoneGain0 (1<<29)
182 #define HDSP_PhoneGain1 (1<<30)
183 #define HDSP_QuadSpeed (1<<31)
185 /* RPM uses some of the registers for special purposes */
186 #define HDSP_RPM_Inp12 0x04A00
187 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
188 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
189 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
190 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
191 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
193 #define HDSP_RPM_Inp34 0x32000
194 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
195 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
196 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
197 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
198 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
200 #define HDSP_RPM_Bypass 0x01000
202 #define HDSP_RPM_Disconnect 0x00001
204 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
205 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
206 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
207 #define HDSP_ADGainLowGain 0
209 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
210 #define HDSP_DAGainHighGain HDSP_DAGainMask
211 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
212 #define HDSP_DAGainMinus10dBV 0
214 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
215 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
216 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
217 #define HDSP_PhoneGainMinus12dB 0
219 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
220 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
222 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputADAT1 0
224 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
225 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
226 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
228 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
229 #define HDSP_SyncRef_ADAT1 0
230 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
231 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
232 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
233 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
234 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
236 /* Sample Clock Sources */
238 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
239 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
240 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
241 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
242 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
243 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
244 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
245 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
246 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
247 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
249 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
251 #define HDSP_SYNC_FROM_WORD 0
252 #define HDSP_SYNC_FROM_SPDIF 1
253 #define HDSP_SYNC_FROM_ADAT1 2
254 #define HDSP_SYNC_FROM_ADAT_SYNC 3
255 #define HDSP_SYNC_FROM_ADAT2 4
256 #define HDSP_SYNC_FROM_ADAT3 5
258 /* SyncCheck status */
260 #define HDSP_SYNC_CHECK_NO_LOCK 0
261 #define HDSP_SYNC_CHECK_LOCK 1
262 #define HDSP_SYNC_CHECK_SYNC 2
264 /* AutoSync references - used by "autosync_ref" control switch */
266 #define HDSP_AUTOSYNC_FROM_WORD 0
267 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
268 #define HDSP_AUTOSYNC_FROM_SPDIF 2
269 #define HDSP_AUTOSYNC_FROM_NONE 3
270 #define HDSP_AUTOSYNC_FROM_ADAT1 4
271 #define HDSP_AUTOSYNC_FROM_ADAT2 5
272 #define HDSP_AUTOSYNC_FROM_ADAT3 6
274 /* Possible sources of S/PDIF input */
276 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
277 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
278 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
279 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
281 #define HDSP_Frequency32KHz HDSP_Frequency0
282 #define HDSP_Frequency44_1KHz HDSP_Frequency1
283 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
284 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
285 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
286 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287 /* For H9632 cards */
288 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
289 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
290 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
291 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
292 return 104857600000000 / rate; // 100 MHz
293 return 110100480000000 / rate; // 105 MHz
295 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
297 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
298 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
300 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
301 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
303 /* Status Register bits */
305 #define HDSP_audioIRQPending (1<<0)
306 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
307 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
308 #define HDSP_Lock1 (1<<2)
309 #define HDSP_Lock0 (1<<3)
310 #define HDSP_SPDIFSync (1<<4)
311 #define HDSP_TimecodeLock (1<<5)
312 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
313 #define HDSP_Sync2 (1<<16)
314 #define HDSP_Sync1 (1<<17)
315 #define HDSP_Sync0 (1<<18)
316 #define HDSP_DoubleSpeedStatus (1<<19)
317 #define HDSP_ConfigError (1<<20)
318 #define HDSP_DllError (1<<21)
319 #define HDSP_spdifFrequency0 (1<<22)
320 #define HDSP_spdifFrequency1 (1<<23)
321 #define HDSP_spdifFrequency2 (1<<24)
322 #define HDSP_SPDIFErrorFlag (1<<25)
323 #define HDSP_BufferID (1<<26)
324 #define HDSP_TimecodeSync (1<<27)
325 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
326 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
327 #define HDSP_midi0IRQPending (1<<30)
328 #define HDSP_midi1IRQPending (1<<31)
330 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
331 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
332 HDSP_spdifFrequency1|\
333 HDSP_spdifFrequency2|\
334 HDSP_spdifFrequency3)
336 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
337 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
338 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
340 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
342 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
344 /* This is for H9632 cards */
345 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2)
348 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
349 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
351 /* Status2 Register bits */
353 #define HDSP_version0 (1<<0)
354 #define HDSP_version1 (1<<1)
355 #define HDSP_version2 (1<<2)
356 #define HDSP_wc_lock (1<<3)
357 #define HDSP_wc_sync (1<<4)
358 #define HDSP_inp_freq0 (1<<5)
359 #define HDSP_inp_freq1 (1<<6)
360 #define HDSP_inp_freq2 (1<<7)
361 #define HDSP_SelSyncRef0 (1<<8)
362 #define HDSP_SelSyncRef1 (1<<9)
363 #define HDSP_SelSyncRef2 (1<<10)
365 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
367 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
368 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
369 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
370 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
371 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
372 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
373 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
374 /* FIXME : more values for 9632 cards ? */
376 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
377 #define HDSP_SelSyncRef_ADAT1 0
378 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
379 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
380 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
381 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
382 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
384 /* Card state flags */
386 #define HDSP_InitializationComplete (1<<0)
387 #define HDSP_FirmwareLoaded (1<<1)
388 #define HDSP_FirmwareCached (1<<2)
390 /* FIFO wait times, defined in terms of 1/10ths of msecs */
392 #define HDSP_LONG_WAIT 5000
393 #define HDSP_SHORT_WAIT 30
395 #define UNITY_GAIN 32768
396 #define MINUS_INFINITY_GAIN 0
398 /* the size of a substream (1 mono data stream) */
400 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
401 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
403 /* the size of the area we need to allocate for DMA transfers. the
404 size is the same regardless of the number of channels - the
405 Multiface still uses the same memory area.
407 Note that we allocate 1 more channel than is apparently needed
408 because the h/w seems to write 1 byte beyond the end of the last
412 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
413 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
415 #define HDSP_FIRMWARE_SIZE (24413 * 4)
417 struct hdsp_9632_meters {
419 u32 playback_peak[16];
423 u32 input_rms_low[16];
424 u32 playback_rms_low[16];
425 u32 output_rms_low[16];
427 u32 input_rms_high[16];
428 u32 playback_rms_high[16];
429 u32 output_rms_high[16];
430 u32 xxx_rms_high[16];
436 struct snd_rawmidi *rmidi;
437 struct snd_rawmidi_substream *input;
438 struct snd_rawmidi_substream *output;
439 char istimer; /* timer in use */
440 struct timer_list timer;
447 struct snd_pcm_substream *capture_substream;
448 struct snd_pcm_substream *playback_substream;
449 struct hdsp_midi midi[2];
450 struct tasklet_struct midi_tasklet;
451 int use_midi_tasklet;
453 u32 control_register; /* cached value */
454 u32 control2_register; /* cached value */
456 u32 creg_spdif_stream;
457 int clock_source_locked;
458 char *card_name; /* digiface/multiface/rpm */
459 enum HDSP_IO_Type io_type; /* ditto, but for code use */
460 unsigned short firmware_rev;
461 unsigned short state; /* stores state bits */
462 const struct firmware *firmware;
464 size_t period_bytes; /* guess what this is */
465 unsigned char max_channels;
466 unsigned char qs_in_channels; /* quad speed mode for H9632 */
467 unsigned char ds_in_channels;
468 unsigned char ss_in_channels; /* different for multiface/digiface */
469 unsigned char qs_out_channels;
470 unsigned char ds_out_channels;
471 unsigned char ss_out_channels;
473 struct snd_dma_buffer capture_dma_buf;
474 struct snd_dma_buffer playback_dma_buf;
475 unsigned char *capture_buffer; /* suitably aligned address */
476 unsigned char *playback_buffer; /* suitably aligned address */
481 int system_sample_rate;
486 void __iomem *iobase;
487 struct snd_card *card;
489 struct snd_hwdep *hwdep;
491 struct snd_kcontrol *spdif_ctl;
492 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
493 unsigned int dds_value; /* last value written to freq register */
496 /* These tables map the ALSA channels 1..N to the channels that we
497 need to use in order to find the relevant channel buffer. RME
498 refer to this kind of mapping as between "the ADAT channel and
499 the DMA channel." We index it using the logical audio channel,
500 and the value is the DMA channel (i.e. channel buffer number)
501 where the data for that channel can be read/written from/to.
504 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
505 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
506 18, 19, 20, 21, 22, 23, 24, 25
509 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
511 0, 1, 2, 3, 4, 5, 6, 7,
513 16, 17, 18, 19, 20, 21, 22, 23,
516 -1, -1, -1, -1, -1, -1, -1, -1
519 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
520 /* ADAT channels are remapped */
521 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
522 /* channels 12 and 13 are S/PDIF */
524 /* others don't exist */
525 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
528 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
530 0, 1, 2, 3, 4, 5, 6, 7,
535 /* AO4S-192 and AI4S-192 extension boards */
537 /* others don't exist */
538 -1, -1, -1, -1, -1, -1, -1, -1,
542 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
549 /* AO4S-192 and AI4S-192 extension boards */
551 /* others don't exist */
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1, -1, -1, -1, -1
556 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
557 /* ADAT is disabled in this mode */
562 /* AO4S-192 and AI4S-192 extension boards */
564 /* others don't exist */
565 -1, -1, -1, -1, -1, -1, -1, -1,
566 -1, -1, -1, -1, -1, -1, -1, -1,
570 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
572 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
575 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
578 snd_dma_free_pages(dmab);
582 static const struct pci_device_id snd_hdsp_ids[] = {
584 .vendor = PCI_VENDOR_ID_XILINX,
585 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586 .subvendor = PCI_ANY_ID,
587 .subdevice = PCI_ANY_ID,
588 }, /* RME Hammerfall-DSP */
592 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
595 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
596 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
597 static int snd_hdsp_enable_io (struct hdsp *hdsp);
598 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
599 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
600 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
601 static int hdsp_autosync_ref(struct hdsp *hdsp);
602 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
603 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
605 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
607 switch (hdsp->io_type) {
612 if (hdsp->firmware_rev == 0xa)
613 return (64 * out) + (32 + (in));
615 return (52 * out) + (26 + (in));
617 return (32 * out) + (16 + (in));
619 return (52 * out) + (26 + (in));
623 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
625 switch (hdsp->io_type) {
630 if (hdsp->firmware_rev == 0xa)
631 return (64 * out) + in;
633 return (52 * out) + in;
635 return (32 * out) + in;
637 return (52 * out) + in;
641 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
643 writel(val, hdsp->iobase + reg);
646 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
648 return readl (hdsp->iobase + reg);
651 static int hdsp_check_for_iobox (struct hdsp *hdsp)
655 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
656 for (i = 0; i < 500; i++) {
657 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
660 dev_dbg(hdsp->card->dev,
661 "IO box found after %d ms\n",
668 dev_err(hdsp->card->dev, "no IO box connected!\n");
669 hdsp->state &= ~HDSP_FirmwareLoaded;
673 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
678 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
681 for (i = 0; i != loops; ++i) {
682 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
685 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
691 dev_info(hdsp->card->dev, "no IO box connected!\n");
692 hdsp->state &= ~HDSP_FirmwareLoaded;
696 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
702 if (hdsp->fw_uploaded)
703 cache = hdsp->fw_uploaded;
707 cache = (u32 *)hdsp->firmware->data;
712 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
714 dev_info(hdsp->card->dev, "loading firmware\n");
716 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
717 hdsp_write (hdsp, HDSP_fifoData, 0);
719 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
720 dev_info(hdsp->card->dev,
721 "timeout waiting for download preparation\n");
722 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
726 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
728 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
729 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
730 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
731 dev_info(hdsp->card->dev,
732 "timeout during firmware loading\n");
733 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
738 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
739 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
742 #ifdef SNDRV_BIG_ENDIAN
743 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
745 hdsp->control2_register = 0;
747 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
748 dev_info(hdsp->card->dev, "finished firmware loading\n");
751 if (hdsp->state & HDSP_InitializationComplete) {
752 dev_info(hdsp->card->dev,
753 "firmware loaded from cache, restoring defaults\n");
754 spin_lock_irqsave(&hdsp->lock, flags);
755 snd_hdsp_set_defaults(hdsp);
756 spin_unlock_irqrestore(&hdsp->lock, flags);
759 hdsp->state |= HDSP_FirmwareLoaded;
764 static int hdsp_get_iobox_version (struct hdsp *hdsp)
766 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
769 hdsp_write(hdsp, HDSP_fifoData, 0);
771 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
772 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
773 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
777 hdsp_write (hdsp, HDSP_fifoData, 0);
778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
781 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
782 hdsp_write(hdsp, HDSP_fifoData, 0);
783 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
784 hdsp->io_type = Digiface;
785 dev_info(hdsp->card->dev, "Digiface found\n");
789 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791 hdsp_write(hdsp, HDSP_fifoData, 0);
792 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
797 hdsp_write(hdsp, HDSP_fifoData, 0);
798 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
802 dev_info(hdsp->card->dev, "RPM found\n");
805 /* firmware was already loaded, get iobox type */
806 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
808 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
809 hdsp->io_type = Multiface;
811 hdsp->io_type = Digiface;
816 hdsp->io_type = Multiface;
817 dev_info(hdsp->card->dev, "Multiface found\n");
822 static int hdsp_request_fw_loader(struct hdsp *hdsp);
824 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
826 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
828 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
829 hdsp->state &= ~HDSP_FirmwareLoaded;
830 if (! load_on_demand)
832 dev_err(hdsp->card->dev, "firmware not present.\n");
833 /* try to load firmware */
834 if (! (hdsp->state & HDSP_FirmwareCached)) {
835 if (! hdsp_request_fw_loader(hdsp))
837 dev_err(hdsp->card->dev,
838 "No firmware loaded nor cached, please upload firmware.\n");
841 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
842 dev_err(hdsp->card->dev,
843 "Firmware loading from cache failed, please upload manually.\n");
851 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
855 /* the fifoStatus registers reports on how many words
856 are available in the command FIFO.
859 for (i = 0; i < timeout; i++) {
861 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
864 /* not very friendly, but we only do this during a firmware
865 load and changing the mixer, so we just put up with it.
871 dev_warn(hdsp->card->dev,
872 "wait for FIFO status <= %d failed after %d iterations\n",
877 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
879 if (addr >= HDSP_MATRIX_MIXER_SIZE)
882 return hdsp->mixer_matrix[addr];
885 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
889 if (addr >= HDSP_MATRIX_MIXER_SIZE)
892 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
894 /* from martin bjornsen:
896 "You can only write dwords to the
897 mixer memory which contain two
898 mixer values in the low and high
899 word. So if you want to change
900 value 0 you have to read value 1
901 from the cache and write both to
902 the first dword in the mixer
906 if (hdsp->io_type == H9632 && addr >= 512)
909 if (hdsp->io_type == H9652 && addr >= 1352)
912 hdsp->mixer_matrix[addr] = data;
915 /* `addr' addresses a 16-bit wide address, but
916 the address space accessed via hdsp_write
917 uses byte offsets. put another way, addr
918 varies from 0 to 1351, but to access the
919 corresponding memory location, we need
920 to access 0 to 2703 ...
924 hdsp_write (hdsp, 4096 + (ad*4),
925 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
926 hdsp->mixer_matrix[addr&0x7fe]);
932 ad = (addr << 16) + data;
934 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
937 hdsp_write (hdsp, HDSP_fifoData, ad);
938 hdsp->mixer_matrix[addr] = data;
945 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
950 spin_lock_irqsave(&hdsp->lock, flags);
951 if ((hdsp->playback_pid != hdsp->capture_pid) &&
952 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
954 spin_unlock_irqrestore(&hdsp->lock, flags);
958 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
960 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
961 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
963 /* For the 9632, the mask is different */
964 if (hdsp->io_type == H9632)
965 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
967 if (status & HDSP_SPDIFErrorFlag)
971 case HDSP_spdifFrequency32KHz: return 32000;
972 case HDSP_spdifFrequency44_1KHz: return 44100;
973 case HDSP_spdifFrequency48KHz: return 48000;
974 case HDSP_spdifFrequency64KHz: return 64000;
975 case HDSP_spdifFrequency88_2KHz: return 88200;
976 case HDSP_spdifFrequency96KHz: return 96000;
977 case HDSP_spdifFrequency128KHz:
978 if (hdsp->io_type == H9632) return 128000;
980 case HDSP_spdifFrequency176_4KHz:
981 if (hdsp->io_type == H9632) return 176400;
983 case HDSP_spdifFrequency192KHz:
984 if (hdsp->io_type == H9632) return 192000;
989 dev_warn(hdsp->card->dev,
990 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
995 static int hdsp_external_sample_rate(struct hdsp *hdsp)
997 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
998 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1000 /* For the 9632 card, there seems to be no bit for indicating external
1001 * sample rate greater than 96kHz. The card reports the corresponding
1002 * single speed. So the best means seems to get spdif rate when
1003 * autosync reference is spdif */
1004 if (hdsp->io_type == H9632 &&
1005 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1006 return hdsp_spdif_sample_rate(hdsp);
1008 switch (rate_bits) {
1009 case HDSP_systemFrequency32: return 32000;
1010 case HDSP_systemFrequency44_1: return 44100;
1011 case HDSP_systemFrequency48: return 48000;
1012 case HDSP_systemFrequency64: return 64000;
1013 case HDSP_systemFrequency88_2: return 88200;
1014 case HDSP_systemFrequency96: return 96000;
1020 static void hdsp_compute_period_size(struct hdsp *hdsp)
1022 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1025 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1029 position = hdsp_read(hdsp, HDSP_statusRegister);
1031 if (!hdsp->precise_ptr)
1032 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1034 position &= HDSP_BufferPositionMask;
1036 position &= (hdsp->period_bytes/2) - 1;
1040 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1042 hdsp_write (hdsp, HDSP_resetPointer, 0);
1043 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1044 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1045 * requires (?) to write again DDS value after a reset pointer
1046 * (at least, it works like this) */
1047 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1050 static void hdsp_start_audio(struct hdsp *s)
1052 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1053 hdsp_write(s, HDSP_controlRegister, s->control_register);
1056 static void hdsp_stop_audio(struct hdsp *s)
1058 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1059 hdsp_write(s, HDSP_controlRegister, s->control_register);
1062 static void hdsp_silence_playback(struct hdsp *hdsp)
1064 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1067 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1071 spin_lock_irq(&s->lock);
1080 s->control_register &= ~HDSP_LatencyMask;
1081 s->control_register |= hdsp_encode_latency(n);
1083 hdsp_write(s, HDSP_controlRegister, s->control_register);
1085 hdsp_compute_period_size(s);
1087 spin_unlock_irq(&s->lock);
1092 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1098 else if (rate >= 56000)
1102 n = div_u64(n, rate);
1103 /* n should be less than 2^32 for being written to FREQ register */
1104 snd_BUG_ON(n >> 32);
1105 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1106 value to write it after a reset */
1107 hdsp->dds_value = n;
1108 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1111 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1113 int reject_if_open = 0;
1117 /* ASSUMPTION: hdsp->lock is either held, or
1118 there is no need for it (e.g. during module
1122 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1123 if (called_internally) {
1124 /* request from ctl or card initialization */
1125 dev_err(hdsp->card->dev,
1126 "device is not running as a clock master: cannot set sample rate.\n");
1129 /* hw_param request while in AutoSync mode */
1130 int external_freq = hdsp_external_sample_rate(hdsp);
1131 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1133 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1134 dev_info(hdsp->card->dev,
1135 "Detected ADAT in double speed mode\n");
1136 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1137 dev_info(hdsp->card->dev,
1138 "Detected ADAT in quad speed mode\n");
1139 else if (rate != external_freq) {
1140 dev_info(hdsp->card->dev,
1141 "No AutoSync source for requested rate\n");
1147 current_rate = hdsp->system_sample_rate;
1149 /* Changing from a "single speed" to a "double speed" rate is
1150 not allowed if any substreams are open. This is because
1151 such a change causes a shift in the location of
1152 the DMA buffers and a reduction in the number of available
1155 Note that a similar but essentially insoluble problem
1156 exists for externally-driven rate changes. All we can do
1157 is to flag rate changes in the read/write routines. */
1159 if (rate > 96000 && hdsp->io_type != H9632)
1164 if (current_rate > 48000)
1166 rate_bits = HDSP_Frequency32KHz;
1169 if (current_rate > 48000)
1171 rate_bits = HDSP_Frequency44_1KHz;
1174 if (current_rate > 48000)
1176 rate_bits = HDSP_Frequency48KHz;
1179 if (current_rate <= 48000 || current_rate > 96000)
1181 rate_bits = HDSP_Frequency64KHz;
1184 if (current_rate <= 48000 || current_rate > 96000)
1186 rate_bits = HDSP_Frequency88_2KHz;
1189 if (current_rate <= 48000 || current_rate > 96000)
1191 rate_bits = HDSP_Frequency96KHz;
1194 if (current_rate < 128000)
1196 rate_bits = HDSP_Frequency128KHz;
1199 if (current_rate < 128000)
1201 rate_bits = HDSP_Frequency176_4KHz;
1204 if (current_rate < 128000)
1206 rate_bits = HDSP_Frequency192KHz;
1212 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1213 dev_warn(hdsp->card->dev,
1214 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1216 hdsp->playback_pid);
1220 hdsp->control_register &= ~HDSP_FrequencyMask;
1221 hdsp->control_register |= rate_bits;
1222 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1224 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1225 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1226 hdsp_set_dds_value(hdsp, rate);
1228 if (rate >= 128000) {
1229 hdsp->channel_map = channel_map_H9632_qs;
1230 } else if (rate > 48000) {
1231 if (hdsp->io_type == H9632)
1232 hdsp->channel_map = channel_map_H9632_ds;
1234 hdsp->channel_map = channel_map_ds;
1236 switch (hdsp->io_type) {
1239 hdsp->channel_map = channel_map_mf_ss;
1243 hdsp->channel_map = channel_map_df_ss;
1246 hdsp->channel_map = channel_map_H9632_ss;
1249 /* should never happen */
1254 hdsp->system_sample_rate = rate;
1259 /*----------------------------------------------------------------------------
1261 ----------------------------------------------------------------------------*/
1263 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1265 /* the hardware already does the relevant bit-mask with 0xff */
1267 return hdsp_read(hdsp, HDSP_midiDataIn1);
1269 return hdsp_read(hdsp, HDSP_midiDataIn0);
1272 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1274 /* the hardware already does the relevant bit-mask with 0xff */
1276 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1278 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1281 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1284 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1286 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1289 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1291 int fifo_bytes_used;
1294 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1296 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1298 if (fifo_bytes_used < 128)
1299 return 128 - fifo_bytes_used;
1304 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1306 while (snd_hdsp_midi_input_available (hdsp, id))
1307 snd_hdsp_midi_read_byte (hdsp, id);
1310 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1312 unsigned long flags;
1316 unsigned char buf[128];
1318 /* Output is not interrupt driven */
1320 spin_lock_irqsave (&hmidi->lock, flags);
1321 if (hmidi->output) {
1322 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1323 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1324 if (n_pending > (int)sizeof (buf))
1325 n_pending = sizeof (buf);
1327 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1328 for (i = 0; i < to_write; ++i)
1329 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1334 spin_unlock_irqrestore (&hmidi->lock, flags);
1338 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1340 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1341 unsigned long flags;
1345 spin_lock_irqsave (&hmidi->lock, flags);
1346 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1348 if (n_pending > (int)sizeof (buf))
1349 n_pending = sizeof (buf);
1350 for (i = 0; i < n_pending; ++i)
1351 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1353 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1355 /* flush the MIDI input FIFO */
1357 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1362 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1364 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1365 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1366 spin_unlock_irqrestore (&hmidi->lock, flags);
1367 return snd_hdsp_midi_output_write (hmidi);
1370 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1373 struct hdsp_midi *hmidi;
1374 unsigned long flags;
1377 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1379 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1380 spin_lock_irqsave (&hdsp->lock, flags);
1382 if (!(hdsp->control_register & ie)) {
1383 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1384 hdsp->control_register |= ie;
1387 hdsp->control_register &= ~ie;
1388 tasklet_kill(&hdsp->midi_tasklet);
1391 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1392 spin_unlock_irqrestore (&hdsp->lock, flags);
1395 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1397 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1398 unsigned long flags;
1400 snd_hdsp_midi_output_write(hmidi);
1401 spin_lock_irqsave (&hmidi->lock, flags);
1403 /* this does not bump hmidi->istimer, because the
1404 kernel automatically removed the timer when it
1405 expired, and we are now adding it back, thus
1406 leaving istimer wherever it was set before.
1410 mod_timer(&hmidi->timer, 1 + jiffies);
1412 spin_unlock_irqrestore (&hmidi->lock, flags);
1415 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1417 struct hdsp_midi *hmidi;
1418 unsigned long flags;
1420 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1421 spin_lock_irqsave (&hmidi->lock, flags);
1423 if (!hmidi->istimer) {
1424 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1426 mod_timer(&hmidi->timer, 1 + jiffies);
1430 if (hmidi->istimer && --hmidi->istimer <= 0)
1431 del_timer (&hmidi->timer);
1433 spin_unlock_irqrestore (&hmidi->lock, flags);
1435 snd_hdsp_midi_output_write(hmidi);
1438 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1440 struct hdsp_midi *hmidi;
1442 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1443 spin_lock_irq (&hmidi->lock);
1444 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1445 hmidi->input = substream;
1446 spin_unlock_irq (&hmidi->lock);
1451 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1453 struct hdsp_midi *hmidi;
1455 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1456 spin_lock_irq (&hmidi->lock);
1457 hmidi->output = substream;
1458 spin_unlock_irq (&hmidi->lock);
1463 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1465 struct hdsp_midi *hmidi;
1467 snd_hdsp_midi_input_trigger (substream, 0);
1469 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1470 spin_lock_irq (&hmidi->lock);
1471 hmidi->input = NULL;
1472 spin_unlock_irq (&hmidi->lock);
1477 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1479 struct hdsp_midi *hmidi;
1481 snd_hdsp_midi_output_trigger (substream, 0);
1483 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1484 spin_lock_irq (&hmidi->lock);
1485 hmidi->output = NULL;
1486 spin_unlock_irq (&hmidi->lock);
1491 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1493 .open = snd_hdsp_midi_output_open,
1494 .close = snd_hdsp_midi_output_close,
1495 .trigger = snd_hdsp_midi_output_trigger,
1498 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1500 .open = snd_hdsp_midi_input_open,
1501 .close = snd_hdsp_midi_input_close,
1502 .trigger = snd_hdsp_midi_input_trigger,
1505 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1509 hdsp->midi[id].id = id;
1510 hdsp->midi[id].rmidi = NULL;
1511 hdsp->midi[id].input = NULL;
1512 hdsp->midi[id].output = NULL;
1513 hdsp->midi[id].hdsp = hdsp;
1514 hdsp->midi[id].istimer = 0;
1515 hdsp->midi[id].pending = 0;
1516 spin_lock_init (&hdsp->midi[id].lock);
1518 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1519 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1522 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1523 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1525 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1526 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1528 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1529 SNDRV_RAWMIDI_INFO_INPUT |
1530 SNDRV_RAWMIDI_INFO_DUPLEX;
1535 /*-----------------------------------------------------------------------------
1537 ----------------------------------------------------------------------------*/
1539 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1542 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1543 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1544 if (val & HDSP_SPDIFProfessional)
1545 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1547 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1551 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1553 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1554 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1555 if (val & HDSP_SPDIFProfessional)
1556 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1558 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1561 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1563 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1568 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1572 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1576 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1578 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1582 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1583 spin_lock_irq(&hdsp->lock);
1584 change = val != hdsp->creg_spdif;
1585 hdsp->creg_spdif = val;
1586 spin_unlock_irq(&hdsp->lock);
1590 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1592 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1597 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1599 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1605 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1607 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1611 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1612 spin_lock_irq(&hdsp->lock);
1613 change = val != hdsp->creg_spdif_stream;
1614 hdsp->creg_spdif_stream = val;
1615 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1616 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1617 spin_unlock_irq(&hdsp->lock);
1621 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1623 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1628 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1630 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1634 #define HDSP_SPDIF_IN(xname, xindex) \
1635 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1638 .info = snd_hdsp_info_spdif_in, \
1639 .get = snd_hdsp_get_spdif_in, \
1640 .put = snd_hdsp_put_spdif_in }
1642 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1644 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1647 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1649 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1650 hdsp->control_register |= hdsp_encode_spdif_in(in);
1651 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1655 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1657 static const char * const texts[4] = {
1658 "Optical", "Coaxial", "Internal", "AES"
1660 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1662 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1666 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1668 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1670 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1674 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1676 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1680 if (!snd_hdsp_use_is_exclusive(hdsp))
1682 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1683 spin_lock_irq(&hdsp->lock);
1684 change = val != hdsp_spdif_in(hdsp);
1686 hdsp_set_spdif_input(hdsp, val);
1687 spin_unlock_irq(&hdsp->lock);
1691 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1692 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1694 .private_value = xindex, \
1695 .info = snd_hdsp_info_toggle_setting, \
1696 .get = snd_hdsp_get_toggle_setting, \
1697 .put = snd_hdsp_put_toggle_setting \
1700 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1702 return (hdsp->control_register & regmask) ? 1 : 0;
1705 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1708 hdsp->control_register |= regmask;
1710 hdsp->control_register &= ~regmask;
1711 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1716 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1718 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1719 struct snd_ctl_elem_value *ucontrol)
1721 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1722 u32 regmask = kcontrol->private_value;
1724 spin_lock_irq(&hdsp->lock);
1725 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1726 spin_unlock_irq(&hdsp->lock);
1730 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1731 struct snd_ctl_elem_value *ucontrol)
1733 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1734 u32 regmask = kcontrol->private_value;
1738 if (!snd_hdsp_use_is_exclusive(hdsp))
1740 val = ucontrol->value.integer.value[0] & 1;
1741 spin_lock_irq(&hdsp->lock);
1742 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1744 hdsp_set_toggle_setting(hdsp, regmask, val);
1745 spin_unlock_irq(&hdsp->lock);
1749 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1750 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1753 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1754 .info = snd_hdsp_info_spdif_sample_rate, \
1755 .get = snd_hdsp_get_spdif_sample_rate \
1758 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1760 static const char * const texts[] = {
1761 "32000", "44100", "48000", "64000", "88200", "96000",
1762 "None", "128000", "176400", "192000"
1764 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1766 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1770 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1772 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1774 switch (hdsp_spdif_sample_rate(hdsp)) {
1776 ucontrol->value.enumerated.item[0] = 0;
1779 ucontrol->value.enumerated.item[0] = 1;
1782 ucontrol->value.enumerated.item[0] = 2;
1785 ucontrol->value.enumerated.item[0] = 3;
1788 ucontrol->value.enumerated.item[0] = 4;
1791 ucontrol->value.enumerated.item[0] = 5;
1794 ucontrol->value.enumerated.item[0] = 7;
1797 ucontrol->value.enumerated.item[0] = 8;
1800 ucontrol->value.enumerated.item[0] = 9;
1803 ucontrol->value.enumerated.item[0] = 6;
1808 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1812 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1813 .info = snd_hdsp_info_system_sample_rate, \
1814 .get = snd_hdsp_get_system_sample_rate \
1817 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1819 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1824 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1826 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1828 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1832 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1836 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1837 .info = snd_hdsp_info_autosync_sample_rate, \
1838 .get = snd_hdsp_get_autosync_sample_rate \
1841 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1843 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1844 static const char * const texts[] = {
1845 "32000", "44100", "48000", "64000", "88200", "96000",
1846 "None", "128000", "176400", "192000"
1849 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1853 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1857 switch (hdsp_external_sample_rate(hdsp)) {
1859 ucontrol->value.enumerated.item[0] = 0;
1862 ucontrol->value.enumerated.item[0] = 1;
1865 ucontrol->value.enumerated.item[0] = 2;
1868 ucontrol->value.enumerated.item[0] = 3;
1871 ucontrol->value.enumerated.item[0] = 4;
1874 ucontrol->value.enumerated.item[0] = 5;
1877 ucontrol->value.enumerated.item[0] = 7;
1880 ucontrol->value.enumerated.item[0] = 8;
1883 ucontrol->value.enumerated.item[0] = 9;
1886 ucontrol->value.enumerated.item[0] = 6;
1891 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1892 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1895 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1896 .info = snd_hdsp_info_system_clock_mode, \
1897 .get = snd_hdsp_get_system_clock_mode \
1900 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1902 if (hdsp->control_register & HDSP_ClockModeMaster)
1904 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1909 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1911 static const char * const texts[] = {"Master", "Slave" };
1913 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1916 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1918 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1920 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1924 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1925 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1928 .info = snd_hdsp_info_clock_source, \
1929 .get = snd_hdsp_get_clock_source, \
1930 .put = snd_hdsp_put_clock_source \
1933 static int hdsp_clock_source(struct hdsp *hdsp)
1935 if (hdsp->control_register & HDSP_ClockModeMaster) {
1936 switch (hdsp->system_sample_rate) {
1963 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1967 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1968 if (hdsp_external_sample_rate(hdsp) != 0) {
1969 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1970 hdsp->control_register &= ~HDSP_ClockModeMaster;
1971 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1976 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1979 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1982 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1985 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1988 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1991 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1994 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1997 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2000 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2006 hdsp->control_register |= HDSP_ClockModeMaster;
2007 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2008 hdsp_set_rate(hdsp, rate, 1);
2012 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2014 static const char * const texts[] = {
2015 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2016 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2017 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2018 "Internal 192.0 KHz"
2020 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2022 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2026 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2028 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2030 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2034 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2036 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2040 if (!snd_hdsp_use_is_exclusive(hdsp))
2042 val = ucontrol->value.enumerated.item[0];
2043 if (val < 0) val = 0;
2044 if (hdsp->io_type == H9632) {
2051 spin_lock_irq(&hdsp->lock);
2052 if (val != hdsp_clock_source(hdsp))
2053 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2056 spin_unlock_irq(&hdsp->lock);
2060 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2062 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2064 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2066 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2070 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2072 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2075 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2077 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2081 #define HDSP_DA_GAIN(xname, xindex) \
2082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2085 .info = snd_hdsp_info_da_gain, \
2086 .get = snd_hdsp_get_da_gain, \
2087 .put = snd_hdsp_put_da_gain \
2090 static int hdsp_da_gain(struct hdsp *hdsp)
2092 switch (hdsp->control_register & HDSP_DAGainMask) {
2093 case HDSP_DAGainHighGain:
2095 case HDSP_DAGainPlus4dBu:
2097 case HDSP_DAGainMinus10dBV:
2104 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2106 hdsp->control_register &= ~HDSP_DAGainMask;
2109 hdsp->control_register |= HDSP_DAGainHighGain;
2112 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2115 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2121 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2125 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2127 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2129 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2132 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2134 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2136 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2140 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2142 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2146 if (!snd_hdsp_use_is_exclusive(hdsp))
2148 val = ucontrol->value.enumerated.item[0];
2149 if (val < 0) val = 0;
2150 if (val > 2) val = 2;
2151 spin_lock_irq(&hdsp->lock);
2152 if (val != hdsp_da_gain(hdsp))
2153 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2156 spin_unlock_irq(&hdsp->lock);
2160 #define HDSP_AD_GAIN(xname, xindex) \
2161 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2164 .info = snd_hdsp_info_ad_gain, \
2165 .get = snd_hdsp_get_ad_gain, \
2166 .put = snd_hdsp_put_ad_gain \
2169 static int hdsp_ad_gain(struct hdsp *hdsp)
2171 switch (hdsp->control_register & HDSP_ADGainMask) {
2172 case HDSP_ADGainMinus10dBV:
2174 case HDSP_ADGainPlus4dBu:
2176 case HDSP_ADGainLowGain:
2183 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2185 hdsp->control_register &= ~HDSP_ADGainMask;
2188 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2191 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2194 hdsp->control_register |= HDSP_ADGainLowGain;
2200 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2204 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2206 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2208 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2211 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2213 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2215 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2219 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2221 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2225 if (!snd_hdsp_use_is_exclusive(hdsp))
2227 val = ucontrol->value.enumerated.item[0];
2228 if (val < 0) val = 0;
2229 if (val > 2) val = 2;
2230 spin_lock_irq(&hdsp->lock);
2231 if (val != hdsp_ad_gain(hdsp))
2232 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2235 spin_unlock_irq(&hdsp->lock);
2239 #define HDSP_PHONE_GAIN(xname, xindex) \
2240 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2243 .info = snd_hdsp_info_phone_gain, \
2244 .get = snd_hdsp_get_phone_gain, \
2245 .put = snd_hdsp_put_phone_gain \
2248 static int hdsp_phone_gain(struct hdsp *hdsp)
2250 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2251 case HDSP_PhoneGain0dB:
2253 case HDSP_PhoneGainMinus6dB:
2255 case HDSP_PhoneGainMinus12dB:
2262 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2264 hdsp->control_register &= ~HDSP_PhoneGainMask;
2267 hdsp->control_register |= HDSP_PhoneGain0dB;
2270 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2273 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2279 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2283 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2285 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2287 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2290 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2292 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2294 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2298 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2300 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2304 if (!snd_hdsp_use_is_exclusive(hdsp))
2306 val = ucontrol->value.enumerated.item[0];
2307 if (val < 0) val = 0;
2308 if (val > 2) val = 2;
2309 spin_lock_irq(&hdsp->lock);
2310 if (val != hdsp_phone_gain(hdsp))
2311 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2314 spin_unlock_irq(&hdsp->lock);
2318 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2322 .info = snd_hdsp_info_pref_sync_ref, \
2323 .get = snd_hdsp_get_pref_sync_ref, \
2324 .put = snd_hdsp_put_pref_sync_ref \
2327 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2329 /* Notice that this looks at the requested sync source,
2330 not the one actually in use.
2333 switch (hdsp->control_register & HDSP_SyncRefMask) {
2334 case HDSP_SyncRef_ADAT1:
2335 return HDSP_SYNC_FROM_ADAT1;
2336 case HDSP_SyncRef_ADAT2:
2337 return HDSP_SYNC_FROM_ADAT2;
2338 case HDSP_SyncRef_ADAT3:
2339 return HDSP_SYNC_FROM_ADAT3;
2340 case HDSP_SyncRef_SPDIF:
2341 return HDSP_SYNC_FROM_SPDIF;
2342 case HDSP_SyncRef_WORD:
2343 return HDSP_SYNC_FROM_WORD;
2344 case HDSP_SyncRef_ADAT_SYNC:
2345 return HDSP_SYNC_FROM_ADAT_SYNC;
2347 return HDSP_SYNC_FROM_WORD;
2352 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2354 hdsp->control_register &= ~HDSP_SyncRefMask;
2356 case HDSP_SYNC_FROM_ADAT1:
2357 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2359 case HDSP_SYNC_FROM_ADAT2:
2360 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2362 case HDSP_SYNC_FROM_ADAT3:
2363 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2365 case HDSP_SYNC_FROM_SPDIF:
2366 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2368 case HDSP_SYNC_FROM_WORD:
2369 hdsp->control_register |= HDSP_SyncRef_WORD;
2371 case HDSP_SYNC_FROM_ADAT_SYNC:
2372 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2377 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2381 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2383 static const char * const texts[] = {
2384 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2386 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2389 switch (hdsp->io_type) {
2404 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2407 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2409 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2411 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2415 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2417 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2421 if (!snd_hdsp_use_is_exclusive(hdsp))
2424 switch (hdsp->io_type) {
2439 val = ucontrol->value.enumerated.item[0] % max;
2440 spin_lock_irq(&hdsp->lock);
2441 change = (int)val != hdsp_pref_sync_ref(hdsp);
2442 hdsp_set_pref_sync_ref(hdsp, val);
2443 spin_unlock_irq(&hdsp->lock);
2447 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2448 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2451 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2452 .info = snd_hdsp_info_autosync_ref, \
2453 .get = snd_hdsp_get_autosync_ref, \
2456 static int hdsp_autosync_ref(struct hdsp *hdsp)
2458 /* This looks at the autosync selected sync reference */
2459 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2461 switch (status2 & HDSP_SelSyncRefMask) {
2462 case HDSP_SelSyncRef_WORD:
2463 return HDSP_AUTOSYNC_FROM_WORD;
2464 case HDSP_SelSyncRef_ADAT_SYNC:
2465 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2466 case HDSP_SelSyncRef_SPDIF:
2467 return HDSP_AUTOSYNC_FROM_SPDIF;
2468 case HDSP_SelSyncRefMask:
2469 return HDSP_AUTOSYNC_FROM_NONE;
2470 case HDSP_SelSyncRef_ADAT1:
2471 return HDSP_AUTOSYNC_FROM_ADAT1;
2472 case HDSP_SelSyncRef_ADAT2:
2473 return HDSP_AUTOSYNC_FROM_ADAT2;
2474 case HDSP_SelSyncRef_ADAT3:
2475 return HDSP_AUTOSYNC_FROM_ADAT3;
2477 return HDSP_AUTOSYNC_FROM_WORD;
2482 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2484 static const char * const texts[] = {
2485 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2488 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2491 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2493 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2495 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2499 #define HDSP_PRECISE_POINTER(xname, xindex) \
2500 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2503 .info = snd_hdsp_info_precise_pointer, \
2504 .get = snd_hdsp_get_precise_pointer, \
2505 .put = snd_hdsp_put_precise_pointer \
2508 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2511 hdsp->precise_ptr = 1;
2513 hdsp->precise_ptr = 0;
2517 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2519 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2521 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2523 spin_lock_irq(&hdsp->lock);
2524 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2525 spin_unlock_irq(&hdsp->lock);
2529 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2531 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2535 if (!snd_hdsp_use_is_exclusive(hdsp))
2537 val = ucontrol->value.integer.value[0] & 1;
2538 spin_lock_irq(&hdsp->lock);
2539 change = (int)val != hdsp->precise_ptr;
2540 hdsp_set_precise_pointer(hdsp, val);
2541 spin_unlock_irq(&hdsp->lock);
2545 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2546 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2549 .info = snd_hdsp_info_use_midi_tasklet, \
2550 .get = snd_hdsp_get_use_midi_tasklet, \
2551 .put = snd_hdsp_put_use_midi_tasklet \
2554 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2557 hdsp->use_midi_tasklet = 1;
2559 hdsp->use_midi_tasklet = 0;
2563 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2565 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2569 spin_lock_irq(&hdsp->lock);
2570 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2571 spin_unlock_irq(&hdsp->lock);
2575 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2581 if (!snd_hdsp_use_is_exclusive(hdsp))
2583 val = ucontrol->value.integer.value[0] & 1;
2584 spin_lock_irq(&hdsp->lock);
2585 change = (int)val != hdsp->use_midi_tasklet;
2586 hdsp_set_use_midi_tasklet(hdsp, val);
2587 spin_unlock_irq(&hdsp->lock);
2591 #define HDSP_MIXER(xname, xindex) \
2592 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2596 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2597 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2598 .info = snd_hdsp_info_mixer, \
2599 .get = snd_hdsp_get_mixer, \
2600 .put = snd_hdsp_put_mixer \
2603 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2605 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2607 uinfo->value.integer.min = 0;
2608 uinfo->value.integer.max = 65536;
2609 uinfo->value.integer.step = 1;
2613 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2615 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2620 source = ucontrol->value.integer.value[0];
2621 destination = ucontrol->value.integer.value[1];
2623 if (source >= hdsp->max_channels)
2624 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2626 addr = hdsp_input_to_output_key(hdsp,source, destination);
2628 spin_lock_irq(&hdsp->lock);
2629 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2630 spin_unlock_irq(&hdsp->lock);
2634 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2643 if (!snd_hdsp_use_is_exclusive(hdsp))
2646 source = ucontrol->value.integer.value[0];
2647 destination = ucontrol->value.integer.value[1];
2649 if (source >= hdsp->max_channels)
2650 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2652 addr = hdsp_input_to_output_key(hdsp,source, destination);
2654 gain = ucontrol->value.integer.value[2];
2656 spin_lock_irq(&hdsp->lock);
2657 change = gain != hdsp_read_gain(hdsp, addr);
2659 hdsp_write_gain(hdsp, addr, gain);
2660 spin_unlock_irq(&hdsp->lock);
2664 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2665 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2668 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2669 .info = snd_hdsp_info_sync_check, \
2670 .get = snd_hdsp_get_wc_sync_check \
2673 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2675 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2677 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2680 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2682 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2683 if (status2 & HDSP_wc_lock) {
2684 if (status2 & HDSP_wc_sync)
2693 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2697 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2701 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2702 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2705 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2706 .info = snd_hdsp_info_sync_check, \
2707 .get = snd_hdsp_get_spdif_sync_check \
2710 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2712 int status = hdsp_read(hdsp, HDSP_statusRegister);
2713 if (status & HDSP_SPDIFErrorFlag)
2716 if (status & HDSP_SPDIFSync)
2724 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2728 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2732 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2733 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2736 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737 .info = snd_hdsp_info_sync_check, \
2738 .get = snd_hdsp_get_adatsync_sync_check \
2741 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2743 int status = hdsp_read(hdsp, HDSP_statusRegister);
2744 if (status & HDSP_TimecodeLock) {
2745 if (status & HDSP_TimecodeSync)
2753 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2755 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2757 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2761 #define HDSP_ADAT_SYNC_CHECK \
2762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2763 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2764 .info = snd_hdsp_info_sync_check, \
2765 .get = snd_hdsp_get_adat_sync_check \
2768 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2770 int status = hdsp_read(hdsp, HDSP_statusRegister);
2772 if (status & (HDSP_Lock0>>idx)) {
2773 if (status & (HDSP_Sync0>>idx))
2781 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2784 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2786 offset = ucontrol->id.index - 1;
2787 if (snd_BUG_ON(offset < 0))
2790 switch (hdsp->io_type) {
2805 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2809 #define HDSP_DDS_OFFSET(xname, xindex) \
2810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2813 .info = snd_hdsp_info_dds_offset, \
2814 .get = snd_hdsp_get_dds_offset, \
2815 .put = snd_hdsp_put_dds_offset \
2818 static int hdsp_dds_offset(struct hdsp *hdsp)
2821 unsigned int dds_value = hdsp->dds_value;
2822 int system_sample_rate = hdsp->system_sample_rate;
2829 * dds_value = n / rate
2830 * rate = n / dds_value
2832 n = div_u64(n, dds_value);
2833 if (system_sample_rate >= 112000)
2835 else if (system_sample_rate >= 56000)
2837 return ((int)n) - system_sample_rate;
2840 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2842 int rate = hdsp->system_sample_rate + offset_hz;
2843 hdsp_set_dds_value(hdsp, rate);
2847 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2849 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2851 uinfo->value.integer.min = -5000;
2852 uinfo->value.integer.max = 5000;
2856 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2858 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2860 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2864 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2866 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2870 if (!snd_hdsp_use_is_exclusive(hdsp))
2872 val = ucontrol->value.integer.value[0];
2873 spin_lock_irq(&hdsp->lock);
2874 if (val != hdsp_dds_offset(hdsp))
2875 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2878 spin_unlock_irq(&hdsp->lock);
2882 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2883 HDSP_DA_GAIN("DA Gain", 0),
2884 HDSP_AD_GAIN("AD Gain", 0),
2885 HDSP_PHONE_GAIN("Phones Gain", 0),
2886 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2887 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2890 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2892 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2893 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2894 .info = snd_hdsp_control_spdif_info,
2895 .get = snd_hdsp_control_spdif_get,
2896 .put = snd_hdsp_control_spdif_put,
2899 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2900 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2901 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2902 .info = snd_hdsp_control_spdif_stream_info,
2903 .get = snd_hdsp_control_spdif_stream_get,
2904 .put = snd_hdsp_control_spdif_stream_put,
2907 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2908 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2909 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2910 .info = snd_hdsp_control_spdif_mask_info,
2911 .get = snd_hdsp_control_spdif_mask_get,
2912 .private_value = IEC958_AES0_NONAUDIO |
2913 IEC958_AES0_PROFESSIONAL |
2914 IEC958_AES0_CON_EMPHASIS,
2917 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2918 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2919 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2920 .info = snd_hdsp_control_spdif_mask_info,
2921 .get = snd_hdsp_control_spdif_mask_get,
2922 .private_value = IEC958_AES0_NONAUDIO |
2923 IEC958_AES0_PROFESSIONAL |
2924 IEC958_AES0_PRO_EMPHASIS,
2926 HDSP_MIXER("Mixer", 0),
2927 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2928 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2929 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2930 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2931 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2932 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2933 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2935 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2936 .name = "Sample Clock Source Locking",
2937 .info = snd_hdsp_info_clock_source_lock,
2938 .get = snd_hdsp_get_clock_source_lock,
2939 .put = snd_hdsp_put_clock_source_lock,
2941 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2942 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2943 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2944 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2945 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2946 /* 'External Rate' complies with the alsa control naming scheme */
2947 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2948 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2949 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2950 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2951 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2952 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2953 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2957 static int hdsp_rpm_input12(struct hdsp *hdsp)
2959 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2960 case HDSP_RPM_Inp12_Phon_6dB:
2962 case HDSP_RPM_Inp12_Phon_n6dB:
2964 case HDSP_RPM_Inp12_Line_0dB:
2966 case HDSP_RPM_Inp12_Line_n6dB:
2973 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2975 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2977 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2982 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2984 hdsp->control_register &= ~HDSP_RPM_Inp12;
2987 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2992 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2998 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3009 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3011 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3015 if (!snd_hdsp_use_is_exclusive(hdsp))
3017 val = ucontrol->value.enumerated.item[0];
3022 spin_lock_irq(&hdsp->lock);
3023 if (val != hdsp_rpm_input12(hdsp))
3024 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3027 spin_unlock_irq(&hdsp->lock);
3032 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3034 static const char * const texts[] = {
3035 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3038 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3042 static int hdsp_rpm_input34(struct hdsp *hdsp)
3044 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3045 case HDSP_RPM_Inp34_Phon_6dB:
3047 case HDSP_RPM_Inp34_Phon_n6dB:
3049 case HDSP_RPM_Inp34_Line_0dB:
3051 case HDSP_RPM_Inp34_Line_n6dB:
3058 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3060 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3062 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3067 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3069 hdsp->control_register &= ~HDSP_RPM_Inp34;
3072 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3077 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3083 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3089 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3094 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3096 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3100 if (!snd_hdsp_use_is_exclusive(hdsp))
3102 val = ucontrol->value.enumerated.item[0];
3107 spin_lock_irq(&hdsp->lock);
3108 if (val != hdsp_rpm_input34(hdsp))
3109 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3112 spin_unlock_irq(&hdsp->lock);
3117 /* RPM Bypass switch */
3118 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3120 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3124 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3126 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3128 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3133 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3136 hdsp->control_register |= HDSP_RPM_Bypass;
3138 hdsp->control_register &= ~HDSP_RPM_Bypass;
3139 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3144 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3146 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3150 if (!snd_hdsp_use_is_exclusive(hdsp))
3152 val = ucontrol->value.integer.value[0] & 1;
3153 spin_lock_irq(&hdsp->lock);
3154 change = (int)val != hdsp_rpm_bypass(hdsp);
3155 hdsp_set_rpm_bypass(hdsp, val);
3156 spin_unlock_irq(&hdsp->lock);
3161 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3163 static const char * const texts[] = {"On", "Off"};
3165 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3169 /* RPM Disconnect switch */
3170 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3172 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3176 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3178 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3180 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3185 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3188 hdsp->control_register |= HDSP_RPM_Disconnect;
3190 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3191 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3196 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3198 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3202 if (!snd_hdsp_use_is_exclusive(hdsp))
3204 val = ucontrol->value.integer.value[0] & 1;
3205 spin_lock_irq(&hdsp->lock);
3206 change = (int)val != hdsp_rpm_disconnect(hdsp);
3207 hdsp_set_rpm_disconnect(hdsp, val);
3208 spin_unlock_irq(&hdsp->lock);
3212 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3214 static const char * const texts[] = {"On", "Off"};
3216 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3219 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3221 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222 .name = "RPM Bypass",
3223 .get = snd_hdsp_get_rpm_bypass,
3224 .put = snd_hdsp_put_rpm_bypass,
3225 .info = snd_hdsp_info_rpm_bypass
3228 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229 .name = "RPM Disconnect",
3230 .get = snd_hdsp_get_rpm_disconnect,
3231 .put = snd_hdsp_put_rpm_disconnect,
3232 .info = snd_hdsp_info_rpm_disconnect
3235 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236 .name = "Input 1/2",
3237 .get = snd_hdsp_get_rpm_input12,
3238 .put = snd_hdsp_put_rpm_input12,
3239 .info = snd_hdsp_info_rpm_input
3242 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3243 .name = "Input 3/4",
3244 .get = snd_hdsp_get_rpm_input34,
3245 .put = snd_hdsp_put_rpm_input34,
3246 .info = snd_hdsp_info_rpm_input
3248 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3249 HDSP_MIXER("Mixer", 0)
3252 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3253 HDSP_TOGGLE_SETTING("Analog Extension Board",
3254 HDSP_AnalogExtensionBoard);
3255 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3257 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3261 struct snd_kcontrol *kctl;
3263 if (hdsp->io_type == RPM) {
3264 /* RPM Bypass, Disconnect and Input switches */
3265 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3266 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3273 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3274 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3276 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3277 hdsp->spdif_ctl = kctl;
3280 /* ADAT SyncCheck status */
3281 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3282 snd_hdsp_adat_sync_check.index = 1;
3283 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3285 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3286 for (idx = 1; idx < 3; ++idx) {
3287 snd_hdsp_adat_sync_check.index = idx+1;
3288 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3293 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3294 if (hdsp->io_type == H9632) {
3295 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3296 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3301 /* AEB control for H96xx card */
3302 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3303 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3310 /*------------------------------------------------------------
3312 ------------------------------------------------------------*/
3315 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3317 struct hdsp *hdsp = entry->private_data;
3318 unsigned int status;
3319 unsigned int status2;
3320 char *pref_sync_ref;
3322 char *system_clock_mode;
3326 status = hdsp_read(hdsp, HDSP_statusRegister);
3327 status2 = hdsp_read(hdsp, HDSP_status2Register);
3329 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3330 hdsp->card->number + 1);
3331 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3332 hdsp->capture_buffer, hdsp->playback_buffer);
3333 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3334 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3335 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3336 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3337 hdsp->control2_register);
3338 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3339 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3341 if (hdsp_check_for_iobox(hdsp)) {
3342 snd_iprintf(buffer, "No I/O box connected.\n"
3343 "Please connect one and upload firmware.\n");
3347 if (hdsp_check_for_firmware(hdsp, 0)) {
3348 if (hdsp->state & HDSP_FirmwareCached) {
3349 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3350 snd_iprintf(buffer, "Firmware loading from "
3352 "please upload manually.\n");
3357 err = hdsp_request_fw_loader(hdsp);
3360 "No firmware loaded nor cached, "
3361 "please upload firmware.\n");
3367 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3368 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3369 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3370 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3371 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3372 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3374 snd_iprintf(buffer, "\n");
3376 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3378 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3379 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3380 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3381 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3383 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3385 snd_iprintf(buffer, "\n");
3387 switch (hdsp_clock_source(hdsp)) {
3388 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3389 clock_source = "AutoSync";
3391 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3392 clock_source = "Internal 32 kHz";
3394 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3395 clock_source = "Internal 44.1 kHz";
3397 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3398 clock_source = "Internal 48 kHz";
3400 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3401 clock_source = "Internal 64 kHz";
3403 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3404 clock_source = "Internal 88.2 kHz";
3406 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3407 clock_source = "Internal 96 kHz";
3409 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3410 clock_source = "Internal 128 kHz";
3412 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3413 clock_source = "Internal 176.4 kHz";
3415 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3416 clock_source = "Internal 192 kHz";
3419 clock_source = "Error";
3421 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3423 if (hdsp_system_clock_mode(hdsp))
3424 system_clock_mode = "Slave";
3426 system_clock_mode = "Master";
3428 switch (hdsp_pref_sync_ref (hdsp)) {
3429 case HDSP_SYNC_FROM_WORD:
3430 pref_sync_ref = "Word Clock";
3432 case HDSP_SYNC_FROM_ADAT_SYNC:
3433 pref_sync_ref = "ADAT Sync";
3435 case HDSP_SYNC_FROM_SPDIF:
3436 pref_sync_ref = "SPDIF";
3438 case HDSP_SYNC_FROM_ADAT1:
3439 pref_sync_ref = "ADAT1";
3441 case HDSP_SYNC_FROM_ADAT2:
3442 pref_sync_ref = "ADAT2";
3444 case HDSP_SYNC_FROM_ADAT3:
3445 pref_sync_ref = "ADAT3";
3448 pref_sync_ref = "Word Clock";
3451 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3453 switch (hdsp_autosync_ref (hdsp)) {
3454 case HDSP_AUTOSYNC_FROM_WORD:
3455 autosync_ref = "Word Clock";
3457 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3458 autosync_ref = "ADAT Sync";
3460 case HDSP_AUTOSYNC_FROM_SPDIF:
3461 autosync_ref = "SPDIF";
3463 case HDSP_AUTOSYNC_FROM_NONE:
3464 autosync_ref = "None";
3466 case HDSP_AUTOSYNC_FROM_ADAT1:
3467 autosync_ref = "ADAT1";
3469 case HDSP_AUTOSYNC_FROM_ADAT2:
3470 autosync_ref = "ADAT2";
3472 case HDSP_AUTOSYNC_FROM_ADAT3:
3473 autosync_ref = "ADAT3";
3476 autosync_ref = "---";
3479 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3481 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3483 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3485 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3486 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3488 snd_iprintf(buffer, "\n");
3490 if (hdsp->io_type != RPM) {
3491 switch (hdsp_spdif_in(hdsp)) {
3492 case HDSP_SPDIFIN_OPTICAL:
3493 snd_iprintf(buffer, "IEC958 input: Optical\n");
3495 case HDSP_SPDIFIN_COAXIAL:
3496 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3498 case HDSP_SPDIFIN_INTERNAL:
3499 snd_iprintf(buffer, "IEC958 input: Internal\n");
3501 case HDSP_SPDIFIN_AES:
3502 snd_iprintf(buffer, "IEC958 input: AES\n");
3505 snd_iprintf(buffer, "IEC958 input: ???\n");
3510 if (RPM == hdsp->io_type) {
3511 if (hdsp->control_register & HDSP_RPM_Bypass)
3512 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3514 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3515 if (hdsp->control_register & HDSP_RPM_Disconnect)
3516 snd_iprintf(buffer, "RPM disconnected\n");
3518 snd_iprintf(buffer, "RPM connected\n");
3520 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3521 case HDSP_RPM_Inp12_Phon_6dB:
3522 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3524 case HDSP_RPM_Inp12_Phon_0dB:
3525 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3527 case HDSP_RPM_Inp12_Phon_n6dB:
3528 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3530 case HDSP_RPM_Inp12_Line_0dB:
3531 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3533 case HDSP_RPM_Inp12_Line_n6dB:
3534 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3537 snd_iprintf(buffer, "Input 1/2: ???\n");
3540 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3541 case HDSP_RPM_Inp34_Phon_6dB:
3542 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3544 case HDSP_RPM_Inp34_Phon_0dB:
3545 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3547 case HDSP_RPM_Inp34_Phon_n6dB:
3548 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3550 case HDSP_RPM_Inp34_Line_0dB:
3551 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3553 case HDSP_RPM_Inp34_Line_n6dB:
3554 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3557 snd_iprintf(buffer, "Input 3/4: ???\n");
3561 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3562 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3564 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3566 if (hdsp->control_register & HDSP_SPDIFProfessional)
3567 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3569 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3571 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3572 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3574 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3576 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3577 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3579 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3580 x = hdsp_spdif_sample_rate(hdsp);
3582 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3584 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3586 snd_iprintf(buffer, "\n");
3589 x = status & HDSP_Sync0;
3590 if (status & HDSP_Lock0)
3591 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3593 snd_iprintf(buffer, "ADAT1: No Lock\n");
3595 switch (hdsp->io_type) {
3598 x = status & HDSP_Sync1;
3599 if (status & HDSP_Lock1)
3600 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3602 snd_iprintf(buffer, "ADAT2: No Lock\n");
3603 x = status & HDSP_Sync2;
3604 if (status & HDSP_Lock2)
3605 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3607 snd_iprintf(buffer, "ADAT3: No Lock\n");
3614 x = status & HDSP_SPDIFSync;
3615 if (status & HDSP_SPDIFErrorFlag)
3616 snd_iprintf (buffer, "SPDIF: No Lock\n");
3618 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3620 x = status2 & HDSP_wc_sync;
3621 if (status2 & HDSP_wc_lock)
3622 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3624 snd_iprintf (buffer, "Word Clock: No Lock\n");
3626 x = status & HDSP_TimecodeSync;
3627 if (status & HDSP_TimecodeLock)
3628 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3630 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3632 snd_iprintf(buffer, "\n");
3634 /* Informations about H9632 specific controls */
3635 if (hdsp->io_type == H9632) {
3638 switch (hdsp_ad_gain(hdsp)) {
3649 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3651 switch (hdsp_da_gain(hdsp)) {
3662 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3664 switch (hdsp_phone_gain(hdsp)) {
3675 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3677 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3678 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3681 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3682 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3684 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3685 snd_iprintf(buffer, "\n");
3690 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3692 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3695 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3697 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3698 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3701 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3703 unsigned long pb_bus, cb_bus;
3705 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3706 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3707 if (hdsp->capture_dma_buf.area)
3708 snd_dma_free_pages(&hdsp->capture_dma_buf);
3709 dev_err(hdsp->card->dev,
3710 "%s: no buffers available\n", hdsp->card_name);
3714 /* Align to bus-space 64K boundary */
3716 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3717 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3719 /* Tell the card where it is */
3721 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3722 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3724 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3725 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3730 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3734 /* ASSUMPTION: hdsp->lock is either held, or
3735 there is no need to hold it (e.g. during module
3741 SPDIF Input via Coax
3743 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3744 which implies 2 4096 sample, 32Kbyte periods).
3748 hdsp->control_register = HDSP_ClockModeMaster |
3749 HDSP_SPDIFInputCoaxial |
3750 hdsp_encode_latency(7) |
3754 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3756 #ifdef SNDRV_BIG_ENDIAN
3757 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3759 hdsp->control2_register = 0;
3761 if (hdsp->io_type == H9652)
3762 snd_hdsp_9652_enable_mixer (hdsp);
3764 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3766 hdsp_reset_hw_pointer(hdsp);
3767 hdsp_compute_period_size(hdsp);
3769 /* silence everything */
3771 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3772 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3774 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3775 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3779 /* H9632 specific defaults */
3780 if (hdsp->io_type == H9632) {
3781 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3782 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3785 /* set a default rate so that the channel map is set up.
3788 hdsp_set_rate(hdsp, 48000, 1);
3793 static void hdsp_midi_tasklet(unsigned long arg)
3795 struct hdsp *hdsp = (struct hdsp *)arg;
3797 if (hdsp->midi[0].pending)
3798 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3799 if (hdsp->midi[1].pending)
3800 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3803 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3805 struct hdsp *hdsp = (struct hdsp *) dev_id;
3806 unsigned int status;
3810 unsigned int midi0status;
3811 unsigned int midi1status;
3814 status = hdsp_read(hdsp, HDSP_statusRegister);
3816 audio = status & HDSP_audioIRQPending;
3817 midi0 = status & HDSP_midi0IRQPending;
3818 midi1 = status & HDSP_midi1IRQPending;
3820 if (!audio && !midi0 && !midi1)
3823 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3825 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3826 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3828 if (!(hdsp->state & HDSP_InitializationComplete))
3832 if (hdsp->capture_substream)
3833 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3835 if (hdsp->playback_substream)
3836 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3839 if (midi0 && midi0status) {
3840 if (hdsp->use_midi_tasklet) {
3841 /* we disable interrupts for this input until processing is done */
3842 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3843 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3844 hdsp->midi[0].pending = 1;
3847 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3850 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3851 if (hdsp->use_midi_tasklet) {
3852 /* we disable interrupts for this input until processing is done */
3853 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3854 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3855 hdsp->midi[1].pending = 1;
3858 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3861 if (hdsp->use_midi_tasklet && schedule)
3862 tasklet_schedule(&hdsp->midi_tasklet);
3866 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3868 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3869 return hdsp_hw_pointer(hdsp);
3872 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3879 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3882 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3885 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3886 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3888 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3891 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3892 int channel, unsigned long pos,
3893 void __user *src, unsigned long count)
3895 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3898 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3901 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3902 if (snd_BUG_ON(!channel_buf))
3904 if (copy_from_user(channel_buf + pos, src, count))
3909 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3910 int channel, unsigned long pos,
3911 void *src, unsigned long count)
3913 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3916 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3917 if (snd_BUG_ON(!channel_buf))
3919 memcpy(channel_buf + pos, src, count);
3923 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3924 int channel, unsigned long pos,
3925 void __user *dst, unsigned long count)
3927 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3930 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3933 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3934 if (snd_BUG_ON(!channel_buf))
3936 if (copy_to_user(dst, channel_buf + pos, count))
3941 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3942 int channel, unsigned long pos,
3943 void *dst, unsigned long count)
3945 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3948 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3949 if (snd_BUG_ON(!channel_buf))
3951 memcpy(dst, channel_buf + pos, count);
3955 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3956 int channel, unsigned long pos,
3957 unsigned long count)
3959 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3962 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3963 if (snd_BUG_ON(!channel_buf))
3965 memset(channel_buf + pos, 0, count);
3969 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3971 struct snd_pcm_runtime *runtime = substream->runtime;
3972 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3973 struct snd_pcm_substream *other;
3974 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3975 other = hdsp->capture_substream;
3977 other = hdsp->playback_substream;
3979 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3981 runtime->status->hw_ptr = 0;
3983 struct snd_pcm_substream *s;
3984 struct snd_pcm_runtime *oruntime = other->runtime;
3985 snd_pcm_group_for_each_entry(s, substream) {
3987 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3995 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3996 struct snd_pcm_hw_params *params)
3998 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4003 if (hdsp_check_for_iobox (hdsp))
4006 if (hdsp_check_for_firmware(hdsp, 1))
4009 spin_lock_irq(&hdsp->lock);
4011 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4012 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4013 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4014 this_pid = hdsp->playback_pid;
4015 other_pid = hdsp->capture_pid;
4017 this_pid = hdsp->capture_pid;
4018 other_pid = hdsp->playback_pid;
4021 if ((other_pid > 0) && (this_pid != other_pid)) {
4023 /* The other stream is open, and not by the same
4024 task as this one. Make sure that the parameters
4025 that matter are the same.
4028 if (params_rate(params) != hdsp->system_sample_rate) {
4029 spin_unlock_irq(&hdsp->lock);
4030 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4034 if (params_period_size(params) != hdsp->period_bytes / 4) {
4035 spin_unlock_irq(&hdsp->lock);
4036 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4042 spin_unlock_irq(&hdsp->lock);
4046 spin_unlock_irq(&hdsp->lock);
4049 /* how to make sure that the rate matches an externally-set one ?
4052 spin_lock_irq(&hdsp->lock);
4053 if (! hdsp->clock_source_locked) {
4054 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4055 spin_unlock_irq(&hdsp->lock);
4056 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4060 spin_unlock_irq(&hdsp->lock);
4062 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4063 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4070 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4071 struct snd_pcm_channel_info *info)
4073 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4074 unsigned int channel = info->channel;
4076 if (snd_BUG_ON(channel >= hdsp->max_channels))
4078 channel = array_index_nospec(channel, hdsp->max_channels);
4080 if (hdsp->channel_map[channel] < 0)
4083 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4089 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4090 unsigned int cmd, void *arg)
4093 case SNDRV_PCM_IOCTL1_RESET:
4094 return snd_hdsp_reset(substream);
4095 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4096 return snd_hdsp_channel_info(substream, arg);
4101 return snd_pcm_lib_ioctl(substream, cmd, arg);
4104 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4106 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4107 struct snd_pcm_substream *other;
4110 if (hdsp_check_for_iobox (hdsp))
4113 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4116 spin_lock(&hdsp->lock);
4117 running = hdsp->running;
4119 case SNDRV_PCM_TRIGGER_START:
4120 running |= 1 << substream->stream;
4122 case SNDRV_PCM_TRIGGER_STOP:
4123 running &= ~(1 << substream->stream);
4127 spin_unlock(&hdsp->lock);
4130 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4131 other = hdsp->capture_substream;
4133 other = hdsp->playback_substream;
4136 struct snd_pcm_substream *s;
4137 snd_pcm_group_for_each_entry(s, substream) {
4139 snd_pcm_trigger_done(s, substream);
4140 if (cmd == SNDRV_PCM_TRIGGER_START)
4141 running |= 1 << s->stream;
4143 running &= ~(1 << s->stream);
4147 if (cmd == SNDRV_PCM_TRIGGER_START) {
4148 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4149 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4150 hdsp_silence_playback(hdsp);
4153 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4154 hdsp_silence_playback(hdsp);
4157 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4158 hdsp_silence_playback(hdsp);
4161 snd_pcm_trigger_done(substream, substream);
4162 if (!hdsp->running && running)
4163 hdsp_start_audio(hdsp);
4164 else if (hdsp->running && !running)
4165 hdsp_stop_audio(hdsp);
4166 hdsp->running = running;
4167 spin_unlock(&hdsp->lock);
4172 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4174 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4177 if (hdsp_check_for_iobox (hdsp))
4180 if (hdsp_check_for_firmware(hdsp, 1))
4183 spin_lock_irq(&hdsp->lock);
4185 hdsp_reset_hw_pointer(hdsp);
4186 spin_unlock_irq(&hdsp->lock);
4190 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4192 .info = (SNDRV_PCM_INFO_MMAP |
4193 SNDRV_PCM_INFO_MMAP_VALID |
4194 SNDRV_PCM_INFO_NONINTERLEAVED |
4195 SNDRV_PCM_INFO_SYNC_START |
4196 SNDRV_PCM_INFO_DOUBLE),
4197 #ifdef SNDRV_BIG_ENDIAN
4198 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4200 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4202 .rates = (SNDRV_PCM_RATE_32000 |
4203 SNDRV_PCM_RATE_44100 |
4204 SNDRV_PCM_RATE_48000 |
4205 SNDRV_PCM_RATE_64000 |
4206 SNDRV_PCM_RATE_88200 |
4207 SNDRV_PCM_RATE_96000),
4211 .channels_max = HDSP_MAX_CHANNELS,
4212 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4213 .period_bytes_min = (64 * 4) * 10,
4214 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4220 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4222 .info = (SNDRV_PCM_INFO_MMAP |
4223 SNDRV_PCM_INFO_MMAP_VALID |
4224 SNDRV_PCM_INFO_NONINTERLEAVED |
4225 SNDRV_PCM_INFO_SYNC_START),
4226 #ifdef SNDRV_BIG_ENDIAN
4227 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4229 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4231 .rates = (SNDRV_PCM_RATE_32000 |
4232 SNDRV_PCM_RATE_44100 |
4233 SNDRV_PCM_RATE_48000 |
4234 SNDRV_PCM_RATE_64000 |
4235 SNDRV_PCM_RATE_88200 |
4236 SNDRV_PCM_RATE_96000),
4240 .channels_max = HDSP_MAX_CHANNELS,
4241 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4242 .period_bytes_min = (64 * 4) * 10,
4243 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4249 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4251 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4252 .count = ARRAY_SIZE(hdsp_period_sizes),
4253 .list = hdsp_period_sizes,
4257 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4259 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4260 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4261 .list = hdsp_9632_sample_rates,
4265 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4266 struct snd_pcm_hw_rule *rule)
4268 struct hdsp *hdsp = rule->private;
4269 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4270 if (hdsp->io_type == H9632) {
4271 unsigned int list[3];
4272 list[0] = hdsp->qs_in_channels;
4273 list[1] = hdsp->ds_in_channels;
4274 list[2] = hdsp->ss_in_channels;
4275 return snd_interval_list(c, 3, list, 0);
4277 unsigned int list[2];
4278 list[0] = hdsp->ds_in_channels;
4279 list[1] = hdsp->ss_in_channels;
4280 return snd_interval_list(c, 2, list, 0);
4284 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4285 struct snd_pcm_hw_rule *rule)
4287 unsigned int list[3];
4288 struct hdsp *hdsp = rule->private;
4289 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4290 if (hdsp->io_type == H9632) {
4291 list[0] = hdsp->qs_out_channels;
4292 list[1] = hdsp->ds_out_channels;
4293 list[2] = hdsp->ss_out_channels;
4294 return snd_interval_list(c, 3, list, 0);
4296 list[0] = hdsp->ds_out_channels;
4297 list[1] = hdsp->ss_out_channels;
4299 return snd_interval_list(c, 2, list, 0);
4302 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4303 struct snd_pcm_hw_rule *rule)
4305 struct hdsp *hdsp = rule->private;
4306 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4307 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4308 if (r->min > 96000 && hdsp->io_type == H9632) {
4309 struct snd_interval t = {
4310 .min = hdsp->qs_in_channels,
4311 .max = hdsp->qs_in_channels,
4314 return snd_interval_refine(c, &t);
4315 } else if (r->min > 48000 && r->max <= 96000) {
4316 struct snd_interval t = {
4317 .min = hdsp->ds_in_channels,
4318 .max = hdsp->ds_in_channels,
4321 return snd_interval_refine(c, &t);
4322 } else if (r->max < 64000) {
4323 struct snd_interval t = {
4324 .min = hdsp->ss_in_channels,
4325 .max = hdsp->ss_in_channels,
4328 return snd_interval_refine(c, &t);
4333 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4334 struct snd_pcm_hw_rule *rule)
4336 struct hdsp *hdsp = rule->private;
4337 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4338 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4339 if (r->min > 96000 && hdsp->io_type == H9632) {
4340 struct snd_interval t = {
4341 .min = hdsp->qs_out_channels,
4342 .max = hdsp->qs_out_channels,
4345 return snd_interval_refine(c, &t);
4346 } else if (r->min > 48000 && r->max <= 96000) {
4347 struct snd_interval t = {
4348 .min = hdsp->ds_out_channels,
4349 .max = hdsp->ds_out_channels,
4352 return snd_interval_refine(c, &t);
4353 } else if (r->max < 64000) {
4354 struct snd_interval t = {
4355 .min = hdsp->ss_out_channels,
4356 .max = hdsp->ss_out_channels,
4359 return snd_interval_refine(c, &t);
4364 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4365 struct snd_pcm_hw_rule *rule)
4367 struct hdsp *hdsp = rule->private;
4368 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4369 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4370 if (c->min >= hdsp->ss_out_channels) {
4371 struct snd_interval t = {
4376 return snd_interval_refine(r, &t);
4377 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4378 struct snd_interval t = {
4383 return snd_interval_refine(r, &t);
4384 } else if (c->max <= hdsp->ds_out_channels) {
4385 struct snd_interval t = {
4390 return snd_interval_refine(r, &t);
4395 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4396 struct snd_pcm_hw_rule *rule)
4398 struct hdsp *hdsp = rule->private;
4399 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4400 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4401 if (c->min >= hdsp->ss_in_channels) {
4402 struct snd_interval t = {
4407 return snd_interval_refine(r, &t);
4408 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4409 struct snd_interval t = {
4414 return snd_interval_refine(r, &t);
4415 } else if (c->max <= hdsp->ds_in_channels) {
4416 struct snd_interval t = {
4421 return snd_interval_refine(r, &t);
4426 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4428 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4429 struct snd_pcm_runtime *runtime = substream->runtime;
4431 if (hdsp_check_for_iobox (hdsp))
4434 if (hdsp_check_for_firmware(hdsp, 1))
4437 spin_lock_irq(&hdsp->lock);
4439 snd_pcm_set_sync(substream);
4441 runtime->hw = snd_hdsp_playback_subinfo;
4442 runtime->dma_area = hdsp->playback_buffer;
4443 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4445 hdsp->playback_pid = current->pid;
4446 hdsp->playback_substream = substream;
4448 spin_unlock_irq(&hdsp->lock);
4450 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4451 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4452 if (hdsp->clock_source_locked) {
4453 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4454 } else if (hdsp->io_type == H9632) {
4455 runtime->hw.rate_max = 192000;
4456 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4457 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4459 if (hdsp->io_type == H9632) {
4460 runtime->hw.channels_min = hdsp->qs_out_channels;
4461 runtime->hw.channels_max = hdsp->ss_out_channels;
4464 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4465 snd_hdsp_hw_rule_out_channels, hdsp,
4466 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4467 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4468 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4469 SNDRV_PCM_HW_PARAM_RATE, -1);
4470 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4471 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4472 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4474 if (RPM != hdsp->io_type) {
4475 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4476 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4477 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4478 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4483 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4485 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4487 spin_lock_irq(&hdsp->lock);
4489 hdsp->playback_pid = -1;
4490 hdsp->playback_substream = NULL;
4492 spin_unlock_irq(&hdsp->lock);
4494 if (RPM != hdsp->io_type) {
4495 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4496 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4497 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4503 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4505 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4506 struct snd_pcm_runtime *runtime = substream->runtime;
4508 if (hdsp_check_for_iobox (hdsp))
4511 if (hdsp_check_for_firmware(hdsp, 1))
4514 spin_lock_irq(&hdsp->lock);
4516 snd_pcm_set_sync(substream);
4518 runtime->hw = snd_hdsp_capture_subinfo;
4519 runtime->dma_area = hdsp->capture_buffer;
4520 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4522 hdsp->capture_pid = current->pid;
4523 hdsp->capture_substream = substream;
4525 spin_unlock_irq(&hdsp->lock);
4527 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4528 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4529 if (hdsp->io_type == H9632) {
4530 runtime->hw.channels_min = hdsp->qs_in_channels;
4531 runtime->hw.channels_max = hdsp->ss_in_channels;
4532 runtime->hw.rate_max = 192000;
4533 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4534 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4536 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4537 snd_hdsp_hw_rule_in_channels, hdsp,
4538 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4539 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4540 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4541 SNDRV_PCM_HW_PARAM_RATE, -1);
4542 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4543 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4544 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4548 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4550 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4552 spin_lock_irq(&hdsp->lock);
4554 hdsp->capture_pid = -1;
4555 hdsp->capture_substream = NULL;
4557 spin_unlock_irq(&hdsp->lock);
4561 /* helper functions for copying meter values */
4562 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4564 u32 val = readl(src);
4565 return copy_to_user(dest, &val, 4);
4568 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4570 u32 rms_low, rms_high;
4572 rms_low = readl(src_low);
4573 rms_high = readl(src_high);
4574 rms = ((u64)rms_high << 32) | rms_low;
4575 return copy_to_user(dest, &rms, 8);
4578 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4580 u32 rms_low, rms_high;
4582 rms_low = readl(src_low) & 0xffffff00;
4583 rms_high = readl(src_high) & 0xffffff00;
4584 rms = ((u64)rms_high << 32) | rms_low;
4585 return copy_to_user(dest, &rms, 8);
4588 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4590 int doublespeed = 0;
4591 int i, j, channels, ofs;
4593 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4595 channels = doublespeed ? 14 : 26;
4596 for (i = 0, j = 0; i < 26; ++i) {
4597 if (doublespeed && (i & 4))
4599 ofs = HDSP_9652_peakBase - j * 4;
4600 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4602 ofs -= channels * 4;
4603 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4605 ofs -= channels * 4;
4606 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4608 ofs = HDSP_9652_rmsBase + j * 8;
4609 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4610 hdsp->iobase + ofs + 4))
4612 ofs += channels * 8;
4613 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4614 hdsp->iobase + ofs + 4))
4616 ofs += channels * 8;
4617 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4618 hdsp->iobase + ofs + 4))
4625 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4628 struct hdsp_9632_meters __iomem *m;
4629 int doublespeed = 0;
4631 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4633 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4634 for (i = 0, j = 0; i < 16; ++i, ++j) {
4635 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4637 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4639 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4641 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4642 &m->input_rms_high[j]))
4644 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4645 &m->playback_rms_high[j]))
4647 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4648 &m->output_rms_high[j]))
4650 if (doublespeed && i == 3) i += 4;
4655 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4659 for (i = 0; i < 26; i++) {
4660 if (copy_u32_le(&peak_rms->playback_peaks[i],
4661 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4663 if (copy_u32_le(&peak_rms->input_peaks[i],
4664 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4667 for (i = 0; i < 28; i++) {
4668 if (copy_u32_le(&peak_rms->output_peaks[i],
4669 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4672 for (i = 0; i < 26; ++i) {
4673 if (copy_u64_le(&peak_rms->playback_rms[i],
4674 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4675 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4677 if (copy_u64_le(&peak_rms->input_rms[i],
4678 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4679 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4685 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4687 struct hdsp *hdsp = hw->private_data;
4688 void __user *argp = (void __user *)arg;
4692 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4693 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4695 err = hdsp_check_for_iobox(hdsp);
4699 err = hdsp_check_for_firmware(hdsp, 1);
4703 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4704 dev_err(hdsp->card->dev,
4705 "firmware needs to be uploaded to the card.\n");
4709 switch (hdsp->io_type) {
4711 return hdsp_9652_get_peak(hdsp, peak_rms);
4713 return hdsp_9632_get_peak(hdsp, peak_rms);
4715 return hdsp_get_peak(hdsp, peak_rms);
4718 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4719 struct hdsp_config_info info;
4720 unsigned long flags;
4723 err = hdsp_check_for_iobox(hdsp);
4727 err = hdsp_check_for_firmware(hdsp, 1);
4731 memset(&info, 0, sizeof(info));
4732 spin_lock_irqsave(&hdsp->lock, flags);
4733 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4734 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4735 if (hdsp->io_type != H9632)
4736 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4737 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4738 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4739 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4740 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4741 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4742 HDSP_SPDIFOpticalOut);
4743 info.spdif_professional = (unsigned char)
4744 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4745 info.spdif_emphasis = (unsigned char)
4746 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4747 info.spdif_nonaudio = (unsigned char)
4748 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4749 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4750 info.system_sample_rate = hdsp->system_sample_rate;
4751 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4752 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4753 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4754 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4755 info.line_out = (unsigned char)
4756 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4757 if (hdsp->io_type == H9632) {
4758 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4759 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4760 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4761 info.xlr_breakout_cable =
4762 (unsigned char)hdsp_toggle_setting(hdsp,
4763 HDSP_XLRBreakoutCable);
4765 } else if (hdsp->io_type == RPM) {
4766 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4767 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4769 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4770 info.analog_extension_board =
4771 (unsigned char)hdsp_toggle_setting(hdsp,
4772 HDSP_AnalogExtensionBoard);
4773 spin_unlock_irqrestore(&hdsp->lock, flags);
4774 if (copy_to_user(argp, &info, sizeof(info)))
4778 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4779 struct hdsp_9632_aeb h9632_aeb;
4781 if (hdsp->io_type != H9632) return -EINVAL;
4782 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4783 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4784 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4788 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4789 struct hdsp_version hdsp_version;
4792 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4793 if (hdsp->io_type == Undefined) {
4794 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4797 memset(&hdsp_version, 0, sizeof(hdsp_version));
4798 hdsp_version.io_type = hdsp->io_type;
4799 hdsp_version.firmware_rev = hdsp->firmware_rev;
4800 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4804 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4805 struct hdsp_firmware __user *firmware;
4806 u32 __user *firmware_data;
4809 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4810 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4811 if (hdsp->io_type == Undefined) return -EINVAL;
4813 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4816 dev_info(hdsp->card->dev,
4817 "initializing firmware upload\n");
4818 firmware = (struct hdsp_firmware __user *)argp;
4820 if (get_user(firmware_data, (__force void __user **)&firmware->firmware_data))
4823 if (hdsp_check_for_iobox (hdsp))
4826 if (!hdsp->fw_uploaded) {
4827 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4828 if (!hdsp->fw_uploaded)
4832 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4833 HDSP_FIRMWARE_SIZE)) {
4834 vfree(hdsp->fw_uploaded);
4835 hdsp->fw_uploaded = NULL;
4839 hdsp->state |= HDSP_FirmwareCached;
4841 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4844 if (!(hdsp->state & HDSP_InitializationComplete)) {
4845 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4848 snd_hdsp_initialize_channels(hdsp);
4849 snd_hdsp_initialize_midi_flush(hdsp);
4851 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4852 dev_err(hdsp->card->dev,
4853 "error creating alsa devices\n");
4859 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4860 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4861 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4871 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4872 .open = snd_hdsp_playback_open,
4873 .close = snd_hdsp_playback_release,
4874 .ioctl = snd_hdsp_ioctl,
4875 .hw_params = snd_hdsp_hw_params,
4876 .prepare = snd_hdsp_prepare,
4877 .trigger = snd_hdsp_trigger,
4878 .pointer = snd_hdsp_hw_pointer,
4879 .copy_user = snd_hdsp_playback_copy,
4880 .copy_kernel = snd_hdsp_playback_copy_kernel,
4881 .fill_silence = snd_hdsp_hw_silence,
4884 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4885 .open = snd_hdsp_capture_open,
4886 .close = snd_hdsp_capture_release,
4887 .ioctl = snd_hdsp_ioctl,
4888 .hw_params = snd_hdsp_hw_params,
4889 .prepare = snd_hdsp_prepare,
4890 .trigger = snd_hdsp_trigger,
4891 .pointer = snd_hdsp_hw_pointer,
4892 .copy_user = snd_hdsp_capture_copy,
4893 .copy_kernel = snd_hdsp_capture_copy_kernel,
4896 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4898 struct snd_hwdep *hw;
4901 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4905 hw->private_data = hdsp;
4906 strcpy(hw->name, "HDSP hwdep interface");
4908 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4909 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4914 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4916 struct snd_pcm *pcm;
4919 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4923 pcm->private_data = hdsp;
4924 strcpy(pcm->name, hdsp->card_name);
4926 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4927 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4929 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4934 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4936 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4937 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4940 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4944 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4945 dev_err(hdsp->card->dev,
4946 "enable_io fifo_wait failed\n");
4950 for (i = 0; i < hdsp->max_channels; ++i) {
4951 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4952 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4958 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4960 int status, aebi_channels, aebo_channels;
4962 switch (hdsp->io_type) {
4964 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4965 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4966 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4970 hdsp->card_name = "RME Hammerfall HDSP 9652";
4971 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4972 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4976 status = hdsp_read(hdsp, HDSP_statusRegister);
4977 /* HDSP_AEBx bits are low when AEB are connected */
4978 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4979 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4980 hdsp->card_name = "RME Hammerfall HDSP 9632";
4981 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4982 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4983 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4984 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4985 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4986 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4990 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4991 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4992 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4996 hdsp->card_name = "RME Hammerfall DSP + RPM";
4997 hdsp->ss_in_channels = RPM_CHANNELS-1;
4998 hdsp->ss_out_channels = RPM_CHANNELS;
4999 hdsp->ds_in_channels = RPM_CHANNELS-1;
5000 hdsp->ds_out_channels = RPM_CHANNELS;
5004 /* should never get here */
5009 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5011 snd_hdsp_flush_midi_input (hdsp, 0);
5012 snd_hdsp_flush_midi_input (hdsp, 1);
5015 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5019 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5021 "Error creating pcm interface\n");
5026 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5028 "Error creating first midi interface\n");
5032 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5033 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5035 "Error creating second midi interface\n");
5040 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5042 "Error creating ctl interface\n");
5046 snd_hdsp_proc_init(hdsp);
5048 hdsp->system_sample_rate = -1;
5049 hdsp->playback_pid = -1;
5050 hdsp->capture_pid = -1;
5051 hdsp->capture_substream = NULL;
5052 hdsp->playback_substream = NULL;
5054 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5056 "Error setting default values\n");
5060 if (!(hdsp->state & HDSP_InitializationComplete)) {
5061 strcpy(card->shortname, "Hammerfall DSP");
5062 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5063 hdsp->port, hdsp->irq);
5065 if ((err = snd_card_register(card)) < 0) {
5067 "error registering card\n");
5070 hdsp->state |= HDSP_InitializationComplete;
5076 /* load firmware via hotplug fw loader */
5077 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5080 const struct firmware *fw;
5083 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5085 if (hdsp->io_type == Undefined) {
5086 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5088 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5092 /* caution: max length of firmware filename is 30! */
5093 switch (hdsp->io_type) {
5095 fwfile = "rpm_firmware.bin";
5098 if (hdsp->firmware_rev == 0xa)
5099 fwfile = "multiface_firmware.bin";
5101 fwfile = "multiface_firmware_rev11.bin";
5104 if (hdsp->firmware_rev == 0xa)
5105 fwfile = "digiface_firmware.bin";
5107 fwfile = "digiface_firmware_rev11.bin";
5110 dev_err(hdsp->card->dev,
5111 "invalid io_type %d\n", hdsp->io_type);
5115 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5116 dev_err(hdsp->card->dev,
5117 "cannot load firmware %s\n", fwfile);
5120 if (fw->size < HDSP_FIRMWARE_SIZE) {
5121 dev_err(hdsp->card->dev,
5122 "too short firmware size %d (expected %d)\n",
5123 (int)fw->size, HDSP_FIRMWARE_SIZE);
5124 release_firmware(fw);
5128 hdsp->firmware = fw;
5130 hdsp->state |= HDSP_FirmwareCached;
5132 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5135 if (!(hdsp->state & HDSP_InitializationComplete)) {
5136 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5139 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5140 dev_err(hdsp->card->dev,
5141 "error creating hwdep device\n");
5144 snd_hdsp_initialize_channels(hdsp);
5145 snd_hdsp_initialize_midi_flush(hdsp);
5146 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5147 dev_err(hdsp->card->dev,
5148 "error creating alsa devices\n");
5155 static int snd_hdsp_create(struct snd_card *card,
5158 struct pci_dev *pci = hdsp->pci;
5165 hdsp->midi[0].rmidi = NULL;
5166 hdsp->midi[1].rmidi = NULL;
5167 hdsp->midi[0].input = NULL;
5168 hdsp->midi[1].input = NULL;
5169 hdsp->midi[0].output = NULL;
5170 hdsp->midi[1].output = NULL;
5171 hdsp->midi[0].pending = 0;
5172 hdsp->midi[1].pending = 0;
5173 spin_lock_init(&hdsp->midi[0].lock);
5174 spin_lock_init(&hdsp->midi[1].lock);
5175 hdsp->iobase = NULL;
5176 hdsp->control_register = 0;
5177 hdsp->control2_register = 0;
5178 hdsp->io_type = Undefined;
5179 hdsp->max_channels = 26;
5183 spin_lock_init(&hdsp->lock);
5185 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5187 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5188 hdsp->firmware_rev &= 0xff;
5190 /* From Martin Bjoernsen :
5191 "It is important that the card's latency timer register in
5192 the PCI configuration space is set to a value much larger
5193 than 0 by the computer's BIOS or the driver.
5194 The windows driver always sets this 8 bit register [...]
5195 to its maximum 255 to avoid problems with some computers."
5197 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5199 strcpy(card->driver, "H-DSP");
5200 strcpy(card->mixername, "Xilinx FPGA");
5202 if (hdsp->firmware_rev < 0xa)
5204 else if (hdsp->firmware_rev < 0x64)
5205 hdsp->card_name = "RME Hammerfall DSP";
5206 else if (hdsp->firmware_rev < 0x96) {
5207 hdsp->card_name = "RME HDSP 9652";
5210 hdsp->card_name = "RME HDSP 9632";
5211 hdsp->max_channels = 16;
5215 if ((err = pci_enable_device(pci)) < 0)
5218 pci_set_master(hdsp->pci);
5220 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5222 hdsp->port = pci_resource_start(pci, 0);
5223 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5224 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5225 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5229 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5230 KBUILD_MODNAME, hdsp)) {
5231 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5235 hdsp->irq = pci->irq;
5236 card->sync_irq = hdsp->irq;
5237 hdsp->precise_ptr = 0;
5238 hdsp->use_midi_tasklet = 1;
5239 hdsp->dds_value = 0;
5241 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5244 if (!is_9652 && !is_9632) {
5245 /* we wait a maximum of 10 seconds to let freshly
5246 * inserted cardbus cards do their hardware init */
5247 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5252 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5253 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5254 /* we don't fail as this can happen
5255 if userspace is not ready for
5258 dev_err(hdsp->card->dev,
5259 "couldn't get firmware from userspace. try using hdsploader\n");
5261 /* init is complete, we return */
5263 /* we defer initialization */
5264 dev_info(hdsp->card->dev,
5265 "card initialization pending : waiting for firmware\n");
5266 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5270 dev_info(hdsp->card->dev,
5271 "Firmware already present, initializing card.\n");
5272 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5273 hdsp->io_type = RPM;
5274 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5275 hdsp->io_type = Multiface;
5277 hdsp->io_type = Digiface;
5281 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5285 hdsp->io_type = H9652;
5288 hdsp->io_type = H9632;
5290 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5293 snd_hdsp_initialize_channels(hdsp);
5294 snd_hdsp_initialize_midi_flush(hdsp);
5296 hdsp->state |= HDSP_FirmwareLoaded;
5298 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5304 static int snd_hdsp_free(struct hdsp *hdsp)
5307 /* stop the audio, and cancel all interrupts */
5308 tasklet_kill(&hdsp->midi_tasklet);
5309 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5310 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5314 free_irq(hdsp->irq, (void *)hdsp);
5316 snd_hdsp_free_buffers(hdsp);
5318 release_firmware(hdsp->firmware);
5319 vfree(hdsp->fw_uploaded);
5320 iounmap(hdsp->iobase);
5323 pci_release_regions(hdsp->pci);
5325 pci_disable_device(hdsp->pci);
5329 static void snd_hdsp_card_free(struct snd_card *card)
5331 struct hdsp *hdsp = card->private_data;
5334 snd_hdsp_free(hdsp);
5337 static int snd_hdsp_probe(struct pci_dev *pci,
5338 const struct pci_device_id *pci_id)
5342 struct snd_card *card;
5345 if (dev >= SNDRV_CARDS)
5352 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5353 sizeof(struct hdsp), &card);
5357 hdsp = card->private_data;
5358 card->private_free = snd_hdsp_card_free;
5361 err = snd_hdsp_create(card, hdsp);
5365 strcpy(card->shortname, "Hammerfall DSP");
5366 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5367 hdsp->port, hdsp->irq);
5368 err = snd_card_register(card);
5371 snd_card_free(card);
5374 pci_set_drvdata(pci, card);
5379 static void snd_hdsp_remove(struct pci_dev *pci)
5381 snd_card_free(pci_get_drvdata(pci));
5384 static struct pci_driver hdsp_driver = {
5385 .name = KBUILD_MODNAME,
5386 .id_table = snd_hdsp_ids,
5387 .probe = snd_hdsp_probe,
5388 .remove = snd_hdsp_remove,
5391 module_pci_driver(hdsp_driver);