sound/soc/amd/acp-pcm-dma.c

   1 /*
   2  * AMD ALSA SoC PCM Driver for ACP 2.x
   3  *
   4  * Copyright 2014-2015 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/sizes.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <sound/soc.h>
  23 #include <drm/amd_asic_type.h>
  24 #include "acp.h"
  25
  26 #define DRV_NAME "acp_audio_dma"
  27
  28 #define PLAYBACK_MIN_NUM_PERIODS    2
  29 #define PLAYBACK_MAX_NUM_PERIODS    2
  30 #define PLAYBACK_MAX_PERIOD_SIZE    16384
  31 #define PLAYBACK_MIN_PERIOD_SIZE    1024
  32 #define CAPTURE_MIN_NUM_PERIODS     2
  33 #define CAPTURE_MAX_NUM_PERIODS     2
  34 #define CAPTURE_MAX_PERIOD_SIZE     16384
  35 #define CAPTURE_MIN_PERIOD_SIZE     1024
  36
  37 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
  38 #define MIN_BUFFER MAX_BUFFER
  39
  40 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
  41 #define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
  42 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
  43 #define ST_MIN_BUFFER ST_MAX_BUFFER
  44
  45 #define DRV_NAME "acp_audio_dma"
  46 bool bt_uart_enable = true;
  47 EXPORT_SYMBOL(bt_uart_enable);
  48
  49 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
  50         .info = SNDRV_PCM_INFO_INTERLEAVED |
  51                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  52                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  53                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  54         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  55                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  56         .channels_min = 1,
  57         .channels_max = 8,
  58         .rates = SNDRV_PCM_RATE_8000_96000,
  59         .rate_min = 8000,
  60         .rate_max = 96000,
  61         .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
  62         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
  63         .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
  64         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
  65         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
  66 };
  67
  68 static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
  69         .info = SNDRV_PCM_INFO_INTERLEAVED |
  70                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  71                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  72             SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  73         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  74                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  75         .channels_min = 1,
  76         .channels_max = 2,
  77         .rates = SNDRV_PCM_RATE_8000_48000,
  78         .rate_min = 8000,
  79         .rate_max = 48000,
  80         .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
  81         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
  82         .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
  83         .periods_min = CAPTURE_MIN_NUM_PERIODS,
  84         .periods_max = CAPTURE_MAX_NUM_PERIODS,
  85 };
  86
  87 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
  88         .info = SNDRV_PCM_INFO_INTERLEAVED |
  89                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  90                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  91                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  92         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  93                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  94         .channels_min = 1,
  95         .channels_max = 8,
  96         .rates = SNDRV_PCM_RATE_8000_96000,
  97         .rate_min = 8000,
  98         .rate_max = 96000,
  99         .buffer_bytes_max = ST_MAX_BUFFER,
 100         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
 101         .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
 102         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
 103         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
 104 };
 105
 106 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
 107         .info = SNDRV_PCM_INFO_INTERLEAVED |
 108                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
 109                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
 110                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
 111         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 112                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 113         .channels_min = 1,
 114         .channels_max = 2,
 115         .rates = SNDRV_PCM_RATE_8000_48000,
 116         .rate_min = 8000,
 117         .rate_max = 48000,
 118         .buffer_bytes_max = ST_MAX_BUFFER,
 119         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
 120         .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
 121         .periods_min = CAPTURE_MIN_NUM_PERIODS,
 122         .periods_max = CAPTURE_MAX_NUM_PERIODS,
 123 };
 124
 125 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 126 {
 127         return readl(acp_mmio + (reg * 4));
 128 }
 129
 130 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
 131 {
 132         writel(val, acp_mmio + (reg * 4));
 133 }
 134
 135 /*
 136  * Configure a given dma channel parameters - enable/disable,
 137  * number of descriptors, priority
 138  */
 139 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
 140                                    u16 dscr_strt_idx, u16 num_dscrs,
 141                                    enum acp_dma_priority_level priority_level)
 142 {
 143         u32 dma_ctrl;
 144
 145         /* disable the channel run field */
 146         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 147         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
 148         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 149
 150         /* program a DMA channel with first descriptor to be processed. */
 151         acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
 152                         & dscr_strt_idx),
 153                         acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
 154
 155         /*
 156          * program a DMA channel with the number of descriptors to be
 157          * processed in the transfer
 158          */
 159         acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
 160                       acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
 161
 162         /* set DMA channel priority */
 163         acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
 164 }
 165
 166 /* Initialize a dma descriptor in SRAM based on descritor information passed */
 167 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
 168                                           u16 descr_idx,
 169                                           acp_dma_dscr_transfer_t *descr_info)
 170 {
 171         u32 sram_offset;
 172
 173         sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
 174
 175         /* program the source base address. */
 176         acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 177         acp_reg_write(descr_info->src,  acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 178         /* program the destination base address. */
 179         acp_reg_write(sram_offset + 4,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 180         acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 181
 182         /* program the number of bytes to be transferred for this descriptor. */
 183         acp_reg_write(sram_offset + 8,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 184         acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 185 }
 186
 187 /*
 188  * Initialize the DMA descriptor information for transfer between
 189  * system memory <-> ACP SRAM
 190  */
 191 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
 192                                            u32 size, int direction,
 193                                            u32 pte_offset, u16 ch,
 194                                            u32 sram_bank, u16 dma_dscr_idx,
 195                                            u32 asic_type)
 196 {
 197         u16 i;
 198         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
 199
 200         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
 201                 dmadscr[i].xfer_val = 0;
 202                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 203                         dma_dscr_idx = dma_dscr_idx + i;
 204                         dmadscr[i].dest = sram_bank + (i * (size / 2));
 205                         dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
 206                                 + (pte_offset * SZ_4K) + (i * (size / 2));
 207                         switch (asic_type) {
 208                         case CHIP_STONEY:
 209                                 dmadscr[i].xfer_val |=
 210                                 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
 211                                 (size / 2);
 212                                 break;
 213                         default:
 214                                 dmadscr[i].xfer_val |=
 215                                 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |
 216                                 (size / 2);
 217                         }
 218                 } else {
 219                         dma_dscr_idx = dma_dscr_idx + i;
 220                         dmadscr[i].src = sram_bank + (i * (size / 2));
 221                         dmadscr[i].dest =
 222                         ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
 223                         (pte_offset * SZ_4K) + (i * (size / 2));
 224                         switch (asic_type) {
 225                         case CHIP_STONEY:
 226                                 dmadscr[i].xfer_val |=
 227                                 BIT(22) |
 228                                 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
 229                                 (size / 2);
 230                                 break;
 231                         default:
 232                                 dmadscr[i].xfer_val |=
 233                                 BIT(22) |
 234                                 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
 235                                 (size / 2);
 236                         }
 237                 }
 238                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
 239                                               &dmadscr[i]);
 240         }
 241         config_acp_dma_channel(acp_mmio, ch,
 242                                dma_dscr_idx - 1,
 243                                NUM_DSCRS_PER_CHANNEL,
 244                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
 245 }
 246
 247 /*
 248  * Initialize the DMA descriptor information for transfer between
 249  * ACP SRAM <-> I2S
 250  */
 251 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
 252                                            int direction, u32 sram_bank,
 253                                            u16 destination, u16 ch,
 254                                            u16 dma_dscr_idx, u32 asic_type)
 255 {
 256         u16 i;
 257         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
 258
 259         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
 260                 dmadscr[i].xfer_val = 0;
 261                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 262                         dma_dscr_idx = dma_dscr_idx + i;
 263                         dmadscr[i].src = sram_bank  + (i * (size / 2));
 264                         /* dmadscr[i].dest is unused by hardware. */
 265                         dmadscr[i].dest = 0;
 266                         dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
 267                                                 (size / 2);
 268                 } else {
 269                         dma_dscr_idx = dma_dscr_idx + i;
 270                         /* dmadscr[i].src is unused by hardware. */
 271                         dmadscr[i].src = 0;
 272                         dmadscr[i].dest =
 273                                  sram_bank + (i * (size / 2));
 274                         dmadscr[i].xfer_val |= BIT(22) |
 275                                 (destination << 16) | (size / 2);
 276                 }
 277                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
 278                                               &dmadscr[i]);
 279         }
 280         /* Configure the DMA channel with the above descriptore */
 281         config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
 282                                NUM_DSCRS_PER_CHANNEL,
 283                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
 284 }
 285
 286 /* Create page table entries in ACP SRAM for the allocated memory */
 287 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
 288                            u16 num_of_pages, u32 pte_offset)
 289 {
 290         u16 page_idx;
 291         u64 addr;
 292         u32 low;
 293         u32 high;
 294         u32 offset;
 295
 296         offset  = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
 297         for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
 298                 /* Load the low address of page int ACP SRAM through SRBM */
 299                 acp_reg_write((offset + (page_idx * 8)),
 300                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 301                 addr = page_to_phys(pg);
 302
 303                 low = lower_32_bits(addr);
 304                 high = upper_32_bits(addr);
 305
 306                 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 307
 308                 /* Load the High address of page int ACP SRAM through SRBM */
 309                 acp_reg_write((offset + (page_idx * 8) + 4),
 310                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 311
 312                 /* page enable in ACP */
 313                 high |= BIT(31);
 314                 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 315
 316                 /* Move to next physically contiguos page */
 317                 pg++;
 318         }
 319 }
 320
 321 static void config_acp_dma(void __iomem *acp_mmio,
 322                            struct audio_substream_data *rtd,
 323                            u32 asic_type)
 324 {
 325         acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
 326                        rtd->pte_offset);
 327         /* Configure System memory <-> ACP SRAM DMA descriptors */
 328         set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
 329                                        rtd->direction, rtd->pte_offset,
 330                                        rtd->ch1, rtd->sram_bank,
 331                                        rtd->dma_dscr_idx_1, asic_type);
 332         /* Configure ACP SRAM <-> I2S DMA descriptors */
 333         set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
 334                                        rtd->direction, rtd->sram_bank,
 335                                        rtd->destination, rtd->ch2,
 336                                        rtd->dma_dscr_idx_2, asic_type);
 337 }
 338
 339 /* Start a given DMA channel transfer */
 340 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num)
 341 {
 342         u32 dma_ctrl;
 343
 344         /* read the dma control register and disable the channel run field */
 345         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 346
 347         /* Invalidating the DAGB cache */
 348         acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
 349
 350         /*
 351          * configure the DMA channel and start the DMA transfer
 352          * set dmachrun bit to start the transfer and enable the
 353          * interrupt on completion of the dma transfer
 354          */
 355         dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
 356
 357         switch (ch_num) {
 358         case ACP_TO_I2S_DMA_CH_NUM:
 359         case ACP_TO_SYSRAM_CH_NUM:
 360         case I2S_TO_ACP_DMA_CH_NUM:
 361         case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
 362         case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM:
 363         case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
 364                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 365                 break;
 366         default:
 367                 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 368                 break;
 369         }
 370
 371         /* circular for both DMA channel */
 372         dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
 373
 374         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 375 }
 376
 377 /* Stop a given DMA channel transfer */
 378 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
 379 {
 380         u32 dma_ctrl;
 381         u32 dma_ch_sts;
 382         u32 count = ACP_DMA_RESET_TIME;
 383
 384         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 385
 386         /*
 387          * clear the dma control register fields before writing zero
 388          * in reset bit
 389          */
 390         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
 391         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 392
 393         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 394         dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
 395
 396         if (dma_ch_sts & BIT(ch_num)) {
 397                 /*
 398                  * set the reset bit for this channel to stop the dma
 399                  *  transfer
 400                  */
 401                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
 402                 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 403         }
 404
 405         /* check the channel status bit for some time and return the status */
 406         while (true) {
 407                 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
 408                 if (!(dma_ch_sts & BIT(ch_num))) {
 409                         /*
 410                          * clear the reset flag after successfully stopping
 411                          * the dma transfer and break from the loop
 412                          */
 413                         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
 414
 415                         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
 416                                       + ch_num);
 417                         break;
 418                 }
 419                 if (--count == 0) {
 420                         pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
 421                         return -ETIMEDOUT;
 422                 }
 423                 udelay(100);
 424         }
 425         return 0;
 426 }
 427
 428 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
 429                                     bool power_on)
 430 {
 431         u32 val, req_reg, sts_reg, sts_reg_mask;
 432         u32 loops = 1000;
 433
 434         if (bank < 32) {
 435                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
 436                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
 437                 sts_reg_mask = 0xFFFFFFFF;
 438
 439         } else {
 440                 bank -= 32;
 441                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
 442                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
 443                 sts_reg_mask = 0x0000FFFF;
 444         }
 445
 446         val = acp_reg_read(acp_mmio, req_reg);
 447         if (val & (1 << bank)) {
 448                 /* bank is in off state */
 449                 if (power_on == true)
 450                         /* request to on */
 451                         val &= ~(1 << bank);
 452                 else
 453                         /* request to off */
 454                         return;
 455         } else {
 456                 /* bank is in on state */
 457                 if (power_on == false)
 458                         /* request to off */
 459                         val |= 1 << bank;
 460                 else
 461                         /* request to on */
 462                         return;
 463         }
 464         acp_reg_write(val, acp_mmio, req_reg);
 465
 466         while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
 467                 if (!loops--) {
 468                         pr_err("ACP SRAM bank %d state change failed\n", bank);
 469                         break;
 470                 }
 471                 cpu_relax();
 472         }
 473 }
 474
 475 /* Initialize and bring ACP hardware to default state. */
 476 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
 477 {
 478         u16 bank;
 479         u32 val, count, sram_pte_offset;
 480
 481         /* Assert Soft reset of ACP */
 482         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 483
 484         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
 485         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 486
 487         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
 488         while (true) {
 489                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 490                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
 491                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
 492                         break;
 493                 if (--count == 0) {
 494                         pr_err("Failed to reset ACP\n");
 495                         return -ETIMEDOUT;
 496                 }
 497                 udelay(100);
 498         }
 499
 500         /* Enable clock to ACP and wait until the clock is enabled */
 501         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
 502         val = val | ACP_CONTROL__ClkEn_MASK;
 503         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
 504
 505         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
 506
 507         while (true) {
 508                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
 509                 if (val & (u32)0x1)
 510                         break;
 511                 if (--count == 0) {
 512                         pr_err("Failed to reset ACP\n");
 513                         return -ETIMEDOUT;
 514                 }
 515                 udelay(100);
 516         }
 517
 518         /* Deassert the SOFT RESET flags */
 519         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 520         val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
 521         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 522
 523         /* For BT instance change pins from UART to BT */
 524         if (!bt_uart_enable) {
 525                 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
 526                 val |= ACP_BT_UART_PAD_SELECT_MASK;
 527                 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
 528         }
 529
 530         /* initiailize Onion control DAGB register */
 531         acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
 532                       mmACP_AXI2DAGB_ONION_CNTL);
 533
 534         /* initiailize Garlic control DAGB registers */
 535         acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
 536                       mmACP_AXI2DAGB_GARLIC_CNTL);
 537
 538         sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
 539                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
 540                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
 541                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
 542         acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
 543         acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
 544                       mmACP_DAGB_PAGE_SIZE_GRP_1);
 545
 546         acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
 547                       mmACP_DMA_DESC_BASE_ADDR);
 548
 549         /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
 550         acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
 551         acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
 552                       acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
 553
 554        /*
 555         * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
 556         * Now, turn off all of them. This can't be done in 'poweron' of
 557         * ACP pm domain, as this requires ACP to be initialized.
 558         * For Stoney, Memory gating is disabled,i.e SRAM Banks
 559         * won't be turned off. The default state for SRAM banks is ON.
 560         * Setting SRAM bank state code skipped for STONEY platform.
 561         */
 562         if (asic_type != CHIP_STONEY) {
 563                 for (bank = 1; bank < 48; bank++)
 564                         acp_set_sram_bank_state(acp_mmio, bank, false);
 565         }
 566         return 0;
 567 }
 568
 569 /* Deinitialize ACP */
 570 static int acp_deinit(void __iomem *acp_mmio)
 571 {
 572         u32 val;
 573         u32 count;
 574
 575         /* Assert Soft reset of ACP */
 576         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 577
 578         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
 579         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 580
 581         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
 582         while (true) {
 583                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 584                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
 585                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
 586                         break;
 587                 if (--count == 0) {
 588                         pr_err("Failed to reset ACP\n");
 589                         return -ETIMEDOUT;
 590                 }
 591                 udelay(100);
 592         }
 593         /* Disable ACP clock */
 594         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
 595         val &= ~ACP_CONTROL__ClkEn_MASK;
 596         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
 597
 598         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
 599
 600         while (true) {
 601                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
 602                 if (!(val & (u32)0x1))
 603                         break;
 604                 if (--count == 0) {
 605                         pr_err("Failed to reset ACP\n");
 606                         return -ETIMEDOUT;
 607                 }
 608                 udelay(100);
 609         }
 610         return 0;
 611 }
 612
 613 /* ACP DMA irq handler routine for playback, capture usecases */
 614 static irqreturn_t dma_irq_handler(int irq, void *arg)
 615 {
 616         u32 intr_flag, ext_intr_status;
 617         struct audio_drv_data *irq_data;
 618         void __iomem *acp_mmio;
 619         struct device *dev = arg;
 620         bool valid_irq = false;
 621
 622         irq_data = dev_get_drvdata(dev);
 623         acp_mmio = irq_data->acp_mmio;
 624
 625         ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 626         intr_flag = (((ext_intr_status &
 627                       ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
 628                      ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
 629
 630         if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
 631                 valid_irq = true;
 632                 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
 633                 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
 634                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 635         }
 636
 637         if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
 638                 valid_irq = true;
 639                 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
 640                 acp_reg_write((intr_flag &
 641                               BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
 642                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 643         }
 644
 645         if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
 646                 valid_irq = true;
 647                 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
 648                 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
 649                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 650         }
 651
 652         if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
 653                 valid_irq = true;
 654                 acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
 655                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 656         }
 657
 658         if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
 659                 valid_irq = true;
 660                 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
 661                 acp_reg_write((intr_flag &
 662                               BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
 663                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 664         }
 665
 666         if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) {
 667                 valid_irq = true;
 668                 acp_reg_write((intr_flag &
 669                               BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16,
 670                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 671         }
 672
 673         if (valid_irq)
 674                 return IRQ_HANDLED;
 675         else
 676                 return IRQ_NONE;
 677 }
 678
 679 static int acp_dma_open(struct snd_pcm_substream *substream)
 680 {
 681         u16 bank;
 682         int ret = 0;
 683         struct snd_pcm_runtime *runtime = substream->runtime;
 684         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 685         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 686                                                                     DRV_NAME);
 687         struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
 688         struct audio_substream_data *adata =
 689                 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
 690         if (!adata)
 691                 return -ENOMEM;
 692
 693         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 694                 switch (intr_data->asic_type) {
 695                 case CHIP_STONEY:
 696                         runtime->hw = acp_st_pcm_hardware_playback;
 697                         break;
 698                 default:
 699                         runtime->hw = acp_pcm_hardware_playback;
 700                 }
 701         } else {
 702                 switch (intr_data->asic_type) {
 703                 case CHIP_STONEY:
 704                         runtime->hw = acp_st_pcm_hardware_capture;
 705                         break;
 706                 default:
 707                         runtime->hw = acp_pcm_hardware_capture;
 708                 }
 709         }
 710
 711         ret = snd_pcm_hw_constraint_integer(runtime,
 712                                             SNDRV_PCM_HW_PARAM_PERIODS);
 713         if (ret < 0) {
 714                 dev_err(component->dev, "set integer constraint failed\n");
 715                 kfree(adata);
 716                 return ret;
 717         }
 718
 719         adata->acp_mmio = intr_data->acp_mmio;
 720         runtime->private_data = adata;
 721
 722         /*
 723          * Enable ACP irq, when neither playback or capture streams are
 724          * active by the time when a new stream is being opened.
 725          * This enablement is not required for another stream, if current
 726          * stream is not closed
 727          */
 728         if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
 729             !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
 730                 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
 731
 732         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 733                 /*
 734                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
 735                  * won't be turned off. The default state for SRAM banks is ON.
 736                  * Setting SRAM bank state code skipped for STONEY platform.
 737                  */
 738                 if (intr_data->asic_type != CHIP_STONEY) {
 739                         for (bank = 1; bank <= 4; bank++)
 740                                 acp_set_sram_bank_state(intr_data->acp_mmio,
 741                                                         bank, true);
 742                 }
 743         } else {
 744                 if (intr_data->asic_type != CHIP_STONEY) {
 745                         for (bank = 5; bank <= 8; bank++)
 746                                 acp_set_sram_bank_state(intr_data->acp_mmio,
 747                                                         bank, true);
 748                 }
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int acp_dma_hw_params(struct snd_pcm_substream *substream,
 755                              struct snd_pcm_hw_params *params)
 756 {
 757         int status;
 758         uint64_t size;
 759         u32 val = 0;
 760         struct page *pg;
 761         struct snd_pcm_runtime *runtime;
 762         struct audio_substream_data *rtd;
 763         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 764         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 765                                                                     DRV_NAME);
 766         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
 767         struct snd_soc_card *card = prtd->card;
 768         struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
 769
 770         runtime = substream->runtime;
 771         rtd = runtime->private_data;
 772
 773         if (WARN_ON(!rtd))
 774                 return -EINVAL;
 775
 776         rtd->i2s_instance = pinfo->i2s_instance;
 777         if (adata->asic_type == CHIP_STONEY) {
 778                 val = acp_reg_read(adata->acp_mmio,
 779                                    mmACP_I2S_16BIT_RESOLUTION_EN);
 780                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 781                         switch (rtd->i2s_instance) {
 782                         case I2S_BT_INSTANCE:
 783                                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
 784                                 break;
 785                         case I2S_SP_INSTANCE:
 786                         default:
 787                                 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
 788                         }
 789                 } else {
 790                         switch (rtd->i2s_instance) {
 791                         case I2S_BT_INSTANCE:
 792                                 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
 793                                 break;
 794                         case I2S_SP_INSTANCE:
 795                         default:
 796                                 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
 797                         }
 798                 }
 799                 acp_reg_write(val, adata->acp_mmio,
 800                               mmACP_I2S_16BIT_RESOLUTION_EN);
 801         }
 802
 803         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 804                 switch (rtd->i2s_instance) {
 805                 case I2S_BT_INSTANCE:
 806                         rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
 807                         rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
 808                         rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
 809                         rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
 810                         rtd->destination = TO_BLUETOOTH;
 811                         rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
 812                         rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
 813                         rtd->byte_cnt_high_reg_offset =
 814                                         mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
 815                         rtd->byte_cnt_low_reg_offset =
 816                                         mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
 817                         adata->play_i2sbt_stream = substream;
 818                         break;
 819                 case I2S_SP_INSTANCE:
 820                 default:
 821                         switch (adata->asic_type) {
 822                         case CHIP_STONEY:
 823                                 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
 824                                 break;
 825                         default:
 826                                 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
 827                         }
 828                         rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
 829                         rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
 830                         rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
 831                         rtd->destination = TO_ACP_I2S_1;
 832                         rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
 833                         rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
 834                         rtd->byte_cnt_high_reg_offset =
 835                                         mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
 836                         rtd->byte_cnt_low_reg_offset =
 837                                         mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
 838                         adata->play_i2ssp_stream = substream;
 839                 }
 840         } else {
 841                 switch (rtd->i2s_instance) {
 842                 case I2S_BT_INSTANCE:
 843                         rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
 844                         rtd->ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
 845                         rtd->ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
 846                         rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
 847                         rtd->destination = FROM_BLUETOOTH;
 848                         rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
 849                         rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
 850                         rtd->byte_cnt_high_reg_offset =
 851                                         mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
 852                         rtd->byte_cnt_low_reg_offset =
 853                                         mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
 854                         adata->capture_i2sbt_stream = substream;
 855                         break;
 856                 case I2S_SP_INSTANCE:
 857                 default:
 858                         rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
 859                         rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
 860                         rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
 861                         switch (adata->asic_type) {
 862                         case CHIP_STONEY:
 863                                 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
 864                                 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
 865                                 break;
 866                         default:
 867                                 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
 868                                 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
 869                         }
 870                         rtd->destination = FROM_ACP_I2S_1;
 871                         rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
 872                         rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
 873                         rtd->byte_cnt_high_reg_offset =
 874                                         mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
 875                         rtd->byte_cnt_low_reg_offset =
 876                                         mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
 877                         adata->capture_i2ssp_stream = substream;
 878                 }
 879         }
 880
 881         size = params_buffer_bytes(params);
 882         status = snd_pcm_lib_malloc_pages(substream, size);
 883         if (status < 0)
 884                 return status;
 885
 886         memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
 887         pg = virt_to_page(substream->dma_buffer.area);
 888
 889         if (pg) {
 890                 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
 891                 /* Save for runtime private data */
 892                 rtd->pg = pg;
 893                 rtd->order = get_order(size);
 894
 895                 /* Fill the page table entries in ACP SRAM */
 896                 rtd->pg = pg;
 897                 rtd->size = size;
 898                 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
 899                 rtd->direction = substream->stream;
 900
 901                 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
 902                 status = 0;
 903         } else {
 904                 status = -ENOMEM;
 905         }
 906         return status;
 907 }
 908
 909 static int acp_dma_hw_free(struct snd_pcm_substream *substream)
 910 {
 911         return snd_pcm_lib_free_pages(substream);
 912 }
 913
 914 static u64 acp_get_byte_count(struct audio_substream_data *rtd)
 915 {
 916         union acp_dma_count byte_count;
 917
 918         byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
 919                                               rtd->byte_cnt_high_reg_offset);
 920         byte_count.bcount.low  = acp_reg_read(rtd->acp_mmio,
 921                                               rtd->byte_cnt_low_reg_offset);
 922         return byte_count.bytescount;
 923 }
 924
 925 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
 926 {
 927         u32 buffersize;
 928         u32 pos = 0;
 929         u64 bytescount = 0;
 930
 931         struct snd_pcm_runtime *runtime = substream->runtime;
 932         struct audio_substream_data *rtd = runtime->private_data;
 933
 934         if (!rtd)
 935                 return -EINVAL;
 936
 937         buffersize = frames_to_bytes(runtime, runtime->buffer_size);
 938         bytescount = acp_get_byte_count(rtd);
 939
 940         if (bytescount > rtd->bytescount)
 941                 bytescount -= rtd->bytescount;
 942         pos = do_div(bytescount, buffersize);
 943         return bytes_to_frames(runtime, pos);
 944 }
 945
 946 static int acp_dma_mmap(struct snd_pcm_substream *substream,
 947                         struct vm_area_struct *vma)
 948 {
 949         return snd_pcm_lib_default_mmap(substream, vma);
 950 }
 951
 952 static int acp_dma_prepare(struct snd_pcm_substream *substream)
 953 {
 954         struct snd_pcm_runtime *runtime = substream->runtime;
 955         struct audio_substream_data *rtd = runtime->private_data;
 956
 957         if (!rtd)
 958                 return -EINVAL;
 959
 960         config_acp_dma_channel(rtd->acp_mmio,
 961                                rtd->ch1,
 962                                rtd->dma_dscr_idx_1,
 963                                NUM_DSCRS_PER_CHANNEL, 0);
 964         config_acp_dma_channel(rtd->acp_mmio,
 965                                rtd->ch2,
 966                                rtd->dma_dscr_idx_2,
 967                                NUM_DSCRS_PER_CHANNEL, 0);
 968         return 0;
 969 }
 970
 971 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
 972 {
 973         int ret;
 974         u64 bytescount = 0;
 975
 976         struct snd_pcm_runtime *runtime = substream->runtime;
 977         struct audio_substream_data *rtd = runtime->private_data;
 978
 979         if (!rtd)
 980                 return -EINVAL;
 981         switch (cmd) {
 982         case SNDRV_PCM_TRIGGER_START:
 983         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 984         case SNDRV_PCM_TRIGGER_RESUME:
 985                 bytescount = acp_get_byte_count(rtd);
 986                 if (rtd->bytescount == 0)
 987                         rtd->bytescount = bytescount;
 988                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 989                         acp_dma_start(rtd->acp_mmio, rtd->ch1);
 990                         acp_dma_start(rtd->acp_mmio, rtd->ch2);
 991                 } else {
 992                         acp_dma_start(rtd->acp_mmio, rtd->ch2);
 993                         acp_dma_start(rtd->acp_mmio, rtd->ch1);
 994                 }
 995                 ret = 0;
 996                 break;
 997         case SNDRV_PCM_TRIGGER_STOP:
 998         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 999         case SNDRV_PCM_TRIGGER_SUSPEND:
1000                 /* For playback, non circular dma should be stopped first
1001                  * i.e Sysram to acp dma transfer channel(rtd->ch1) should be
1002                  * stopped before stopping cirular dma which is acp sram to i2s
1003                  * fifo dma transfer channel(rtd->ch2). Where as in Capture
1004                  * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
1005                  * first before stopping acp sram to sysram which is circular
1006                  * dma(rtd->ch1).
1007                  */
1008                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1009                         acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1010                         ret =  acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1011                 } else {
1012                         acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1013                         ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1014                 }
1015                 rtd->bytescount = 0;
1016                 break;
1017         default:
1018                 ret = -EINVAL;
1019         }
1020         return ret;
1021 }
1022
1023 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
1024 {
1025         int ret;
1026         struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
1027                                                                     DRV_NAME);
1028         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1029
1030         switch (adata->asic_type) {
1031         case CHIP_STONEY:
1032                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1033                                                             SNDRV_DMA_TYPE_DEV,
1034                                                             NULL, ST_MIN_BUFFER,
1035                                                             ST_MAX_BUFFER);
1036                 break;
1037         default:
1038                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1039                                                             SNDRV_DMA_TYPE_DEV,
1040                                                             NULL, MIN_BUFFER,
1041                                                             MAX_BUFFER);
1042                 break;
1043         }
1044         if (ret < 0)
1045                 dev_err(component->dev,
1046                         "buffer preallocation failure error:%d\n", ret);
1047         return ret;
1048 }
1049
1050 static int acp_dma_close(struct snd_pcm_substream *substream)
1051 {
1052         u16 bank;
1053         struct snd_pcm_runtime *runtime = substream->runtime;
1054         struct audio_substream_data *rtd = runtime->private_data;
1055         struct snd_soc_pcm_runtime *prtd = substream->private_data;
1056         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
1057                                                                     DRV_NAME);
1058         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1059
1060         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1061                 switch (rtd->i2s_instance) {
1062                 case I2S_BT_INSTANCE:
1063                         adata->play_i2sbt_stream = NULL;
1064                         break;
1065                 case I2S_SP_INSTANCE:
1066                 default:
1067                         adata->play_i2ssp_stream = NULL;
1068                         /*
1069                          * For Stoney, Memory gating is disabled,i.e SRAM Banks
1070                          * won't be turned off. The default state for SRAM banks
1071                          * is ON.Setting SRAM bank state code skipped for STONEY
1072                          * platform. Added condition checks for Carrizo platform
1073                          * only.
1074                          */
1075                         if (adata->asic_type != CHIP_STONEY) {
1076                                 for (bank = 1; bank <= 4; bank++)
1077                                         acp_set_sram_bank_state(adata->acp_mmio,
1078                                                                 bank, false);
1079                         }
1080                 }
1081         } else  {
1082                 switch (rtd->i2s_instance) {
1083                 case I2S_BT_INSTANCE:
1084                         adata->capture_i2sbt_stream = NULL;
1085                         break;
1086                 case I2S_SP_INSTANCE:
1087                 default:
1088                         adata->capture_i2ssp_stream = NULL;
1089                         if (adata->asic_type != CHIP_STONEY) {
1090                                 for (bank = 5; bank <= 8; bank++)
1091                                         acp_set_sram_bank_state(adata->acp_mmio,
1092                                                                 bank, false);
1093                         }
1094                 }
1095         }
1096
1097         /*
1098          * Disable ACP irq, when the current stream is being closed and
1099          * another stream is also not active.
1100          */
1101         if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
1102             !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
1103                 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1104         kfree(rtd);
1105         return 0;
1106 }
1107
1108 static const struct snd_pcm_ops acp_dma_ops = {
1109         .open = acp_dma_open,
1110         .close = acp_dma_close,
1111         .ioctl = snd_pcm_lib_ioctl,
1112         .hw_params = acp_dma_hw_params,
1113         .hw_free = acp_dma_hw_free,
1114         .trigger = acp_dma_trigger,
1115         .pointer = acp_dma_pointer,
1116         .mmap = acp_dma_mmap,
1117         .prepare = acp_dma_prepare,
1118 };
1119
1120 static const struct snd_soc_component_driver acp_asoc_platform = {
1121         .name = DRV_NAME,
1122         .ops = &acp_dma_ops,
1123         .pcm_new = acp_dma_new,
1124 };
1125
1126 static int acp_audio_probe(struct platform_device *pdev)
1127 {
1128         int status;
1129         struct audio_drv_data *audio_drv_data;
1130         struct resource *res;
1131         const u32 *pdata = pdev->dev.platform_data;
1132
1133         if (!pdata) {
1134                 dev_err(&pdev->dev, "Missing platform data\n");
1135                 return -ENODEV;
1136         }
1137
1138         audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1139                                       GFP_KERNEL);
1140         if (!audio_drv_data)
1141                 return -ENOMEM;
1142
1143         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1144         audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1145         if (IS_ERR(audio_drv_data->acp_mmio))
1146                 return PTR_ERR(audio_drv_data->acp_mmio);
1147
1148         /*
1149          * The following members gets populated in device 'open'
1150          * function. Till then interrupts are disabled in 'acp_init'
1151          * and device doesn't generate any interrupts.
1152          */
1153
1154         audio_drv_data->play_i2ssp_stream = NULL;
1155         audio_drv_data->capture_i2ssp_stream = NULL;
1156         audio_drv_data->play_i2sbt_stream = NULL;
1157         audio_drv_data->capture_i2sbt_stream = NULL;
1158
1159         audio_drv_data->asic_type =  *pdata;
1160
1161         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1162         if (!res) {
1163                 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
1164                 return -ENODEV;
1165         }
1166
1167         status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1168                                   0, "ACP_IRQ", &pdev->dev);
1169         if (status) {
1170                 dev_err(&pdev->dev, "ACP IRQ request failed\n");
1171                 return status;
1172         }
1173
1174         dev_set_drvdata(&pdev->dev, audio_drv_data);
1175
1176         /* Initialize the ACP */
1177         status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1178         if (status) {
1179                 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1180                 return status;
1181         }
1182
1183         status = devm_snd_soc_register_component(&pdev->dev,
1184                                                  &acp_asoc_platform, NULL, 0);
1185         if (status != 0) {
1186                 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1187                 return status;
1188         }
1189
1190         pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1191         pm_runtime_use_autosuspend(&pdev->dev);
1192         pm_runtime_enable(&pdev->dev);
1193
1194         return status;
1195 }
1196
1197 static int acp_audio_remove(struct platform_device *pdev)
1198 {
1199         int status;
1200         struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1201
1202         status = acp_deinit(adata->acp_mmio);
1203         if (status)
1204                 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1205         pm_runtime_disable(&pdev->dev);
1206
1207         return 0;
1208 }
1209
1210 static int acp_pcm_resume(struct device *dev)
1211 {
1212         u16 bank;
1213         int status;
1214         struct audio_substream_data *rtd;
1215         struct audio_drv_data *adata = dev_get_drvdata(dev);
1216
1217         status = acp_init(adata->acp_mmio, adata->asic_type);
1218         if (status) {
1219                 dev_err(dev, "ACP Init failed status:%d\n", status);
1220                 return status;
1221         }
1222
1223         if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1224                 /*
1225                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
1226                  * won't be turned off. The default state for SRAM banks is ON.
1227                  * Setting SRAM bank state code skipped for STONEY platform.
1228                  */
1229                 if (adata->asic_type != CHIP_STONEY) {
1230                         for (bank = 1; bank <= 4; bank++)
1231                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1232                                                         true);
1233                 }
1234                 rtd = adata->play_i2ssp_stream->runtime->private_data;
1235                 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1236         }
1237         if (adata->capture_i2ssp_stream &&
1238             adata->capture_i2ssp_stream->runtime) {
1239                 if (adata->asic_type != CHIP_STONEY) {
1240                         for (bank = 5; bank <= 8; bank++)
1241                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1242                                                         true);
1243                 }
1244                 rtd =  adata->capture_i2ssp_stream->runtime->private_data;
1245                 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1246         }
1247         if (adata->asic_type != CHIP_CARRIZO) {
1248                 if (adata->play_i2sbt_stream &&
1249                     adata->play_i2sbt_stream->runtime) {
1250                         rtd = adata->play_i2sbt_stream->runtime->private_data;
1251                         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1252                 }
1253                 if (adata->capture_i2sbt_stream &&
1254                     adata->capture_i2sbt_stream->runtime) {
1255                         rtd = adata->capture_i2sbt_stream->runtime->private_data;
1256                         config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1257                 }
1258         }
1259         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1260         return 0;
1261 }
1262
1263 static int acp_pcm_runtime_suspend(struct device *dev)
1264 {
1265         int status;
1266         struct audio_drv_data *adata = dev_get_drvdata(dev);
1267
1268         status = acp_deinit(adata->acp_mmio);
1269         if (status)
1270                 dev_err(dev, "ACP Deinit failed status:%d\n", status);
1271         acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1272         return 0;
1273 }
1274
1275 static int acp_pcm_runtime_resume(struct device *dev)
1276 {
1277         int status;
1278         struct audio_drv_data *adata = dev_get_drvdata(dev);
1279
1280         status = acp_init(adata->acp_mmio, adata->asic_type);
1281         if (status) {
1282                 dev_err(dev, "ACP Init failed status:%d\n", status);
1283                 return status;
1284         }
1285         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1286         return 0;
1287 }
1288
1289 static const struct dev_pm_ops acp_pm_ops = {
1290         .resume = acp_pcm_resume,
1291         .runtime_suspend = acp_pcm_runtime_suspend,
1292         .runtime_resume = acp_pcm_runtime_resume,
1293 };
1294
1295 static struct platform_driver acp_dma_driver = {
1296         .probe = acp_audio_probe,
1297         .remove = acp_audio_remove,
1298         .driver = {
1299                 .name = DRV_NAME,
1300                 .pm = &acp_pm_ops,
1301         },
1302 };
1303
1304 module_platform_driver(acp_dma_driver);
1305
1306 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1307 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1308 MODULE_DESCRIPTION("AMD ACP PCM Driver");
1309 MODULE_LICENSE("GPL v2");
1310 MODULE_ALIAS("platform:"DRV_NAME);