sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <linux/of.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38
  39 static const struct reg_default cs42l42_reg_defaults[] = {
  40         { CS42L42_FRZ_CTL,                      0x00 },
  41         { CS42L42_SRC_CTL,                      0x10 },
  42         { CS42L42_MCLK_STATUS,                  0x02 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  46         { CS42L42_I2C_STRETCH,                  0x03 },
  47         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  48         { CS42L42_PWR_CTL1,                     0xFF },
  49         { CS42L42_PWR_CTL2,                     0x84 },
  50         { CS42L42_PWR_CTL3,                     0x20 },
  51         { CS42L42_RSENSE_CTL1,                  0x40 },
  52         { CS42L42_RSENSE_CTL2,                  0x00 },
  53         { CS42L42_OSC_SWITCH,                   0x00 },
  54         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_TRSENSE_STATUS,               0x00 },
  59         { CS42L42_HSDET_CTL1,                   0x77 },
  60         { CS42L42_HSDET_CTL2,                   0x00 },
  61         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  62         { CS42L42_HS_DET_STATUS,                0x00 },
  63         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  64         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  65         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  66         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  67         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  68         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  69         { CS42L42_FSYNC_P_UPPER,                0x00 },
  70         { CS42L42_ASP_CLK_CFG,                  0x00 },
  71         { CS42L42_ASP_FRM_CFG,                  0x10 },
  72         { CS42L42_FS_RATE_EN,                   0x00 },
  73         { CS42L42_IN_ASRC_CLK,                  0x00 },
  74         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  75         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  76         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  77         { CS42L42_MIXER_STATUS,                 0x00 },
  78         { CS42L42_SRC_STATUS,                   0x00 },
  79         { CS42L42_ASP_RX_STATUS,                0x00 },
  80         { CS42L42_ASP_TX_STATUS,                0x00 },
  81         { CS42L42_CODEC_STATUS,                 0x00 },
  82         { CS42L42_DET_INT_STATUS1,              0x00 },
  83         { CS42L42_DET_INT_STATUS2,              0x00 },
  84         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  85         { CS42L42_VPMON_STATUS,                 0x00 },
  86         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  87         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  88         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  89         { CS42L42_MIXER_INT_MASK,               0x0F },
  90         { CS42L42_SRC_INT_MASK,                 0x0F },
  91         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  92         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  93         { CS42L42_CODEC_INT_MASK,               0x03 },
  94         { CS42L42_SRCPL_INT_MASK,               0xFF },
  95         { CS42L42_VPMON_INT_MASK,               0x01 },
  96         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  97         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  98         { CS42L42_PLL_CTL1,                     0x00 },
  99         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 100         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 101         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 102         { CS42L42_PLL_DIV_INT,                  0x40 },
 103         { CS42L42_PLL_CTL3,                     0x10 },
 104         { CS42L42_PLL_CAL_RATIO,                0x80 },
 105         { CS42L42_PLL_CTL4,                     0x03 },
 106         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 107         { CS42L42_LOAD_DET_DONE,                0x00 },
 108         { CS42L42_LOAD_DET_EN,                  0x00 },
 109         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 110         { CS42L42_WAKE_CTL,                     0xC0 },
 111         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 112         { CS42L42_TIPSENSE_CTL,                 0x02 },
 113         { CS42L42_MISC_DET_CTL,                 0x03 },
 114         { CS42L42_MIC_DET_CTL1,                 0x1F },
 115         { CS42L42_MIC_DET_CTL2,                 0x2F },
 116         { CS42L42_DET_STATUS1,                  0x00 },
 117         { CS42L42_DET_STATUS2,                  0x00 },
 118         { CS42L42_DET_INT1_MASK,                0xE0 },
 119         { CS42L42_DET_INT2_MASK,                0xFF },
 120         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 121         { CS42L42_ADC_CTL,                      0x00 },
 122         { CS42L42_ADC_VOLUME,                   0x00 },
 123         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 124         { CS42L42_DAC_CTL1,                     0x00 },
 125         { CS42L42_DAC_CTL2,                     0x02 },
 126         { CS42L42_HP_CTL,                       0x0D },
 127         { CS42L42_CLASSH_CTL,                   0x07 },
 128         { CS42L42_MIXER_CHA_VOL,                0x3F },
 129         { CS42L42_MIXER_ADC_VOL,                0x3F },
 130         { CS42L42_MIXER_CHB_VOL,                0x3F },
 131         { CS42L42_EQ_COEF_IN0,                  0x22 },
 132         { CS42L42_EQ_COEF_IN1,                  0x00 },
 133         { CS42L42_EQ_COEF_IN2,                  0x00 },
 134         { CS42L42_EQ_COEF_IN3,                  0x00 },
 135         { CS42L42_EQ_COEF_RW,                   0x00 },
 136         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 137         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 138         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 139         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 140         { CS42L42_EQ_INIT_STAT,                 0x00 },
 141         { CS42L42_EQ_START_FILT,                0x00 },
 142         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 143         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 144         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 145         { CS42L42_SP_RX_FS,                     0x8C },
 146         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 147         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 148         { CS42L42_SP_TX_FS,                     0xCC },
 149         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 150         { CS42L42_SRC_SDIN_FS,                  0x40 },
 151         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 152         { CS42L42_SPDIF_CTL1,                   0x01 },
 153         { CS42L42_SPDIF_CTL2,                   0x00 },
 154         { CS42L42_SPDIF_CTL3,                   0x00 },
 155         { CS42L42_SPDIF_CTL4,                   0x42 },
 156         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 157         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 158         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 159         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 160         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 161         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 162         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 163         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 164         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 165         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 166         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 167         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 168         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 169         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 170         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 172         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 173         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 174         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 175         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 176         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 177         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 178         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 179         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 180         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 181         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 182         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 183         { CS42L42_SUB_REVID,                    0x03 },
 184 };
 185
 186 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 187 {
 188         switch (reg) {
 189         case CS42L42_PAGE_REGISTER:
 190         case CS42L42_DEVID_AB:
 191         case CS42L42_DEVID_CD:
 192         case CS42L42_DEVID_E:
 193         case CS42L42_FABID:
 194         case CS42L42_REVID:
 195         case CS42L42_FRZ_CTL:
 196         case CS42L42_SRC_CTL:
 197         case CS42L42_MCLK_STATUS:
 198         case CS42L42_MCLK_CTL:
 199         case CS42L42_SFTRAMP_RATE:
 200         case CS42L42_I2C_DEBOUNCE:
 201         case CS42L42_I2C_STRETCH:
 202         case CS42L42_I2C_TIMEOUT:
 203         case CS42L42_PWR_CTL1:
 204         case CS42L42_PWR_CTL2:
 205         case CS42L42_PWR_CTL3:
 206         case CS42L42_RSENSE_CTL1:
 207         case CS42L42_RSENSE_CTL2:
 208         case CS42L42_OSC_SWITCH:
 209         case CS42L42_OSC_SWITCH_STATUS:
 210         case CS42L42_RSENSE_CTL3:
 211         case CS42L42_TSENSE_CTL:
 212         case CS42L42_TSRS_INT_DISABLE:
 213         case CS42L42_TRSENSE_STATUS:
 214         case CS42L42_HSDET_CTL1:
 215         case CS42L42_HSDET_CTL2:
 216         case CS42L42_HS_SWITCH_CTL:
 217         case CS42L42_HS_DET_STATUS:
 218         case CS42L42_HS_CLAMP_DISABLE:
 219         case CS42L42_MCLK_SRC_SEL:
 220         case CS42L42_SPDIF_CLK_CFG:
 221         case CS42L42_FSYNC_PW_LOWER:
 222         case CS42L42_FSYNC_PW_UPPER:
 223         case CS42L42_FSYNC_P_LOWER:
 224         case CS42L42_FSYNC_P_UPPER:
 225         case CS42L42_ASP_CLK_CFG:
 226         case CS42L42_ASP_FRM_CFG:
 227         case CS42L42_FS_RATE_EN:
 228         case CS42L42_IN_ASRC_CLK:
 229         case CS42L42_OUT_ASRC_CLK:
 230         case CS42L42_PLL_DIV_CFG1:
 231         case CS42L42_ADC_OVFL_STATUS:
 232         case CS42L42_MIXER_STATUS:
 233         case CS42L42_SRC_STATUS:
 234         case CS42L42_ASP_RX_STATUS:
 235         case CS42L42_ASP_TX_STATUS:
 236         case CS42L42_CODEC_STATUS:
 237         case CS42L42_DET_INT_STATUS1:
 238         case CS42L42_DET_INT_STATUS2:
 239         case CS42L42_SRCPL_INT_STATUS:
 240         case CS42L42_VPMON_STATUS:
 241         case CS42L42_PLL_LOCK_STATUS:
 242         case CS42L42_TSRS_PLUG_STATUS:
 243         case CS42L42_ADC_OVFL_INT_MASK:
 244         case CS42L42_MIXER_INT_MASK:
 245         case CS42L42_SRC_INT_MASK:
 246         case CS42L42_ASP_RX_INT_MASK:
 247         case CS42L42_ASP_TX_INT_MASK:
 248         case CS42L42_CODEC_INT_MASK:
 249         case CS42L42_SRCPL_INT_MASK:
 250         case CS42L42_VPMON_INT_MASK:
 251         case CS42L42_PLL_LOCK_INT_MASK:
 252         case CS42L42_TSRS_PLUG_INT_MASK:
 253         case CS42L42_PLL_CTL1:
 254         case CS42L42_PLL_DIV_FRAC0:
 255         case CS42L42_PLL_DIV_FRAC1:
 256         case CS42L42_PLL_DIV_FRAC2:
 257         case CS42L42_PLL_DIV_INT:
 258         case CS42L42_PLL_CTL3:
 259         case CS42L42_PLL_CAL_RATIO:
 260         case CS42L42_PLL_CTL4:
 261         case CS42L42_LOAD_DET_RCSTAT:
 262         case CS42L42_LOAD_DET_DONE:
 263         case CS42L42_LOAD_DET_EN:
 264         case CS42L42_HSBIAS_SC_AUTOCTL:
 265         case CS42L42_WAKE_CTL:
 266         case CS42L42_ADC_DISABLE_MUTE:
 267         case CS42L42_TIPSENSE_CTL:
 268         case CS42L42_MISC_DET_CTL:
 269         case CS42L42_MIC_DET_CTL1:
 270         case CS42L42_MIC_DET_CTL2:
 271         case CS42L42_DET_STATUS1:
 272         case CS42L42_DET_STATUS2:
 273         case CS42L42_DET_INT1_MASK:
 274         case CS42L42_DET_INT2_MASK:
 275         case CS42L42_HS_BIAS_CTL:
 276         case CS42L42_ADC_CTL:
 277         case CS42L42_ADC_VOLUME:
 278         case CS42L42_ADC_WNF_HPF_CTL:
 279         case CS42L42_DAC_CTL1:
 280         case CS42L42_DAC_CTL2:
 281         case CS42L42_HP_CTL:
 282         case CS42L42_CLASSH_CTL:
 283         case CS42L42_MIXER_CHA_VOL:
 284         case CS42L42_MIXER_ADC_VOL:
 285         case CS42L42_MIXER_CHB_VOL:
 286         case CS42L42_EQ_COEF_IN0:
 287         case CS42L42_EQ_COEF_IN1:
 288         case CS42L42_EQ_COEF_IN2:
 289         case CS42L42_EQ_COEF_IN3:
 290         case CS42L42_EQ_COEF_RW:
 291         case CS42L42_EQ_COEF_OUT0:
 292         case CS42L42_EQ_COEF_OUT1:
 293         case CS42L42_EQ_COEF_OUT2:
 294         case CS42L42_EQ_COEF_OUT3:
 295         case CS42L42_EQ_INIT_STAT:
 296         case CS42L42_EQ_START_FILT:
 297         case CS42L42_EQ_MUTE_CTL:
 298         case CS42L42_SP_RX_CH_SEL:
 299         case CS42L42_SP_RX_ISOC_CTL:
 300         case CS42L42_SP_RX_FS:
 301         case CS42l42_SPDIF_CH_SEL:
 302         case CS42L42_SP_TX_ISOC_CTL:
 303         case CS42L42_SP_TX_FS:
 304         case CS42L42_SPDIF_SW_CTL1:
 305         case CS42L42_SRC_SDIN_FS:
 306         case CS42L42_SRC_SDOUT_FS:
 307         case CS42L42_SPDIF_CTL1:
 308         case CS42L42_SPDIF_CTL2:
 309         case CS42L42_SPDIF_CTL3:
 310         case CS42L42_SPDIF_CTL4:
 311         case CS42L42_ASP_TX_SZ_EN:
 312         case CS42L42_ASP_TX_CH_EN:
 313         case CS42L42_ASP_TX_CH_AP_RES:
 314         case CS42L42_ASP_TX_CH1_BIT_MSB:
 315         case CS42L42_ASP_TX_CH1_BIT_LSB:
 316         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 317         case CS42L42_ASP_TX_CH2_BIT_MSB:
 318         case CS42L42_ASP_TX_CH2_BIT_LSB:
 319         case CS42L42_ASP_RX_DAI0_EN:
 320         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 321         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 322         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 324         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 325         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 326         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 327         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 328         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 329         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 330         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 331         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 332         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 333         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 334         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 335         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 336         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 337         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 338         case CS42L42_SUB_REVID:
 339                 return true;
 340         default:
 341                 return false;
 342         }
 343 }
 344
 345 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 346 {
 347         switch (reg) {
 348         case CS42L42_DEVID_AB:
 349         case CS42L42_DEVID_CD:
 350         case CS42L42_DEVID_E:
 351         case CS42L42_MCLK_STATUS:
 352         case CS42L42_TRSENSE_STATUS:
 353         case CS42L42_HS_DET_STATUS:
 354         case CS42L42_ADC_OVFL_STATUS:
 355         case CS42L42_MIXER_STATUS:
 356         case CS42L42_SRC_STATUS:
 357         case CS42L42_ASP_RX_STATUS:
 358         case CS42L42_ASP_TX_STATUS:
 359         case CS42L42_CODEC_STATUS:
 360         case CS42L42_DET_INT_STATUS1:
 361         case CS42L42_DET_INT_STATUS2:
 362         case CS42L42_SRCPL_INT_STATUS:
 363         case CS42L42_VPMON_STATUS:
 364         case CS42L42_PLL_LOCK_STATUS:
 365         case CS42L42_TSRS_PLUG_STATUS:
 366         case CS42L42_LOAD_DET_RCSTAT:
 367         case CS42L42_LOAD_DET_DONE:
 368         case CS42L42_DET_STATUS1:
 369         case CS42L42_DET_STATUS2:
 370                 return true;
 371         default:
 372                 return false;
 373         }
 374 }
 375
 376 static const struct regmap_range_cfg cs42l42_page_range = {
 377         .name = "Pages",
 378         .range_min = 0,
 379         .range_max = CS42L42_MAX_REGISTER,
 380         .selector_reg = CS42L42_PAGE_REGISTER,
 381         .selector_mask = 0xff,
 382         .selector_shift = 0,
 383         .window_start = 0,
 384         .window_len = 256,
 385 };
 386
 387 static const struct regmap_config cs42l42_regmap = {
 388         .reg_bits = 8,
 389         .val_bits = 8,
 390
 391         .readable_reg = cs42l42_readable_register,
 392         .volatile_reg = cs42l42_volatile_register,
 393
 394         .ranges = &cs42l42_page_range,
 395         .num_ranges = 1,
 396
 397         .max_register = CS42L42_MAX_REGISTER,
 398         .reg_defaults = cs42l42_reg_defaults,
 399         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 400         .cache_type = REGCACHE_RBTREE,
 401 };
 402
 403 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false);
 404 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6200, 100, false);
 405
 406 static const char * const cs42l42_hpf_freq_text[] = {
 407         "1.86Hz", "120Hz", "235Hz", "466Hz"
 408 };
 409
 410 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 411                             CS42L42_ADC_HPF_CF_SHIFT,
 412                             cs42l42_hpf_freq_text);
 413
 414 static const char * const cs42l42_wnf3_freq_text[] = {
 415         "160Hz", "180Hz", "200Hz", "220Hz",
 416         "240Hz", "260Hz", "280Hz", "300Hz"
 417 };
 418
 419 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 420                             CS42L42_ADC_WNF_CF_SHIFT,
 421                             cs42l42_wnf3_freq_text);
 422
 423 static const char * const cs42l42_wnf05_freq_text[] = {
 424         "280Hz", "315Hz", "350Hz", "385Hz",
 425         "420Hz", "455Hz", "490Hz", "525Hz"
 426 };
 427
 428 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 429                             CS42L42_ADC_WNF_CF_SHIFT,
 430                             cs42l42_wnf05_freq_text);
 431
 432 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 433         /* ADC Volume and Filter Controls */
 434         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 435                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false),
 436         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 437                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 438         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 439                                 CS42L42_ADC_INV_SHIFT, true, false),
 440         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 441                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 442         SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME,
 443                                 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv),
 444         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 446         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 447                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 448         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 449         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 450         SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
 451
 452         /* DAC Volume and Filter Controls */
 453         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 454                                 CS42L42_DACA_INV_SHIFT, true, false),
 455         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 456                                 CS42L42_DACB_INV_SHIFT, true, false),
 457         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 458                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 459         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 460                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 461                                 0x3e, 1, mixer_tlv)
 462 };
 463
 464 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
 465                                 struct snd_kcontrol *kcontrol, int event)
 466 {
 467         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 468
 469         if (event & SND_SOC_DAPM_POST_PMU) {
 470                 /* Enable the channels */
 471                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 472                                 CS42L42_ASP_RX0_CH_EN_MASK,
 473                                 (CS42L42_ASP_RX0_CH1_EN |
 474                                 CS42L42_ASP_RX0_CH2_EN) <<
 475                                 CS42L42_ASP_RX0_CH_EN_SHIFT);
 476
 477                 /* Power up */
 478                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 479                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 480                                 CS42L42_HP_PDN_MASK, 0);
 481         } else if (event & SND_SOC_DAPM_PRE_PMD) {
 482                 /* Disable the channels */
 483                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 484                                 CS42L42_ASP_RX0_CH_EN_MASK, 0);
 485
 486                 /* Power down */
 487                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 488                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 489                                 CS42L42_HP_PDN_MASK,
 490                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 491                                 CS42L42_HP_PDN_MASK);
 492         } else {
 493                 dev_err(component->dev, "Invalid event 0x%x\n", event);
 494         }
 495         return 0;
 496 }
 497
 498 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 499         SND_SOC_DAPM_OUTPUT("HP"),
 500         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
 501                                         CS42L42_ASP_SCLK_EN_SHIFT, false),
 502         SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
 503                                         0, NULL, 0, cs42l42_hpdrv_evt,
 504                                         SND_SOC_DAPM_POST_PMU |
 505                                         SND_SOC_DAPM_PRE_PMD)
 506 };
 507
 508 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 509         {"SDIN", NULL, "Playback"},
 510         {"HPDRV", NULL, "SDIN"},
 511         {"HP", NULL, "HPDRV"}
 512 };
 513
 514 static int cs42l42_set_bias_level(struct snd_soc_component *component,
 515                                         enum snd_soc_bias_level level)
 516 {
 517         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 518         int ret;
 519
 520         switch (level) {
 521         case SND_SOC_BIAS_ON:
 522                 break;
 523         case SND_SOC_BIAS_PREPARE:
 524                 break;
 525         case SND_SOC_BIAS_STANDBY:
 526                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
 527                         regcache_cache_only(cs42l42->regmap, false);
 528                         regcache_sync(cs42l42->regmap);
 529                         ret = regulator_bulk_enable(
 530                                                 ARRAY_SIZE(cs42l42->supplies),
 531                                                 cs42l42->supplies);
 532                         if (ret != 0) {
 533                                 dev_err(component->dev,
 534                                         "Failed to enable regulators: %d\n",
 535                                         ret);
 536                                 return ret;
 537                         }
 538                 }
 539                 break;
 540         case SND_SOC_BIAS_OFF:
 541
 542                 regcache_cache_only(cs42l42->regmap, true);
 543                 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
 544                                                     cs42l42->supplies);
 545                 break;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static int cs42l42_component_probe(struct snd_soc_component *component)
 552 {
 553         struct cs42l42_private *cs42l42 =
 554                 (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
 555
 556         cs42l42->component = component;
 557
 558         return 0;
 559 }
 560
 561 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 562         .probe                  = cs42l42_component_probe,
 563         .set_bias_level         = cs42l42_set_bias_level,
 564         .dapm_widgets           = cs42l42_dapm_widgets,
 565         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 566         .dapm_routes            = cs42l42_audio_map,
 567         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 568         .controls               = cs42l42_snd_controls,
 569         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 570         .idle_bias_on           = 1,
 571         .endianness             = 1,
 572         .non_legacy_dai_naming  = 1,
 573 };
 574
 575 struct cs42l42_pll_params {
 576         u32 sclk;
 577         u8 mclk_div;
 578         u8 mclk_src_sel;
 579         u8 sclk_prediv;
 580         u8 pll_div_int;
 581         u32 pll_div_frac;
 582         u8 pll_mode;
 583         u8 pll_divout;
 584         u32 mclk_int;
 585         u8 pll_cal_ratio;
 586 };
 587
 588 /*
 589  * Common PLL Settings for given SCLK
 590  * Table 4-5 from the Datasheet
 591  */
 592 static const struct cs42l42_pll_params pll_ratio_table[] = {
 593         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
 594         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 595         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 596         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 597         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
 598         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
 599         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 600         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 601         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 602         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
 603         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
 604         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
 605         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
 606         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
 607         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
 608 };
 609
 610 static int cs42l42_pll_config(struct snd_soc_component *component)
 611 {
 612         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 613         int i;
 614         u32 fsync;
 615
 616         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 617                 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
 618                         /* Configure the internal sample rate */
 619                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 620                                         CS42L42_INTERNAL_FS_MASK,
 621                                         ((pll_ratio_table[i].mclk_int !=
 622                                         12000000) &&
 623                                         (pll_ratio_table[i].mclk_int !=
 624                                         24000000)) <<
 625                                         CS42L42_INTERNAL_FS_SHIFT);
 626                         /* Set the MCLK src (PLL or SCLK) and the divide
 627                          * ratio
 628                          */
 629                         snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
 630                                         CS42L42_MCLK_SRC_SEL_MASK |
 631                                         CS42L42_MCLKDIV_MASK,
 632                                         (pll_ratio_table[i].mclk_src_sel
 633                                         << CS42L42_MCLK_SRC_SEL_SHIFT) |
 634                                         (pll_ratio_table[i].mclk_div <<
 635                                         CS42L42_MCLKDIV_SHIFT));
 636                         /* Set up the LRCLK */
 637                         fsync = cs42l42->sclk / cs42l42->srate;
 638                         if (((fsync * cs42l42->srate) != cs42l42->sclk)
 639                                 || ((fsync % 2) != 0)) {
 640                                 dev_err(component->dev,
 641                                         "Unsupported sclk %d/sample rate %d\n",
 642                                         cs42l42->sclk,
 643                                         cs42l42->srate);
 644                                 return -EINVAL;
 645                         }
 646                         /* Set the LRCLK period */
 647                         snd_soc_component_update_bits(component,
 648                                         CS42L42_FSYNC_P_LOWER,
 649                                         CS42L42_FSYNC_PERIOD_MASK,
 650                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 651                                         CS42L42_FSYNC_PERIOD_SHIFT);
 652                         snd_soc_component_update_bits(component,
 653                                         CS42L42_FSYNC_P_UPPER,
 654                                         CS42L42_FSYNC_PERIOD_MASK,
 655                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 656                                         CS42L42_FSYNC_PERIOD_SHIFT);
 657                         /* Set the LRCLK to 50% duty cycle */
 658                         fsync = fsync / 2;
 659                         snd_soc_component_update_bits(component,
 660                                         CS42L42_FSYNC_PW_LOWER,
 661                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 662                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 663                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 664                         snd_soc_component_update_bits(component,
 665                                         CS42L42_FSYNC_PW_UPPER,
 666                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 667                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 668                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 669                         snd_soc_component_update_bits(component,
 670                                         CS42L42_ASP_FRM_CFG,
 671                                         CS42L42_ASP_5050_MASK,
 672                                         CS42L42_ASP_5050_MASK);
 673                         /* Set the frame delay to 1.0 SCLK clocks */
 674                         snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG,
 675                                         CS42L42_ASP_FSD_MASK,
 676                                         CS42L42_ASP_FSD_1_0 <<
 677                                         CS42L42_ASP_FSD_SHIFT);
 678                         /* Set the sample rates (96k or lower) */
 679                         snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
 680                                         CS42L42_FS_EN_MASK,
 681                                         (CS42L42_FS_EN_IASRC_96K |
 682                                         CS42L42_FS_EN_OASRC_96K) <<
 683                                         CS42L42_FS_EN_SHIFT);
 684                         /* Set the input/output internal MCLK clock ~12 MHz */
 685                         snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
 686                                         CS42L42_CLK_IASRC_SEL_MASK,
 687                                         CS42L42_CLK_IASRC_SEL_12 <<
 688                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 689                         snd_soc_component_update_bits(component,
 690                                         CS42L42_OUT_ASRC_CLK,
 691                                         CS42L42_CLK_OASRC_SEL_MASK,
 692                                         CS42L42_CLK_OASRC_SEL_12 <<
 693                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 694                         /* channel 1 on low LRCLK, 32 bit */
 695                         snd_soc_component_update_bits(component,
 696                                         CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 697                                         CS42L42_ASP_RX_CH_AP_MASK |
 698                                         CS42L42_ASP_RX_CH_RES_MASK,
 699                                         (CS42L42_ASP_RX_CH_AP_LOW <<
 700                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 701                                         (CS42L42_ASP_RX_CH_RES_32 <<
 702                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 703                         /* Channel 2 on high LRCLK, 32 bit */
 704                         snd_soc_component_update_bits(component,
 705                                         CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 706                                         CS42L42_ASP_RX_CH_AP_MASK |
 707                                         CS42L42_ASP_RX_CH_RES_MASK,
 708                                         (CS42L42_ASP_RX_CH_AP_HI <<
 709                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 710                                         (CS42L42_ASP_RX_CH_RES_32 <<
 711                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 712                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 713                                 /* Pass the clock straight through */
 714                                 snd_soc_component_update_bits(component,
 715                                         CS42L42_PLL_CTL1,
 716                                         CS42L42_PLL_START_MASK, 0);
 717                         } else {
 718                                 /* Configure PLL per table 4-5 */
 719                                 snd_soc_component_update_bits(component,
 720                                         CS42L42_PLL_DIV_CFG1,
 721                                         CS42L42_SCLK_PREDIV_MASK,
 722                                         pll_ratio_table[i].sclk_prediv
 723                                         << CS42L42_SCLK_PREDIV_SHIFT);
 724                                 snd_soc_component_update_bits(component,
 725                                         CS42L42_PLL_DIV_INT,
 726                                         CS42L42_PLL_DIV_INT_MASK,
 727                                         pll_ratio_table[i].pll_div_int
 728                                         << CS42L42_PLL_DIV_INT_SHIFT);
 729                                 snd_soc_component_update_bits(component,
 730                                         CS42L42_PLL_DIV_FRAC0,
 731                                         CS42L42_PLL_DIV_FRAC_MASK,
 732                                         CS42L42_FRAC0_VAL(
 733                                         pll_ratio_table[i].pll_div_frac)
 734                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 735                                 snd_soc_component_update_bits(component,
 736                                         CS42L42_PLL_DIV_FRAC1,
 737                                         CS42L42_PLL_DIV_FRAC_MASK,
 738                                         CS42L42_FRAC1_VAL(
 739                                         pll_ratio_table[i].pll_div_frac)
 740                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 741                                 snd_soc_component_update_bits(component,
 742                                         CS42L42_PLL_DIV_FRAC2,
 743                                         CS42L42_PLL_DIV_FRAC_MASK,
 744                                         CS42L42_FRAC2_VAL(
 745                                         pll_ratio_table[i].pll_div_frac)
 746                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 747                                 snd_soc_component_update_bits(component,
 748                                         CS42L42_PLL_CTL4,
 749                                         CS42L42_PLL_MODE_MASK,
 750                                         pll_ratio_table[i].pll_mode
 751                                         << CS42L42_PLL_MODE_SHIFT);
 752                                 snd_soc_component_update_bits(component,
 753                                         CS42L42_PLL_CTL3,
 754                                         CS42L42_PLL_DIVOUT_MASK,
 755                                         pll_ratio_table[i].pll_divout
 756                                         << CS42L42_PLL_DIVOUT_SHIFT);
 757                                 snd_soc_component_update_bits(component,
 758                                         CS42L42_PLL_CAL_RATIO,
 759                                         CS42L42_PLL_CAL_RATIO_MASK,
 760                                         pll_ratio_table[i].pll_cal_ratio
 761                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 762                         }
 763                         return 0;
 764                 }
 765         }
 766
 767         return -EINVAL;
 768 }
 769
 770 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 771 {
 772         struct snd_soc_component *component = codec_dai->component;
 773         u32 asp_cfg_val = 0;
 774
 775         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 776         case SND_SOC_DAIFMT_CBS_CFM:
 777                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 778                                 CS42L42_ASP_MODE_SHIFT;
 779                 break;
 780         case SND_SOC_DAIFMT_CBS_CFS:
 781                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 782                                 CS42L42_ASP_MODE_SHIFT;
 783                 break;
 784         default:
 785                 return -EINVAL;
 786         }
 787
 788         /* interface format */
 789         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 790         case SND_SOC_DAIFMT_I2S:
 791         case SND_SOC_DAIFMT_LEFT_J:
 792                 break;
 793         default:
 794                 return -EINVAL;
 795         }
 796
 797         /* Bitclock/frame inversion */
 798         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 799         case SND_SOC_DAIFMT_NB_NF:
 800                 break;
 801         case SND_SOC_DAIFMT_NB_IF:
 802                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 803                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 804                 break;
 805         case SND_SOC_DAIFMT_IB_NF:
 806                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 807                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 808                 break;
 809         case SND_SOC_DAIFMT_IB_IF:
 810                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 811                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 812                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 813                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 814                 break;
 815         }
 816
 817         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG,
 818                                 CS42L42_ASP_MODE_MASK |
 819                                 CS42L42_ASP_SCPOL_IN_DAC_MASK |
 820                                 CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val);
 821
 822         return 0;
 823 }
 824
 825 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 826                                 struct snd_pcm_hw_params *params,
 827                                 struct snd_soc_dai *dai)
 828 {
 829         struct snd_soc_component *component = dai->component;
 830         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 831         int retval;
 832
 833         cs42l42->srate = params_rate(params);
 834         cs42l42->swidth = params_width(params);
 835
 836         retval = cs42l42_pll_config(component);
 837
 838         return retval;
 839 }
 840
 841 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 842                                 int clk_id, unsigned int freq, int dir)
 843 {
 844         struct snd_soc_component *component = dai->component;
 845         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 846
 847         cs42l42->sclk = freq;
 848
 849         return 0;
 850 }
 851
 852 static int cs42l42_digital_mute(struct snd_soc_dai *dai, int mute)
 853 {
 854         struct snd_soc_component *component = dai->component;
 855         unsigned int regval;
 856         u8 fullScaleVol;
 857
 858         if (mute) {
 859                 /* Mark SCLK as not present to turn on the internal
 860                  * oscillator.
 861                  */
 862                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 863                                                 CS42L42_SCLK_PRESENT_MASK, 0);
 864
 865                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 866                                 CS42L42_PLL_START_MASK,
 867                                 0 << CS42L42_PLL_START_SHIFT);
 868
 869                 /* Mute the headphone */
 870                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 871                                 CS42L42_HP_ANA_AMUTE_MASK |
 872                                 CS42L42_HP_ANA_BMUTE_MASK,
 873                                 CS42L42_HP_ANA_AMUTE_MASK |
 874                                 CS42L42_HP_ANA_BMUTE_MASK);
 875         } else {
 876                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 877                                 CS42L42_PLL_START_MASK,
 878                                 1 << CS42L42_PLL_START_SHIFT);
 879                 /* Read the headphone load */
 880                 regval = snd_soc_component_read32(component, CS42L42_LOAD_DET_RCSTAT);
 881                 if (((regval & CS42L42_RLA_STAT_MASK) >>
 882                         CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
 883                         fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
 884                 } else {
 885                         fullScaleVol = 0;
 886                 }
 887
 888                 /* Un-mute the headphone, set the full scale volume flag */
 889                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 890                                 CS42L42_HP_ANA_AMUTE_MASK |
 891                                 CS42L42_HP_ANA_BMUTE_MASK |
 892                                 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
 893
 894                 /* Mark SCLK as present, turn off internal oscillator */
 895                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 896                                 CS42L42_SCLK_PRESENT_MASK,
 897                                 CS42L42_SCLK_PRESENT_MASK);
 898         }
 899
 900         return 0;
 901 }
 902
 903 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
 904                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
 905                         SNDRV_PCM_FMTBIT_S32_LE)
 906
 907
 908 static const struct snd_soc_dai_ops cs42l42_ops = {
 909         .hw_params      = cs42l42_pcm_hw_params,
 910         .set_fmt        = cs42l42_set_dai_fmt,
 911         .set_sysclk     = cs42l42_set_sysclk,
 912         .digital_mute = cs42l42_digital_mute
 913 };
 914
 915 static struct snd_soc_dai_driver cs42l42_dai = {
 916                 .name = "cs42l42",
 917                 .playback = {
 918                         .stream_name = "Playback",
 919                         .channels_min = 1,
 920                         .channels_max = 2,
 921                         .rates = SNDRV_PCM_RATE_8000_192000,
 922                         .formats = CS42L42_FORMATS,
 923                 },
 924                 .capture = {
 925                         .stream_name = "Capture",
 926                         .channels_min = 1,
 927                         .channels_max = 2,
 928                         .rates = SNDRV_PCM_RATE_8000_192000,
 929                         .formats = CS42L42_FORMATS,
 930                 },
 931                 .ops = &cs42l42_ops,
 932 };
 933
 934 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
 935 {
 936         unsigned int hs_det_status;
 937         unsigned int int_status;
 938
 939         /* Mask the auto detect interrupt */
 940         regmap_update_bits(cs42l42->regmap,
 941                 CS42L42_CODEC_INT_MASK,
 942                 CS42L42_PDN_DONE_MASK |
 943                 CS42L42_HSDET_AUTO_DONE_MASK,
 944                 (1 << CS42L42_PDN_DONE_SHIFT) |
 945                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
 946
 947         /* Set hs detect to automatic, disabled mode */
 948         regmap_update_bits(cs42l42->regmap,
 949                 CS42L42_HSDET_CTL2,
 950                 CS42L42_HSDET_CTRL_MASK |
 951                 CS42L42_HSDET_SET_MASK |
 952                 CS42L42_HSBIAS_REF_MASK |
 953                 CS42L42_HSDET_AUTO_TIME_MASK,
 954                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
 955                 (2 << CS42L42_HSDET_SET_SHIFT) |
 956                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 957                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 958
 959         /* Read and save the hs detection result */
 960         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
 961
 962         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
 963                                 CS42L42_HSDET_TYPE_SHIFT;
 964
 965         /* Set up button detection */
 966         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
 967               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
 968                 /* Set auto HS bias settings to default */
 969                 regmap_update_bits(cs42l42->regmap,
 970                         CS42L42_HSBIAS_SC_AUTOCTL,
 971                         CS42L42_HSBIAS_SENSE_EN_MASK |
 972                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 973                         CS42L42_TIP_SENSE_EN_MASK |
 974                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 975                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 976                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 977                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 978                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 979
 980                 /* Set up hs detect level sensitivity */
 981                 regmap_update_bits(cs42l42->regmap,
 982                         CS42L42_MIC_DET_CTL1,
 983                         CS42L42_LATCH_TO_VP_MASK |
 984                         CS42L42_EVENT_STAT_SEL_MASK |
 985                         CS42L42_HS_DET_LEVEL_MASK,
 986                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
 987                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
 988                         (cs42l42->bias_thresholds[0] <<
 989                         CS42L42_HS_DET_LEVEL_SHIFT));
 990
 991                 /* Set auto HS bias settings to default */
 992                 regmap_update_bits(cs42l42->regmap,
 993                         CS42L42_HSBIAS_SC_AUTOCTL,
 994                         CS42L42_HSBIAS_SENSE_EN_MASK |
 995                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 996                         CS42L42_TIP_SENSE_EN_MASK |
 997                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 998                         (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 999                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1000                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1001                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1002
1003                 /* Turn on level detect circuitry */
1004                 regmap_update_bits(cs42l42->regmap,
1005                         CS42L42_MISC_DET_CTL,
1006                         CS42L42_DETECT_MODE_MASK |
1007                         CS42L42_HSBIAS_CTL_MASK |
1008                         CS42L42_PDN_MIC_LVL_DET_MASK,
1009                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1010                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1011                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1012
1013                 msleep(cs42l42->btn_det_init_dbnce);
1014
1015                 /* Clear any button interrupts before unmasking them */
1016                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1017                             &int_status);
1018
1019                 /* Unmask button detect interrupts */
1020                 regmap_update_bits(cs42l42->regmap,
1021                         CS42L42_DET_INT2_MASK,
1022                         CS42L42_M_DETECT_TF_MASK |
1023                         CS42L42_M_DETECT_FT_MASK |
1024                         CS42L42_M_HSBIAS_HIZ_MASK |
1025                         CS42L42_M_SHORT_RLS_MASK |
1026                         CS42L42_M_SHORT_DET_MASK,
1027                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1028                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1029                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1030                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1031                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1032         } else {
1033                 /* Make sure button detect and HS bias circuits are off */
1034                 regmap_update_bits(cs42l42->regmap,
1035                         CS42L42_MISC_DET_CTL,
1036                         CS42L42_DETECT_MODE_MASK |
1037                         CS42L42_HSBIAS_CTL_MASK |
1038                         CS42L42_PDN_MIC_LVL_DET_MASK,
1039                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1040                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1041                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1042         }
1043
1044         regmap_update_bits(cs42l42->regmap,
1045                                 CS42L42_DAC_CTL2,
1046                                 CS42L42_HPOUT_PULLDOWN_MASK |
1047                                 CS42L42_HPOUT_LOAD_MASK |
1048                                 CS42L42_HPOUT_CLAMP_MASK |
1049                                 CS42L42_DAC_HPF_EN_MASK |
1050                                 CS42L42_DAC_MON_EN_MASK,
1051                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1052                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1053                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1054                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1055                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1056
1057         /* Unmask tip sense interrupts */
1058         regmap_update_bits(cs42l42->regmap,
1059                 CS42L42_TSRS_PLUG_INT_MASK,
1060                 CS42L42_RS_PLUG_MASK |
1061                 CS42L42_RS_UNPLUG_MASK |
1062                 CS42L42_TS_PLUG_MASK |
1063                 CS42L42_TS_UNPLUG_MASK,
1064                 (1 << CS42L42_RS_PLUG_SHIFT) |
1065                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1066                 (0 << CS42L42_TS_PLUG_SHIFT) |
1067                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1068 }
1069
1070 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1071 {
1072         /* Mask tip sense interrupts */
1073         regmap_update_bits(cs42l42->regmap,
1074                                 CS42L42_TSRS_PLUG_INT_MASK,
1075                                 CS42L42_RS_PLUG_MASK |
1076                                 CS42L42_RS_UNPLUG_MASK |
1077                                 CS42L42_TS_PLUG_MASK |
1078                                 CS42L42_TS_UNPLUG_MASK,
1079                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1080                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1081                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1082                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1083
1084         /* Make sure button detect and HS bias circuits are off */
1085         regmap_update_bits(cs42l42->regmap,
1086                                 CS42L42_MISC_DET_CTL,
1087                                 CS42L42_DETECT_MODE_MASK |
1088                                 CS42L42_HSBIAS_CTL_MASK |
1089                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1090                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1091                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1092                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1093
1094         /* Set auto HS bias settings to default */
1095         regmap_update_bits(cs42l42->regmap,
1096                                 CS42L42_HSBIAS_SC_AUTOCTL,
1097                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1098                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1099                                 CS42L42_TIP_SENSE_EN_MASK |
1100                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1101                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1102                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1103                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1104                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1105
1106         /* Set hs detect to manual, disabled mode */
1107         regmap_update_bits(cs42l42->regmap,
1108                                 CS42L42_HSDET_CTL2,
1109                                 CS42L42_HSDET_CTRL_MASK |
1110                                 CS42L42_HSDET_SET_MASK |
1111                                 CS42L42_HSBIAS_REF_MASK |
1112                                 CS42L42_HSDET_AUTO_TIME_MASK,
1113                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1114                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1115                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1116                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1117
1118         regmap_update_bits(cs42l42->regmap,
1119                                 CS42L42_DAC_CTL2,
1120                                 CS42L42_HPOUT_PULLDOWN_MASK |
1121                                 CS42L42_HPOUT_LOAD_MASK |
1122                                 CS42L42_HPOUT_CLAMP_MASK |
1123                                 CS42L42_DAC_HPF_EN_MASK |
1124                                 CS42L42_DAC_MON_EN_MASK,
1125                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1126                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1127                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1128                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1129                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1130
1131         /* Power up HS bias to 2.7V */
1132         regmap_update_bits(cs42l42->regmap,
1133                                 CS42L42_MISC_DET_CTL,
1134                                 CS42L42_DETECT_MODE_MASK |
1135                                 CS42L42_HSBIAS_CTL_MASK |
1136                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1137                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1138                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1139                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1140
1141         /* Wait for HS bias to ramp up */
1142         msleep(cs42l42->hs_bias_ramp_time);
1143
1144         /* Unmask auto detect interrupt */
1145         regmap_update_bits(cs42l42->regmap,
1146                                 CS42L42_CODEC_INT_MASK,
1147                                 CS42L42_PDN_DONE_MASK |
1148                                 CS42L42_HSDET_AUTO_DONE_MASK,
1149                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1150                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1151
1152         /* Set hs detect to automatic, enabled mode */
1153         regmap_update_bits(cs42l42->regmap,
1154                                 CS42L42_HSDET_CTL2,
1155                                 CS42L42_HSDET_CTRL_MASK |
1156                                 CS42L42_HSDET_SET_MASK |
1157                                 CS42L42_HSBIAS_REF_MASK |
1158                                 CS42L42_HSDET_AUTO_TIME_MASK,
1159                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1160                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1161                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1162                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1163 }
1164
1165 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1166 {
1167         /* Mask button detect interrupts */
1168         regmap_update_bits(cs42l42->regmap,
1169                 CS42L42_DET_INT2_MASK,
1170                 CS42L42_M_DETECT_TF_MASK |
1171                 CS42L42_M_DETECT_FT_MASK |
1172                 CS42L42_M_HSBIAS_HIZ_MASK |
1173                 CS42L42_M_SHORT_RLS_MASK |
1174                 CS42L42_M_SHORT_DET_MASK,
1175                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1176                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1177                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1178                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1179                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1180
1181         /* Ground HS bias */
1182         regmap_update_bits(cs42l42->regmap,
1183                                 CS42L42_MISC_DET_CTL,
1184                                 CS42L42_DETECT_MODE_MASK |
1185                                 CS42L42_HSBIAS_CTL_MASK |
1186                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1187                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1188                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1189                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1190
1191         /* Set auto HS bias settings to default */
1192         regmap_update_bits(cs42l42->regmap,
1193                                 CS42L42_HSBIAS_SC_AUTOCTL,
1194                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1195                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1196                                 CS42L42_TIP_SENSE_EN_MASK |
1197                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1198                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1199                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1200                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1201                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1202
1203         /* Set hs detect to manual, disabled mode */
1204         regmap_update_bits(cs42l42->regmap,
1205                                 CS42L42_HSDET_CTL2,
1206                                 CS42L42_HSDET_CTRL_MASK |
1207                                 CS42L42_HSDET_SET_MASK |
1208                                 CS42L42_HSBIAS_REF_MASK |
1209                                 CS42L42_HSDET_AUTO_TIME_MASK,
1210                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1211                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1212                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1213                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1214 }
1215
1216 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1217 {
1218         int bias_level;
1219         unsigned int detect_status;
1220
1221         /* Mask button detect interrupts */
1222         regmap_update_bits(cs42l42->regmap,
1223                 CS42L42_DET_INT2_MASK,
1224                 CS42L42_M_DETECT_TF_MASK |
1225                 CS42L42_M_DETECT_FT_MASK |
1226                 CS42L42_M_HSBIAS_HIZ_MASK |
1227                 CS42L42_M_SHORT_RLS_MASK |
1228                 CS42L42_M_SHORT_DET_MASK,
1229                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1230                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1231                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1232                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1233                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1234
1235         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1236                      cs42l42->btn_det_event_dbnce * 2000);
1237
1238         /* Test all 4 level detect biases */
1239         bias_level = 1;
1240         do {
1241                 /* Adjust button detect level sensitivity */
1242                 regmap_update_bits(cs42l42->regmap,
1243                         CS42L42_MIC_DET_CTL1,
1244                         CS42L42_LATCH_TO_VP_MASK |
1245                         CS42L42_EVENT_STAT_SEL_MASK |
1246                         CS42L42_HS_DET_LEVEL_MASK,
1247                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1248                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1249                         (cs42l42->bias_thresholds[bias_level] <<
1250                         CS42L42_HS_DET_LEVEL_SHIFT));
1251
1252                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1253                                 &detect_status);
1254         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1255                 (++bias_level < CS42L42_NUM_BIASES));
1256
1257         switch (bias_level) {
1258         case 1: /* Function C button press */
1259                 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1260                 break;
1261         case 2: /* Function B button press */
1262                 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1263                 break;
1264         case 3: /* Function D button press */
1265                 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1266                 break;
1267         case 4: /* Function A button press */
1268                 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1269                 break;
1270         }
1271
1272         /* Set button detect level sensitivity back to default */
1273         regmap_update_bits(cs42l42->regmap,
1274                 CS42L42_MIC_DET_CTL1,
1275                 CS42L42_LATCH_TO_VP_MASK |
1276                 CS42L42_EVENT_STAT_SEL_MASK |
1277                 CS42L42_HS_DET_LEVEL_MASK,
1278                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1279                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1280                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1281
1282         /* Clear any button interrupts before unmasking them */
1283         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1284                     &detect_status);
1285
1286         /* Unmask button detect interrupts */
1287         regmap_update_bits(cs42l42->regmap,
1288                 CS42L42_DET_INT2_MASK,
1289                 CS42L42_M_DETECT_TF_MASK |
1290                 CS42L42_M_DETECT_FT_MASK |
1291                 CS42L42_M_HSBIAS_HIZ_MASK |
1292                 CS42L42_M_SHORT_RLS_MASK |
1293                 CS42L42_M_SHORT_DET_MASK,
1294                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1295                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1296                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1297                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1298                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1299 }
1300
1301 struct cs42l42_irq_params {
1302         u16 status_addr;
1303         u16 mask_addr;
1304         u8 mask;
1305 };
1306
1307 static const struct cs42l42_irq_params irq_params_table[] = {
1308         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1309                 CS42L42_ADC_OVFL_VAL_MASK},
1310         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1311                 CS42L42_MIXER_VAL_MASK},
1312         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1313                 CS42L42_SRC_VAL_MASK},
1314         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1315                 CS42L42_ASP_RX_VAL_MASK},
1316         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1317                 CS42L42_ASP_TX_VAL_MASK},
1318         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1319                 CS42L42_CODEC_VAL_MASK},
1320         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1321                 CS42L42_DET_INT_VAL1_MASK},
1322         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1323                 CS42L42_DET_INT_VAL2_MASK},
1324         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1325                 CS42L42_SRCPL_VAL_MASK},
1326         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1327                 CS42L42_VPMON_VAL_MASK},
1328         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1329                 CS42L42_PLL_LOCK_VAL_MASK},
1330         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1331                 CS42L42_TSRS_PLUG_VAL_MASK}
1332 };
1333
1334 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1335 {
1336         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1337         struct snd_soc_component *component = cs42l42->component;
1338         unsigned int stickies[12];
1339         unsigned int masks[12];
1340         unsigned int current_plug_status;
1341         unsigned int current_button_status;
1342         unsigned int i;
1343
1344         /* Read sticky registers to clear interurpt */
1345         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1346                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1347                                 &(stickies[i]));
1348                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1349                                 &(masks[i]));
1350                 stickies[i] = stickies[i] & (~masks[i]) &
1351                                 irq_params_table[i].mask;
1352         }
1353
1354         /* Read tip sense status before handling type detect */
1355         current_plug_status = (stickies[11] &
1356                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1357                 CS42L42_TS_PLUG_SHIFT;
1358
1359         /* Read button sense status */
1360         current_button_status = stickies[7] &
1361                 (CS42L42_M_DETECT_TF_MASK |
1362                 CS42L42_M_DETECT_FT_MASK |
1363                 CS42L42_M_HSBIAS_HIZ_MASK);
1364
1365         /* Check auto-detect status */
1366         if ((~masks[5]) & irq_params_table[5].mask) {
1367                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1368                         cs42l42_process_hs_type_detect(cs42l42);
1369                         dev_dbg(component->dev,
1370                                 "Auto detect done (%d)\n",
1371                                 cs42l42->hs_type);
1372                 }
1373         }
1374
1375         /* Check tip sense status */
1376         if ((~masks[11]) & irq_params_table[11].mask) {
1377                 switch (current_plug_status) {
1378                 case CS42L42_TS_PLUG:
1379                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1380                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1381                                 cs42l42_init_hs_type_detect(cs42l42);
1382                         }
1383                         break;
1384
1385                 case CS42L42_TS_UNPLUG:
1386                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1387                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1388                                 cs42l42_cancel_hs_type_detect(cs42l42);
1389                                 dev_dbg(component->dev,
1390                                         "Unplug event\n");
1391                         }
1392                         break;
1393
1394                 default:
1395                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1396                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1397                 }
1398         }
1399
1400         /* Check button detect status */
1401         if ((~masks[7]) & irq_params_table[7].mask) {
1402                 if (!(current_button_status &
1403                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1404
1405                         if (current_button_status &
1406                                 CS42L42_M_DETECT_TF_MASK) {
1407                                 dev_dbg(component->dev,
1408                                         "Button released\n");
1409                         } else if (current_button_status &
1410                                 CS42L42_M_DETECT_FT_MASK) {
1411                                 cs42l42_handle_button_press(cs42l42);
1412                         }
1413                 }
1414         }
1415
1416         return IRQ_HANDLED;
1417 }
1418
1419 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1420 {
1421         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1422                         CS42L42_ADC_OVFL_MASK,
1423                         (1 << CS42L42_ADC_OVFL_SHIFT));
1424
1425         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1426                         CS42L42_MIX_CHB_OVFL_MASK |
1427                         CS42L42_MIX_CHA_OVFL_MASK |
1428                         CS42L42_EQ_OVFL_MASK |
1429                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1430                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1431                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1432                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1433                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1434
1435         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1436                         CS42L42_SRC_ILK_MASK |
1437                         CS42L42_SRC_OLK_MASK |
1438                         CS42L42_SRC_IUNLK_MASK |
1439                         CS42L42_SRC_OUNLK_MASK,
1440                         (1 << CS42L42_SRC_ILK_SHIFT) |
1441                         (1 << CS42L42_SRC_OLK_SHIFT) |
1442                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1443                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1444
1445         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1446                         CS42L42_ASPRX_NOLRCK_MASK |
1447                         CS42L42_ASPRX_EARLY_MASK |
1448                         CS42L42_ASPRX_LATE_MASK |
1449                         CS42L42_ASPRX_ERROR_MASK |
1450                         CS42L42_ASPRX_OVLD_MASK,
1451                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1452                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1453                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1454                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1455                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1456
1457         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1458                         CS42L42_ASPTX_NOLRCK_MASK |
1459                         CS42L42_ASPTX_EARLY_MASK |
1460                         CS42L42_ASPTX_LATE_MASK |
1461                         CS42L42_ASPTX_SMERROR_MASK,
1462                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1463                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1464                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1465                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1466
1467         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1468                         CS42L42_PDN_DONE_MASK |
1469                         CS42L42_HSDET_AUTO_DONE_MASK,
1470                         (1 << CS42L42_PDN_DONE_SHIFT) |
1471                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1472
1473         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1474                         CS42L42_SRCPL_ADC_LK_MASK |
1475                         CS42L42_SRCPL_DAC_LK_MASK |
1476                         CS42L42_SRCPL_ADC_UNLK_MASK |
1477                         CS42L42_SRCPL_DAC_UNLK_MASK,
1478                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1479                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1480                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1481                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1482
1483         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1484                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1485                         CS42L42_TIP_SENSE_PLUG_MASK |
1486                         CS42L42_HSBIAS_SENSE_MASK,
1487                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1488                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1489                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1490
1491         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1492                         CS42L42_M_DETECT_TF_MASK |
1493                         CS42L42_M_DETECT_FT_MASK |
1494                         CS42L42_M_HSBIAS_HIZ_MASK |
1495                         CS42L42_M_SHORT_RLS_MASK |
1496                         CS42L42_M_SHORT_DET_MASK,
1497                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1498                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1499                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1500                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1501                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1502
1503         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1504                         CS42L42_VPMON_MASK,
1505                         (1 << CS42L42_VPMON_SHIFT));
1506
1507         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1508                         CS42L42_PLL_LOCK_MASK,
1509                         (1 << CS42L42_PLL_LOCK_SHIFT));
1510
1511         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1512                         CS42L42_RS_PLUG_MASK |
1513                         CS42L42_RS_UNPLUG_MASK |
1514                         CS42L42_TS_PLUG_MASK |
1515                         CS42L42_TS_UNPLUG_MASK,
1516                         (1 << CS42L42_RS_PLUG_SHIFT) |
1517                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1518                         (0 << CS42L42_TS_PLUG_SHIFT) |
1519                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1520 }
1521
1522 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1523 {
1524         unsigned int reg;
1525
1526         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1527
1528         /* Latch analog controls to VP power domain */
1529         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1530                         CS42L42_LATCH_TO_VP_MASK |
1531                         CS42L42_EVENT_STAT_SEL_MASK |
1532                         CS42L42_HS_DET_LEVEL_MASK,
1533                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1534                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1535                         (cs42l42->bias_thresholds[0] <<
1536                         CS42L42_HS_DET_LEVEL_SHIFT));
1537
1538         /* Remove ground noise-suppression clamps */
1539         regmap_update_bits(cs42l42->regmap,
1540                         CS42L42_HS_CLAMP_DISABLE,
1541                         CS42L42_HS_CLAMP_DISABLE_MASK,
1542                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1543
1544         /* Enable the tip sense circuit */
1545         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1546                         CS42L42_TIP_SENSE_CTRL_MASK |
1547                         CS42L42_TIP_SENSE_INV_MASK |
1548                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1549                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1550                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1551                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1552
1553         /* Save the initial status of the tip sense */
1554         regmap_read(cs42l42->regmap,
1555                           CS42L42_TSRS_PLUG_STATUS,
1556                           &reg);
1557         cs42l42->plug_state = (((char) reg) &
1558                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1559                       CS42L42_TS_PLUG_SHIFT;
1560 }
1561
1562 static const unsigned int threshold_defaults[] = {
1563         CS42L42_HS_DET_LEVEL_15,
1564         CS42L42_HS_DET_LEVEL_8,
1565         CS42L42_HS_DET_LEVEL_4,
1566         CS42L42_HS_DET_LEVEL_1
1567 };
1568
1569 static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1570                                         struct cs42l42_private *cs42l42)
1571 {
1572         struct device_node *np = i2c_client->dev.of_node;
1573         unsigned int val;
1574         unsigned int thresholds[CS42L42_NUM_BIASES];
1575         int ret;
1576         int i;
1577
1578         ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1579
1580         if (!ret) {
1581                 switch (val) {
1582                 case CS42L42_TS_INV_EN:
1583                 case CS42L42_TS_INV_DIS:
1584                         cs42l42->ts_inv = val;
1585                         break;
1586                 default:
1587                         dev_err(&i2c_client->dev,
1588                                 "Wrong cirrus,ts-inv DT value %d\n",
1589                                 val);
1590                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1591                 }
1592         } else {
1593                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1594         }
1595
1596         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1597                         CS42L42_TS_INV_MASK,
1598                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1599
1600         ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1601
1602         if (!ret) {
1603                 switch (val) {
1604                 case CS42L42_TS_DBNCE_0:
1605                 case CS42L42_TS_DBNCE_125:
1606                 case CS42L42_TS_DBNCE_250:
1607                 case CS42L42_TS_DBNCE_500:
1608                 case CS42L42_TS_DBNCE_750:
1609                 case CS42L42_TS_DBNCE_1000:
1610                 case CS42L42_TS_DBNCE_1250:
1611                 case CS42L42_TS_DBNCE_1500:
1612                         cs42l42->ts_dbnc_rise = val;
1613                         break;
1614                 default:
1615                         dev_err(&i2c_client->dev,
1616                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1617                                 val);
1618                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1619                 }
1620         } else {
1621                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1622         }
1623
1624         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1625                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1626                         (cs42l42->ts_dbnc_rise <<
1627                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1628
1629         ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1630
1631         if (!ret) {
1632                 switch (val) {
1633                 case CS42L42_TS_DBNCE_0:
1634                 case CS42L42_TS_DBNCE_125:
1635                 case CS42L42_TS_DBNCE_250:
1636                 case CS42L42_TS_DBNCE_500:
1637                 case CS42L42_TS_DBNCE_750:
1638                 case CS42L42_TS_DBNCE_1000:
1639                 case CS42L42_TS_DBNCE_1250:
1640                 case CS42L42_TS_DBNCE_1500:
1641                         cs42l42->ts_dbnc_fall = val;
1642                         break;
1643                 default:
1644                         dev_err(&i2c_client->dev,
1645                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1646                                 val);
1647                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1648                 }
1649         } else {
1650                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1651         }
1652
1653         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1654                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1655                         (cs42l42->ts_dbnc_fall <<
1656                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1657
1658         ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1659
1660         if (!ret) {
1661                 if ((val >= CS42L42_BTN_DET_INIT_DBNCE_MIN) &&
1662                         (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX))
1663                         cs42l42->btn_det_init_dbnce = val;
1664                 else {
1665                         dev_err(&i2c_client->dev,
1666                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1667                                 val);
1668                         cs42l42->btn_det_init_dbnce =
1669                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1670                 }
1671         } else {
1672                 cs42l42->btn_det_init_dbnce =
1673                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1674         }
1675
1676         ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1677
1678         if (!ret) {
1679                 if ((val >= CS42L42_BTN_DET_EVENT_DBNCE_MIN) &&
1680                         (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX))
1681                         cs42l42->btn_det_event_dbnce = val;
1682                 else {
1683                         dev_err(&i2c_client->dev,
1684                         "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1685                         cs42l42->btn_det_event_dbnce =
1686                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1687                 }
1688         } else {
1689                 cs42l42->btn_det_event_dbnce =
1690                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1691         }
1692
1693         ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1694                                    (u32 *)thresholds, CS42L42_NUM_BIASES);
1695
1696         if (!ret) {
1697                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1698                         if ((thresholds[i] >= CS42L42_HS_DET_LEVEL_MIN) &&
1699                                 (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX))
1700                                 cs42l42->bias_thresholds[i] = thresholds[i];
1701                         else {
1702                                 dev_err(&i2c_client->dev,
1703                                 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1704                                         thresholds[i]);
1705                                 cs42l42->bias_thresholds[i] =
1706                                         threshold_defaults[i];
1707                         }
1708                 }
1709         } else {
1710                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1711                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1712         }
1713
1714         ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1715
1716         if (!ret) {
1717                 switch (val) {
1718                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1719                         cs42l42->hs_bias_ramp_rate = val;
1720                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1721                         break;
1722                 case CS42L42_HSBIAS_RAMP_FAST:
1723                         cs42l42->hs_bias_ramp_rate = val;
1724                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1725                         break;
1726                 case CS42L42_HSBIAS_RAMP_SLOW:
1727                         cs42l42->hs_bias_ramp_rate = val;
1728                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1729                         break;
1730                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1731                         cs42l42->hs_bias_ramp_rate = val;
1732                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1733                         break;
1734                 default:
1735                         dev_err(&i2c_client->dev,
1736                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1737                                 val);
1738                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1739                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1740                 }
1741         } else {
1742                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1743                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1744         }
1745
1746         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1747                         CS42L42_HSBIAS_RAMP_MASK,
1748                         (cs42l42->hs_bias_ramp_rate <<
1749                         CS42L42_HSBIAS_RAMP_SHIFT));
1750
1751         return 0;
1752 }
1753
1754 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1755                                        const struct i2c_device_id *id)
1756 {
1757         struct cs42l42_private *cs42l42;
1758         int ret, i;
1759         unsigned int devid = 0;
1760         unsigned int reg;
1761
1762         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1763                                GFP_KERNEL);
1764         if (!cs42l42)
1765                 return -ENOMEM;
1766
1767         i2c_set_clientdata(i2c_client, cs42l42);
1768
1769         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1770         if (IS_ERR(cs42l42->regmap)) {
1771                 ret = PTR_ERR(cs42l42->regmap);
1772                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1773                 return ret;
1774         }
1775
1776         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1777                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1778
1779         ret = devm_regulator_bulk_get(&i2c_client->dev,
1780                                       ARRAY_SIZE(cs42l42->supplies),
1781                                       cs42l42->supplies);
1782         if (ret != 0) {
1783                 dev_err(&i2c_client->dev,
1784                         "Failed to request supplies: %d\n", ret);
1785                 return ret;
1786         }
1787
1788         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1789                                     cs42l42->supplies);
1790         if (ret != 0) {
1791                 dev_err(&i2c_client->dev,
1792                         "Failed to enable supplies: %d\n", ret);
1793                 return ret;
1794         }
1795
1796         /* Reset the Device */
1797         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1798                 "reset", GPIOD_OUT_LOW);
1799         if (IS_ERR(cs42l42->reset_gpio))
1800                 return PTR_ERR(cs42l42->reset_gpio);
1801
1802         if (cs42l42->reset_gpio) {
1803                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1804                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1805         }
1806         mdelay(3);
1807
1808         /* Request IRQ */
1809         ret = devm_request_threaded_irq(&i2c_client->dev,
1810                         i2c_client->irq,
1811                         NULL, cs42l42_irq_thread,
1812                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1813                         "cs42l42", cs42l42);
1814
1815         if (ret != 0)
1816                 dev_err(&i2c_client->dev,
1817                         "Failed to request IRQ: %d\n", ret);
1818
1819         /* initialize codec */
1820         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
1821         devid = (reg & 0xFF) << 12;
1822
1823         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
1824         devid |= (reg & 0xFF) << 4;
1825
1826         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
1827         devid |= (reg & 0xF0) >> 4;
1828
1829         if (devid != CS42L42_CHIP_ID) {
1830                 ret = -ENODEV;
1831                 dev_err(&i2c_client->dev,
1832                         "CS42L42 Device ID (%X). Expected %X\n",
1833                         devid, CS42L42_CHIP_ID);
1834                 return ret;
1835         }
1836
1837         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1838         if (ret < 0) {
1839                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1840                 return ret;
1841         }
1842
1843         dev_info(&i2c_client->dev,
1844                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1845
1846         /* Power up the codec */
1847         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1848                         CS42L42_ASP_DAO_PDN_MASK |
1849                         CS42L42_ASP_DAI_PDN_MASK |
1850                         CS42L42_MIXER_PDN_MASK |
1851                         CS42L42_EQ_PDN_MASK |
1852                         CS42L42_HP_PDN_MASK |
1853                         CS42L42_ADC_PDN_MASK |
1854                         CS42L42_PDN_ALL_MASK,
1855                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1856                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1857                         (1 << CS42L42_MIXER_PDN_SHIFT) |
1858                         (1 << CS42L42_EQ_PDN_SHIFT) |
1859                         (1 << CS42L42_HP_PDN_SHIFT) |
1860                         (1 << CS42L42_ADC_PDN_SHIFT) |
1861                         (0 << CS42L42_PDN_ALL_SHIFT));
1862
1863         if (i2c_client->dev.of_node) {
1864                 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1865                 if (ret != 0)
1866                         return ret;
1867         }
1868
1869         /* Setup headset detection */
1870         cs42l42_setup_hs_type_detect(cs42l42);
1871
1872         /* Mask/Unmask Interrupts */
1873         cs42l42_set_interrupt_masks(cs42l42);
1874
1875         /* Register codec for machine driver */
1876         ret = devm_snd_soc_register_component(&i2c_client->dev,
1877                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1878         if (ret < 0)
1879                 goto err_disable;
1880         return 0;
1881
1882 err_disable:
1883         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1884                                 cs42l42->supplies);
1885         return ret;
1886 }
1887
1888 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1889 {
1890         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1891
1892         /* Hold down reset */
1893         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1894
1895         return 0;
1896 }
1897
1898 #ifdef CONFIG_PM
1899 static int cs42l42_runtime_suspend(struct device *dev)
1900 {
1901         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1902
1903         regcache_cache_only(cs42l42->regmap, true);
1904         regcache_mark_dirty(cs42l42->regmap);
1905
1906         /* Hold down reset */
1907         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1908
1909         /* remove power */
1910         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1911                                 cs42l42->supplies);
1912
1913         return 0;
1914 }
1915
1916 static int cs42l42_runtime_resume(struct device *dev)
1917 {
1918         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1919         int ret;
1920
1921         /* Enable power */
1922         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1923                                         cs42l42->supplies);
1924         if (ret != 0) {
1925                 dev_err(dev, "Failed to enable supplies: %d\n",
1926                         ret);
1927                 return ret;
1928         }
1929
1930         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1931
1932         regcache_cache_only(cs42l42->regmap, false);
1933         regcache_sync(cs42l42->regmap);
1934
1935         return 0;
1936 }
1937 #endif
1938
1939 static const struct dev_pm_ops cs42l42_runtime_pm = {
1940         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1941                            NULL)
1942 };
1943
1944 static const struct of_device_id cs42l42_of_match[] = {
1945         { .compatible = "cirrus,cs42l42", },
1946         {},
1947 };
1948 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1949
1950
1951 static const struct i2c_device_id cs42l42_id[] = {
1952         {"cs42l42", 0},
1953         {}
1954 };
1955
1956 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1957
1958 static struct i2c_driver cs42l42_i2c_driver = {
1959         .driver = {
1960                 .name = "cs42l42",
1961                 .pm = &cs42l42_runtime_pm,
1962                 .of_match_table = cs42l42_of_match,
1963                 },
1964         .id_table = cs42l42_id,
1965         .probe = cs42l42_i2c_probe,
1966         .remove = cs42l42_i2c_remove,
1967 };
1968
1969 module_i2c_driver(cs42l42_i2c_driver);
1970
1971 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1972 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1973 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1974 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1975 MODULE_LICENSE("GPL");