sound/soc/codecs/max98373.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/delay.h>
   6 #include <linux/i2c.h>
   7 #include <linux/module.h>
   8 #include <linux/regmap.h>
   9 #include <linux/slab.h>
  10 #include <linux/cdev.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <linux/gpio.h>
  15 #include <linux/of_gpio.h>
  16 #include <sound/tlv.h>
  17 #include "max98373.h"
  18
  19 static struct reg_default max98373_reg[] = {
  20         {MAX98373_R2000_SW_RESET, 0x00},
  21         {MAX98373_R2001_INT_RAW1, 0x00},
  22         {MAX98373_R2002_INT_RAW2, 0x00},
  23         {MAX98373_R2003_INT_RAW3, 0x00},
  24         {MAX98373_R2004_INT_STATE1, 0x00},
  25         {MAX98373_R2005_INT_STATE2, 0x00},
  26         {MAX98373_R2006_INT_STATE3, 0x00},
  27         {MAX98373_R2007_INT_FLAG1, 0x00},
  28         {MAX98373_R2008_INT_FLAG2, 0x00},
  29         {MAX98373_R2009_INT_FLAG3, 0x00},
  30         {MAX98373_R200A_INT_EN1, 0x00},
  31         {MAX98373_R200B_INT_EN2, 0x00},
  32         {MAX98373_R200C_INT_EN3, 0x00},
  33         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  34         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  35         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  36         {MAX98373_R2010_IRQ_CTRL, 0x00},
  37         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  38         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
  39         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
  40         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
  41         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
  42         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
  43         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
  44         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
  45         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
  46         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
  47         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
  48         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
  49         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
  50         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
  51         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
  52         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
  53         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
  54         {MAX98373_R202B_PCM_RX_EN, 0x00},
  55         {MAX98373_R202C_PCM_TX_EN, 0x00},
  56         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
  57         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
  58         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
  59         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
  60         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
  61         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
  62         {MAX98373_R2035_ICC_TX_EN, 0x00},
  63         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
  64         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
  65         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
  66         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
  67         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
  68         {MAX98373_R2041_AMP_CFG, 0x03},
  69         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
  70         {MAX98373_R2043_AMP_EN, 0x00},
  71         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
  72         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
  73         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
  74         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
  75         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
  76         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
  77         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
  78         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
  79         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
  80         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
  81         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
  82         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
  83         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
  84         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
  85         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
  86         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
  87         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
  88         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
  89         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
  90         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
  91         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
  92         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
  93         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
  94         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
  95         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
  96         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
  97         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
  98         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
  99         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
 100         {MAX98373_R20B5_BDE_EN, 0x00},
 101         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 102         {MAX98373_R20D1_DHT_CFG, 0x01},
 103         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 104         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 105         {MAX98373_R20D4_DHT_EN, 0x00},
 106         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 107         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 108         {MAX98373_R20E2_LIMITER_EN, 0x00},
 109         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 110         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 111         {MAX98373_R21FF_REV_ID, 0x42},
 112 };
 113
 114 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 115 {
 116         struct snd_soc_component *component = codec_dai->component;
 117         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 118         unsigned int format = 0;
 119         unsigned int invert = 0;
 120
 121         dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
 122
 123         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 124         case SND_SOC_DAIFMT_NB_NF:
 125                 break;
 126         case SND_SOC_DAIFMT_IB_NF:
 127                 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
 128                 break;
 129         default:
 130                 dev_err(component->dev, "DAI invert mode unsupported\n");
 131                 return -EINVAL;
 132         }
 133
 134         regmap_update_bits(max98373->regmap,
 135                 MAX98373_R2026_PCM_CLOCK_RATIO,
 136                 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
 137                 invert);
 138
 139         /* interface format */
 140         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 141         case SND_SOC_DAIFMT_I2S:
 142                 format = MAX98373_PCM_FORMAT_I2S;
 143                 break;
 144         case SND_SOC_DAIFMT_LEFT_J:
 145                 format = MAX98373_PCM_FORMAT_LJ;
 146                 break;
 147         case SND_SOC_DAIFMT_DSP_A:
 148                 format = MAX98373_PCM_FORMAT_TDM_MODE1;
 149                 break;
 150         case SND_SOC_DAIFMT_DSP_B:
 151                 format = MAX98373_PCM_FORMAT_TDM_MODE0;
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156
 157         regmap_update_bits(max98373->regmap,
 158                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 159                 MAX98373_PCM_MODE_CFG_FORMAT_MASK,
 160                 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
 161
 162         return 0;
 163 }
 164
 165 /* BCLKs per LRCLK */
 166 static const int bclk_sel_table[] = {
 167         32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
 168 };
 169
 170 static int max98373_get_bclk_sel(int bclk)
 171 {
 172         int i;
 173         /* match BCLKs per LRCLK */
 174         for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
 175                 if (bclk_sel_table[i] == bclk)
 176                         return i + 2;
 177         }
 178         return 0;
 179 }
 180
 181 static int max98373_set_clock(struct snd_soc_component *component,
 182         struct snd_pcm_hw_params *params)
 183 {
 184         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 185         /* BCLK/LRCLK ratio calculation */
 186         int blr_clk_ratio = params_channels(params) * max98373->ch_size;
 187         int value;
 188
 189         if (!max98373->tdm_mode) {
 190                 /* BCLK configuration */
 191                 value = max98373_get_bclk_sel(blr_clk_ratio);
 192                 if (!value) {
 193                         dev_err(component->dev, "format unsupported %d\n",
 194                                 params_format(params));
 195                         return -EINVAL;
 196                 }
 197
 198                 regmap_update_bits(max98373->regmap,
 199                         MAX98373_R2026_PCM_CLOCK_RATIO,
 200                         MAX98373_PCM_CLK_SETUP_BSEL_MASK,
 201                         value);
 202         }
 203         return 0;
 204 }
 205
 206 static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
 207         struct snd_pcm_hw_params *params,
 208         struct snd_soc_dai *dai)
 209 {
 210         struct snd_soc_component *component = dai->component;
 211         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 212         unsigned int sampling_rate = 0;
 213         unsigned int chan_sz = 0;
 214
 215         /* pcm mode configuration */
 216         switch (snd_pcm_format_width(params_format(params))) {
 217         case 16:
 218                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 219                 break;
 220         case 24:
 221                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 222                 break;
 223         case 32:
 224                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 225                 break;
 226         default:
 227                 dev_err(component->dev, "format unsupported %d\n",
 228                         params_format(params));
 229                 goto err;
 230         }
 231
 232         max98373->ch_size = snd_pcm_format_width(params_format(params));
 233
 234         regmap_update_bits(max98373->regmap,
 235                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 236                 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 237
 238         dev_dbg(component->dev, "format supported %d",
 239                 params_format(params));
 240
 241         /* sampling rate configuration */
 242         switch (params_rate(params)) {
 243         case 8000:
 244                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 245                 break;
 246         case 11025:
 247                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 248                 break;
 249         case 12000:
 250                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 251                 break;
 252         case 16000:
 253                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 254                 break;
 255         case 22050:
 256                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 257                 break;
 258         case 24000:
 259                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 260                 break;
 261         case 32000:
 262                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 263                 break;
 264         case 44100:
 265                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 266                 break;
 267         case 48000:
 268                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 269                 break;
 270         default:
 271                 dev_err(component->dev, "rate %d not supported\n",
 272                         params_rate(params));
 273                 goto err;
 274         }
 275
 276         /* set DAI_SR to correct LRCLK frequency */
 277         regmap_update_bits(max98373->regmap,
 278                 MAX98373_R2027_PCM_SR_SETUP_1,
 279                 MAX98373_PCM_SR_SET1_SR_MASK,
 280                 sampling_rate);
 281         regmap_update_bits(max98373->regmap,
 282                 MAX98373_R2028_PCM_SR_SETUP_2,
 283                 MAX98373_PCM_SR_SET2_SR_MASK,
 284                 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 285
 286         /* set sampling rate of IV */
 287         if (max98373->interleave_mode &&
 288             sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
 289                 regmap_update_bits(max98373->regmap,
 290                         MAX98373_R2028_PCM_SR_SETUP_2,
 291                         MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 292                         sampling_rate - 3);
 293         else
 294                 regmap_update_bits(max98373->regmap,
 295                         MAX98373_R2028_PCM_SR_SETUP_2,
 296                         MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 297                         sampling_rate);
 298
 299         return max98373_set_clock(component, params);
 300 err:
 301         return -EINVAL;
 302 }
 303
 304 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
 305         unsigned int tx_mask, unsigned int rx_mask,
 306         int slots, int slot_width)
 307 {
 308         struct snd_soc_component *component = dai->component;
 309         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 310         int bsel = 0;
 311         unsigned int chan_sz = 0;
 312         unsigned int mask;
 313         int x, slot_found;
 314
 315         if (!tx_mask && !rx_mask && !slots && !slot_width)
 316                 max98373->tdm_mode = false;
 317         else
 318                 max98373->tdm_mode = true;
 319
 320         /* BCLK configuration */
 321         bsel = max98373_get_bclk_sel(slots * slot_width);
 322         if (bsel == 0) {
 323                 dev_err(component->dev, "BCLK %d not supported\n",
 324                         slots * slot_width);
 325                 return -EINVAL;
 326         }
 327
 328         regmap_update_bits(max98373->regmap,
 329                 MAX98373_R2026_PCM_CLOCK_RATIO,
 330                 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
 331                 bsel);
 332
 333         /* Channel size configuration */
 334         switch (slot_width) {
 335         case 16:
 336                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 337                 break;
 338         case 24:
 339                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 340                 break;
 341         case 32:
 342                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 343                 break;
 344         default:
 345                 dev_err(component->dev, "format unsupported %d\n",
 346                         slot_width);
 347                 return -EINVAL;
 348         }
 349
 350         regmap_update_bits(max98373->regmap,
 351                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 352                 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 353
 354         /* Rx slot configuration */
 355         slot_found = 0;
 356         mask = rx_mask;
 357         for (x = 0 ; x < 16 ; x++, mask >>= 1) {
 358                 if (mask & 0x1) {
 359                         if (slot_found == 0)
 360                                 regmap_update_bits(max98373->regmap,
 361                                         MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 362                                         MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
 363                         else
 364                                 regmap_write(max98373->regmap,
 365                                         MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 366                                         x);
 367                         slot_found++;
 368                         if (slot_found > 1)
 369                                 break;
 370                 }
 371         }
 372
 373         /* Tx slot Hi-Z configuration */
 374         regmap_write(max98373->regmap,
 375                 MAX98373_R2020_PCM_TX_HIZ_EN_1,
 376                 ~tx_mask & 0xFF);
 377         regmap_write(max98373->regmap,
 378                 MAX98373_R2021_PCM_TX_HIZ_EN_2,
 379                 (~tx_mask & 0xFF00) >> 8);
 380
 381         return 0;
 382 }
 383
 384 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 385
 386 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 387         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 388
 389 static const struct snd_soc_dai_ops max98373_dai_ops = {
 390         .set_fmt = max98373_dai_set_fmt,
 391         .hw_params = max98373_dai_hw_params,
 392         .set_tdm_slot = max98373_dai_tdm_slot,
 393 };
 394
 395 static int max98373_dac_event(struct snd_soc_dapm_widget *w,
 396         struct snd_kcontrol *kcontrol, int event)
 397 {
 398         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 399         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 400
 401         switch (event) {
 402         case SND_SOC_DAPM_POST_PMU:
 403                 regmap_update_bits(max98373->regmap,
 404                         MAX98373_R20FF_GLOBAL_SHDN,
 405                         MAX98373_GLOBAL_EN_MASK, 1);
 406                 break;
 407         case SND_SOC_DAPM_POST_PMD:
 408                 regmap_update_bits(max98373->regmap,
 409                         MAX98373_R20FF_GLOBAL_SHDN,
 410                         MAX98373_GLOBAL_EN_MASK, 0);
 411                 max98373->tdm_mode = false;
 412                 break;
 413         default:
 414                 return 0;
 415         }
 416         return 0;
 417 }
 418
 419 static const char * const max98373_switch_text[] = {
 420         "Left", "Right", "LeftRight"};
 421
 422 static const struct soc_enum dai_sel_enum =
 423         SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 424                 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
 425                 3, max98373_switch_text);
 426
 427 static const struct snd_kcontrol_new max98373_dai_controls =
 428         SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
 429
 430 static const struct snd_kcontrol_new max98373_vi_control =
 431         SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
 432
 433 static const struct snd_kcontrol_new max98373_spkfb_control =
 434         SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
 435
 436 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
 437 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
 438         MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
 439         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 440 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
 441         &max98373_dai_controls),
 442 SND_SOC_DAPM_OUTPUT("BE_OUT"),
 443 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
 444         MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
 445 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
 446         MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
 447 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
 448         SND_SOC_NOPM, 0, 0),
 449 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
 450         &max98373_vi_control),
 451 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
 452         &max98373_spkfb_control),
 453 SND_SOC_DAPM_SIGGEN("VMON"),
 454 SND_SOC_DAPM_SIGGEN("IMON"),
 455 SND_SOC_DAPM_SIGGEN("FBMON"),
 456 };
 457
 458 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
 459 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
 460         0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
 461         9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
 462 );
 463 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
 464         0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
 465 );
 466 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
 467         0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
 468         2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
 469 );
 470 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
 471         0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
 472 );
 473 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
 474         0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
 475         2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
 476         5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
 477         7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
 478         10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
 479         14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
 480 );
 481 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
 482         0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
 483 );
 484
 485 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
 486         0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
 487 );
 488
 489 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 490 {
 491         switch (reg) {
 492         case MAX98373_R2000_SW_RESET:
 493         case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
 494         case MAX98373_R2010_IRQ_CTRL:
 495         case MAX98373_R2014_THERM_WARN_THRESH
 496                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 497         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 498                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 499         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 500         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 501                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 502         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 503                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 504         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 505         case MAX98373_R2097_BDE_L1_THRESH
 506                 ... MAX98373_R209B_BDE_THRESH_HYST:
 507         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 508         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 509         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 510         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 511         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 512                 ... MAX98373_R20FF_GLOBAL_SHDN:
 513         case MAX98373_R21FF_REV_ID:
 514                 return true;
 515         default:
 516                 return false;
 517         }
 518 };
 519
 520 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 521 {
 522         switch (reg) {
 523         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 524         case MAX98373_R203E_AMP_PATH_GAIN:
 525         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 526         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 527         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 528         case MAX98373_R21FF_REV_ID:
 529                 return true;
 530         default:
 531                 return false;
 532         }
 533 }
 534
 535 static const char * const max98373_output_voltage_lvl_text[] = {
 536         "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
 537         "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
 538 };
 539
 540 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
 541                             MAX98373_R203E_AMP_PATH_GAIN, 0,
 542                             max98373_output_voltage_lvl_text);
 543
 544 static const char * const max98373_dht_attack_rate_text[] = {
 545         "17.5us", "35us", "70us", "140us",
 546         "280us", "560us", "1120us", "2240us"
 547 };
 548
 549 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
 550                             MAX98373_R20D2_DHT_ATTACK_CFG, 0,
 551                             max98373_dht_attack_rate_text);
 552
 553 static const char * const max98373_dht_release_rate_text[] = {
 554         "45ms", "225ms", "450ms", "1150ms",
 555         "2250ms", "3100ms", "4500ms", "6750ms"
 556 };
 557
 558 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
 559                             MAX98373_R20D3_DHT_RELEASE_CFG, 0,
 560                             max98373_dht_release_rate_text);
 561
 562 static const char * const max98373_limiter_attack_rate_text[] = {
 563         "10us", "20us", "40us", "80us",
 564         "160us", "320us", "640us", "1.28ms",
 565         "2.56ms", "5.12ms", "10.24ms", "20.48ms",
 566         "40.96ms", "81.92ms", "16.384ms", "32.768ms"
 567 };
 568
 569 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
 570                             MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
 571                             max98373_limiter_attack_rate_text);
 572
 573 static const char * const max98373_limiter_release_rate_text[] = {
 574         "40us", "80us", "160us", "320us",
 575         "640us", "1.28ms", "2.56ms", "5.120ms",
 576         "10.24ms", "20.48ms", "40.96ms", "81.92ms",
 577         "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
 578 };
 579
 580 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
 581                             MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
 582                             max98373_limiter_release_rate_text);
 583
 584 static const char * const max98373_ADC_samplerate_text[] = {
 585         "333kHz", "192kHz", "64kHz", "48kHz"
 586 };
 587
 588 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
 589                             MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
 590                             max98373_ADC_samplerate_text);
 591
 592 static const struct snd_kcontrol_new max98373_snd_controls[] = {
 593 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
 594         MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
 595 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
 596         MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
 597 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
 598         MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
 599 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
 600         MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
 601 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
 602         MAX98373_CLOCK_MON_SHIFT, 1, 0),
 603 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
 604         MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
 605 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
 606         MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
 607 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
 608         0, 0x7F, 1, max98373_digital_tlv),
 609 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
 610         MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
 611 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
 612         MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
 613 SOC_ENUM("Output Voltage", max98373_out_volt_enum),
 614 /* Dynamic Headroom Tracking */
 615 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
 616         MAX98373_DHT_EN_SHIFT, 1, 0),
 617 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
 618         MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
 619 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
 620         MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
 621 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
 622         MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
 623 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
 624         MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
 625 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
 626 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
 627 /* ADC configuration */
 628 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
 629 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
 630         MAX98373_FLT_EN_SHIFT, 1, 0),
 631 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
 632         MAX98373_FLT_EN_SHIFT, 1, 0),
 633 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
 634 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
 635 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
 636         0, 0x3, 0),
 637 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
 638         0, 0x3, 0),
 639 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
 640 /* Brownout Detection Engine */
 641 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
 642 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
 643         MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
 644 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
 645         MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
 646 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
 647 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
 648 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
 649 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
 650 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
 651 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
 652 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
 653 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
 654 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
 655 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
 656 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
 657         0, 0x3C, 1, max98373_bde_gain_tlv),
 658 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
 659         0, 0x3C, 1, max98373_bde_gain_tlv),
 660 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
 661         0, 0x3C, 1, max98373_bde_gain_tlv),
 662 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
 663         0, 0x3C, 1, max98373_bde_gain_tlv),
 664 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
 665         0, 0x3C, 1, max98373_bde_gain_tlv),
 666 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
 667         0, 0x3C, 1, max98373_bde_gain_tlv),
 668 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
 669         0, 0x3C, 1, max98373_bde_gain_tlv),
 670 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
 671         0, 0x3C, 1, max98373_bde_gain_tlv),
 672 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
 673         0, 0xF, 1, max98373_limiter_thresh_tlv),
 674 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
 675         0, 0xF, 1, max98373_limiter_thresh_tlv),
 676 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
 677         0, 0xF, 1, max98373_limiter_thresh_tlv),
 678 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
 679         0, 0xF, 1, max98373_limiter_thresh_tlv),
 680 /* Limiter */
 681 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
 682         MAX98373_LIMITER_EN_SHIFT, 1, 0),
 683 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
 684         MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
 685 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
 686         MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
 687 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
 688 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
 689 };
 690
 691 static const struct snd_soc_dapm_route max98373_audio_map[] = {
 692         /* Plabyack */
 693         {"DAI Sel Mux", "Left", "Amp Enable"},
 694         {"DAI Sel Mux", "Right", "Amp Enable"},
 695         {"DAI Sel Mux", "LeftRight", "Amp Enable"},
 696         {"BE_OUT", NULL, "DAI Sel Mux"},
 697         /* Capture */
 698         { "VI Sense", "Switch", "VMON" },
 699         { "VI Sense", "Switch", "IMON" },
 700         { "SpkFB Sense", "Switch", "FBMON" },
 701         { "Voltage Sense", NULL, "VI Sense" },
 702         { "Current Sense", NULL, "VI Sense" },
 703         { "Speaker FB Sense", NULL, "SpkFB Sense" },
 704 };
 705
 706 static struct snd_soc_dai_driver max98373_dai[] = {
 707         {
 708                 .name = "max98373-aif1",
 709                 .playback = {
 710                         .stream_name = "HiFi Playback",
 711                         .channels_min = 1,
 712                         .channels_max = 2,
 713                         .rates = MAX98373_RATES,
 714                         .formats = MAX98373_FORMATS,
 715                 },
 716                 .capture = {
 717                         .stream_name = "HiFi Capture",
 718                         .channels_min = 1,
 719                         .channels_max = 2,
 720                         .rates = MAX98373_RATES,
 721                         .formats = MAX98373_FORMATS,
 722                 },
 723                 .ops = &max98373_dai_ops,
 724         }
 725 };
 726
 727 static void max98373_reset(struct max98373_priv *max98373, struct device *dev)
 728 {
 729         int ret, reg, count;
 730
 731         /* Software Reset */
 732         ret = regmap_update_bits(max98373->regmap,
 733                 MAX98373_R2000_SW_RESET,
 734                 MAX98373_SOFT_RESET,
 735                 MAX98373_SOFT_RESET);
 736         if (ret)
 737                 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
 738
 739         count = 0;
 740         while (count < 3) {
 741                 usleep_range(10000, 11000);
 742                 /* Software Reset Verification */
 743                 ret = regmap_read(max98373->regmap,
 744                         MAX98373_R21FF_REV_ID, &reg);
 745                 if (!ret) {
 746                         dev_info(dev, "Reset completed (retry:%d)\n", count);
 747                         return;
 748                 }
 749                 count++;
 750         }
 751         dev_err(dev, "Reset failed. (ret:%d)\n", ret);
 752 }
 753
 754 static int max98373_probe(struct snd_soc_component *component)
 755 {
 756         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 757
 758         /* Software Reset */
 759         max98373_reset(max98373, component->dev);
 760
 761         /* IV default slot configuration */
 762         regmap_write(max98373->regmap,
 763                 MAX98373_R2020_PCM_TX_HIZ_EN_1,
 764                 0xFF);
 765         regmap_write(max98373->regmap,
 766                 MAX98373_R2021_PCM_TX_HIZ_EN_2,
 767                 0xFF);
 768         /* L/R mix configuration */
 769         regmap_write(max98373->regmap,
 770                 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 771                 0x80);
 772         regmap_write(max98373->regmap,
 773                 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 774                 0x1);
 775         /* Set inital volume (0dB) */
 776         regmap_write(max98373->regmap,
 777                 MAX98373_R203D_AMP_DIG_VOL_CTRL,
 778                 0x00);
 779         regmap_write(max98373->regmap,
 780                 MAX98373_R203E_AMP_PATH_GAIN,
 781                 0x00);
 782         /* Enable DC blocker */
 783         regmap_write(max98373->regmap,
 784                 MAX98373_R203F_AMP_DSP_CFG,
 785                 0x3);
 786         /* Enable IMON VMON DC blocker */
 787         regmap_write(max98373->regmap,
 788                 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 789                 0x7);
 790         /* voltage, current slot configuration */
 791         regmap_write(max98373->regmap,
 792                 MAX98373_R2022_PCM_TX_SRC_1,
 793                 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 794                 max98373->v_slot) & 0xFF);
 795         if (max98373->v_slot < 8)
 796                 regmap_update_bits(max98373->regmap,
 797                         MAX98373_R2020_PCM_TX_HIZ_EN_1,
 798                         1 << max98373->v_slot, 0);
 799         else
 800                 regmap_update_bits(max98373->regmap,
 801                         MAX98373_R2021_PCM_TX_HIZ_EN_2,
 802                         1 << (max98373->v_slot - 8), 0);
 803
 804         if (max98373->i_slot < 8)
 805                 regmap_update_bits(max98373->regmap,
 806                         MAX98373_R2020_PCM_TX_HIZ_EN_1,
 807                         1 << max98373->i_slot, 0);
 808         else
 809                 regmap_update_bits(max98373->regmap,
 810                         MAX98373_R2021_PCM_TX_HIZ_EN_2,
 811                         1 << (max98373->i_slot - 8), 0);
 812
 813         /* speaker feedback slot configuration */
 814         regmap_write(max98373->regmap,
 815                 MAX98373_R2023_PCM_TX_SRC_2,
 816                 max98373->spkfb_slot & 0xFF);
 817
 818         /* Set interleave mode */
 819         if (max98373->interleave_mode)
 820                 regmap_update_bits(max98373->regmap,
 821                         MAX98373_R2024_PCM_DATA_FMT_CFG,
 822                         MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 823                         MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 824
 825         /* Speaker enable */
 826         regmap_update_bits(max98373->regmap,
 827                 MAX98373_R2043_AMP_EN,
 828                 MAX98373_SPK_EN_MASK, 1);
 829
 830         return 0;
 831 }
 832
 833 #ifdef CONFIG_PM_SLEEP
 834 static int max98373_suspend(struct device *dev)
 835 {
 836         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 837
 838         regcache_cache_only(max98373->regmap, true);
 839         regcache_mark_dirty(max98373->regmap);
 840         return 0;
 841 }
 842 static int max98373_resume(struct device *dev)
 843 {
 844         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 845
 846         max98373_reset(max98373, dev);
 847         regcache_cache_only(max98373->regmap, false);
 848         regcache_sync(max98373->regmap);
 849         return 0;
 850 }
 851 #endif
 852
 853 static const struct dev_pm_ops max98373_pm = {
 854         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 855 };
 856
 857 static const struct snd_soc_component_driver soc_codec_dev_max98373 = {
 858         .probe                  = max98373_probe,
 859         .controls               = max98373_snd_controls,
 860         .num_controls           = ARRAY_SIZE(max98373_snd_controls),
 861         .dapm_widgets           = max98373_dapm_widgets,
 862         .num_dapm_widgets       = ARRAY_SIZE(max98373_dapm_widgets),
 863         .dapm_routes            = max98373_audio_map,
 864         .num_dapm_routes        = ARRAY_SIZE(max98373_audio_map),
 865         .idle_bias_on           = 1,
 866         .use_pmdown_time        = 1,
 867         .endianness             = 1,
 868         .non_legacy_dai_naming  = 1,
 869 };
 870
 871 static const struct regmap_config max98373_regmap = {
 872         .reg_bits = 16,
 873         .val_bits = 8,
 874         .max_register = MAX98373_R21FF_REV_ID,
 875         .reg_defaults  = max98373_reg,
 876         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 877         .readable_reg = max98373_readable_register,
 878         .volatile_reg = max98373_volatile_reg,
 879         .cache_type = REGCACHE_RBTREE,
 880 };
 881
 882 static void max98373_slot_config(struct i2c_client *i2c,
 883         struct max98373_priv *max98373)
 884 {
 885         int value;
 886         struct device *dev = &i2c->dev;
 887
 888         if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
 889                 max98373->v_slot = value & 0xF;
 890         else
 891                 max98373->v_slot = 0;
 892
 893         if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
 894                 max98373->i_slot = value & 0xF;
 895         else
 896                 max98373->i_slot = 1;
 897
 898         if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
 899                 max98373->spkfb_slot = value & 0xF;
 900         else
 901                 max98373->spkfb_slot = 2;
 902 }
 903
 904 static int max98373_i2c_probe(struct i2c_client *i2c,
 905         const struct i2c_device_id *id)
 906 {
 907
 908         int ret = 0;
 909         int reg = 0;
 910         struct max98373_priv *max98373 = NULL;
 911
 912         max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
 913
 914         if (!max98373) {
 915                 ret = -ENOMEM;
 916                 return ret;
 917         }
 918         i2c_set_clientdata(i2c, max98373);
 919
 920         /* update interleave mode info */
 921         if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
 922                 max98373->interleave_mode = true;
 923         else
 924                 max98373->interleave_mode = false;
 925
 926
 927         /* regmap initialization */
 928         max98373->regmap
 929                 = devm_regmap_init_i2c(i2c, &max98373_regmap);
 930         if (IS_ERR(max98373->regmap)) {
 931                 ret = PTR_ERR(max98373->regmap);
 932                 dev_err(&i2c->dev,
 933                         "Failed to allocate regmap: %d\n", ret);
 934                 return ret;
 935         }
 936
 937         /* Check Revision ID */
 938         ret = regmap_read(max98373->regmap,
 939                 MAX98373_R21FF_REV_ID, &reg);
 940         if (ret < 0) {
 941                 dev_err(&i2c->dev,
 942                         "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
 943                 return ret;
 944         }
 945         dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
 946
 947         /* voltage/current slot configuration */
 948         max98373_slot_config(i2c, max98373);
 949
 950         /* codec registeration */
 951         ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
 952                 max98373_dai, ARRAY_SIZE(max98373_dai));
 953         if (ret < 0)
 954                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
 955
 956         return ret;
 957 }
 958
 959 static const struct i2c_device_id max98373_i2c_id[] = {
 960         { "max98373", 0},
 961         { },
 962 };
 963
 964 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
 965
 966 #if defined(CONFIG_OF)
 967 static const struct of_device_id max98373_of_match[] = {
 968         { .compatible = "maxim,max98373", },
 969         { }
 970 };
 971 MODULE_DEVICE_TABLE(of, max98373_of_match);
 972 #endif
 973
 974 #ifdef CONFIG_ACPI
 975 static const struct acpi_device_id max98373_acpi_match[] = {
 976         { "MX98373", 0 },
 977         {},
 978 };
 979 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 980 #endif
 981
 982 static struct i2c_driver max98373_i2c_driver = {
 983         .driver = {
 984                 .name = "max98373",
 985                 .of_match_table = of_match_ptr(max98373_of_match),
 986                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 987                 .pm = &max98373_pm,
 988         },
 989         .probe = max98373_i2c_probe,
 990         .id_table = max98373_i2c_id,
 991 };
 992
 993 module_i2c_driver(max98373_i2c_driver)
 994
 995 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
 996 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
 997 MODULE_LICENSE("GPL");