1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
8 #include <linux/platform_device.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/sched.h>
14 #include <linux/mfd/mt6397/core.h>
15 #include <linux/regulator/consumer.h>
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
23 AUDIO_ANALOG_VOLUME_HSOUTL,
24 AUDIO_ANALOG_VOLUME_HSOUTR,
25 AUDIO_ANALOG_VOLUME_HPOUTL,
26 AUDIO_ANALOG_VOLUME_HPOUTR,
27 AUDIO_ANALOG_VOLUME_LINEOUTL,
28 AUDIO_ANALOG_VOLUME_LINEOUTR,
29 AUDIO_ANALOG_VOLUME_MICAMP1,
30 AUDIO_ANALOG_VOLUME_MICAMP2,
31 AUDIO_ANALOG_VOLUME_TYPE_MAX
54 /* Supply widget subseq */
60 SUPPLY_SEQ_VOW_AUD_LPW,
65 SUPPLY_SEQ_TOP_CK_LAST,
67 SUPPLY_SEQ_AUD_TOP_LAST,
70 SUPPLY_SEQ_ADC_SUPPLY,
83 struct regmap *regmap;
88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
89 unsigned int mux_select[MUX_NUM];
91 int dev_counter[DEVICE_NUM];
95 struct regulator *avdd_reg;
98 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
101 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
103 priv->mtkaif_protocol = mtkaif_protocol;
107 static void playback_gpio_set(struct mt6358_priv *priv)
109 /* set gpio mosi mode */
110 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
112 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
118 static void playback_gpio_reset(struct mt6358_priv *priv)
120 /* set pad_aud_*_mosi to GPIO mode and dir input
122 * pad_aud_dat_mosi*, because the pin is used as boot strap
123 * don't clean clk/sync, for mtkaif protocol 2
125 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
127 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
129 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
133 static void capture_gpio_set(struct mt6358_priv *priv)
135 /* set gpio miso mode */
136 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
138 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
144 static void capture_gpio_reset(struct mt6358_priv *priv)
146 /* set pad_aud_*_miso to GPIO mode and dir input
148 * pad_aud_clk_miso, because when playback only the miso_clk
149 * will also have 26m, so will have power leak
150 * pad_aud_dat_miso*, because the pin is used as boot strap
152 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
154 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
156 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
160 /* use only when not govern by DAPM */
161 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
163 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
164 0x1 << RG_XO_AUDIO_EN_M_SFT,
165 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
169 /* use only when not govern by DAPM */
170 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
172 /* audio clk source from internal dcxo */
173 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
174 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
177 /* Enable/disable CLKSQ 26MHz */
178 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
179 RG_CLKSQ_EN_MASK_SFT,
180 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
184 /* use only when not govern by DAPM */
185 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
187 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
188 RG_AUDGLB_PWRDN_VA28_MASK_SFT,
189 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
193 /* use only when not govern by DAPM */
194 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
196 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
197 0x0066, enable ? 0x0 : 0x66);
201 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
203 switch (priv->mtkaif_protocol) {
204 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
205 /* MTKAIF TX format setting */
206 regmap_update_bits(priv->regmap,
207 MT6358_AFE_ADDA_MTKAIF_CFG0,
209 /* enable aud_pad TX fifos */
210 regmap_update_bits(priv->regmap,
211 MT6358_AFE_AUD_PAD_TOP,
213 regmap_update_bits(priv->regmap,
214 MT6358_AFE_AUD_PAD_TOP,
217 case MT6358_MTKAIF_PROTOCOL_2:
218 /* MTKAIF TX format setting */
219 regmap_update_bits(priv->regmap,
220 MT6358_AFE_ADDA_MTKAIF_CFG0,
222 /* enable aud_pad TX fifos */
223 regmap_update_bits(priv->regmap,
224 MT6358_AFE_AUD_PAD_TOP,
227 case MT6358_MTKAIF_PROTOCOL_1:
229 /* MTKAIF TX format setting */
230 regmap_update_bits(priv->regmap,
231 MT6358_AFE_ADDA_MTKAIF_CFG0,
233 /* enable aud_pad TX fifos */
234 regmap_update_bits(priv->regmap,
235 MT6358_AFE_AUD_PAD_TOP,
242 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
244 /* disable aud_pad TX fifos */
245 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
250 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
252 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
254 playback_gpio_set(priv);
255 capture_gpio_set(priv);
256 mt6358_mtkaif_tx_enable(priv);
258 mt6358_set_dcxo(priv, true);
259 mt6358_set_aud_global_bias(priv, true);
260 mt6358_set_clksq(priv, true);
261 mt6358_set_topck(priv, true);
263 /* set dat_miso_loopback on */
264 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
265 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
266 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
267 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
268 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
269 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
273 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
275 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
277 /* set dat_miso_loopback off */
278 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
279 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
280 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
281 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
282 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
283 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
285 mt6358_set_topck(priv, false);
286 mt6358_set_clksq(priv, false);
287 mt6358_set_aud_global_bias(priv, false);
288 mt6358_set_dcxo(priv, false);
290 mt6358_mtkaif_tx_disable(priv);
291 playback_gpio_reset(priv);
292 capture_gpio_reset(priv);
296 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
297 int phase_1, int phase_2)
299 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
301 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
302 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
303 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
304 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
305 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
306 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
316 DL_GAIN_N_40DB = 0x1f,
319 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
320 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
321 #define DL_GAIN_REG_MASK 0x0f9f
323 static void hp_zcd_disable(struct mt6358_priv *priv)
325 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
328 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
330 int i = 0, stage = 0;
333 /* Enable/Reduce HPL/R main output stage step by step */
334 for (i = 0; i <= target; i++) {
335 stage = up ? i : target - i;
336 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
337 0x7 << 8, stage << 8);
338 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
339 0x7 << 11, stage << 11);
340 usleep_range(100, 150);
344 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
346 int i = 0, stage = 0;
348 /* Reduce HP aux feedback loop gain step by step */
349 for (i = 0; i <= 0xf; i++) {
350 stage = up ? i : 0xf - i;
351 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
352 0xf << 12, stage << 12);
353 usleep_range(100, 150);
357 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
362 for (i = 0x0; i <= 0x6; i++) {
363 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
365 usleep_range(600, 700);
368 for (i = 0x6; i >= 0x1; i--) {
369 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
371 usleep_range(600, 700);
376 static bool is_valid_hp_pga_idx(int reg_idx)
378 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
379 reg_idx == DL_GAIN_N_40DB;
382 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
384 int offset = 0, count = 0, reg_idx;
386 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
387 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
390 dev_info(priv->dev, "%s(), from %d, to %d\n",
398 while (offset >= 0) {
400 reg_idx = from + count;
402 reg_idx = from - count;
404 if (is_valid_hp_pga_idx(reg_idx)) {
405 regmap_update_bits(priv->regmap,
408 (reg_idx << 7) | reg_idx);
409 usleep_range(200, 300);
416 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
417 struct snd_ctl_elem_value *ucontrol)
419 struct snd_soc_component *component =
420 snd_soc_kcontrol_component(kcontrol);
421 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
422 struct soc_mixer_control *mc =
423 (struct soc_mixer_control *)kcontrol->private_value;
427 ret = snd_soc_put_volsw(kcontrol, ucontrol);
432 case MT6358_ZCD_CON2:
433 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®);
434 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
435 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
436 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
437 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
439 case MT6358_ZCD_CON1:
440 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®);
441 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
442 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
443 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
444 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
446 case MT6358_ZCD_CON3:
447 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®);
448 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
449 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
450 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
451 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
453 case MT6358_AUDENC_ANA_CON0:
454 case MT6358_AUDENC_ANA_CON1:
455 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®);
456 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
457 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
458 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®);
459 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
460 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
467 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
468 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
470 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
472 SOC_DOUBLE_EXT_TLV("Headphone Volume",
473 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
474 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
475 SOC_DOUBLE_EXT_TLV("Lineout Volume",
476 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
477 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
478 SOC_SINGLE_EXT_TLV("Handset Volume",
479 MT6358_ZCD_CON3, 0, 0x12, 1,
480 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
482 SOC_DOUBLE_R_EXT_TLV("PGA Volume",
483 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
485 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
490 static const char * const lo_in_mux_map[] = {
491 "Open", "Mute", "Playback", "Test Mode"
494 static int lo_in_mux_map_value[] = {
498 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
499 MT6358_AUDDEC_ANA_CON7,
500 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
501 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
503 lo_in_mux_map_value);
505 static const struct snd_kcontrol_new lo_in_mux_control =
506 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
518 static const char * const hp_in_mux_map[] = {
529 static int hp_in_mux_map_value[] = {
540 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
545 hp_in_mux_map_value);
547 static const struct snd_kcontrol_new hpl_in_mux_control =
548 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
550 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
555 hp_in_mux_map_value);
557 static const struct snd_kcontrol_new hpr_in_mux_control =
558 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
564 RCV_MUX_VOICE_PLAYBACK,
569 static const char * const rcv_in_mux_map[] = {
570 "Open", "Mute", "Voice Playback", "Test Mode"
573 static int rcv_in_mux_map_value[] = {
576 RCV_MUX_VOICE_PLAYBACK,
580 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
585 rcv_in_mux_map_value);
587 static const struct snd_kcontrol_new rcv_in_mux_control =
588 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
591 static const char * const dac_in_mux_map[] = {
592 "Normal Path", "Sgen"
595 static int dac_in_mux_map_value[] = {
599 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
604 dac_in_mux_map_value);
606 static const struct snd_kcontrol_new dac_in_mux_control =
607 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
610 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
615 dac_in_mux_map_value);
617 static const struct snd_kcontrol_new aif_out_mux_control =
618 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
622 MIC_TYPE_MUX_IDLE = 0,
626 MIC_TYPE_MUX_DCC_ECM_DIFF,
627 MIC_TYPE_MUX_DCC_ECM_SINGLE,
628 MIC_TYPE_MUX_MASK = 0x7,
631 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
632 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
633 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
635 static const char * const mic_type_mux_map[] = {
644 static int mic_type_mux_map_value[] = {
649 MIC_TYPE_MUX_DCC_ECM_DIFF,
650 MIC_TYPE_MUX_DCC_ECM_SINGLE,
653 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
658 mic_type_mux_map_value);
660 static const struct snd_kcontrol_new mic_type_mux_control =
661 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
667 ADC_MUX_PREAMPLIFIER,
672 static const char * const adc_left_mux_map[] = {
673 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
676 static int adc_mux_map_value[] = {
679 ADC_MUX_PREAMPLIFIER,
683 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
690 static const struct snd_kcontrol_new adc_left_mux_control =
691 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
694 static const char * const adc_right_mux_map[] = {
695 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
698 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
705 static const struct snd_kcontrol_new adc_right_mux_control =
706 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
717 static const char * const pga_mux_map[] = {
718 "None", "AIN0", "AIN1", "AIN2"
721 static int pga_mux_map_value[] = {
728 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
735 static const struct snd_kcontrol_new pga_left_mux_control =
736 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
739 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
746 static const struct snd_kcontrol_new pga_right_mux_control =
747 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
749 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
750 struct snd_kcontrol *kcontrol,
753 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
754 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
756 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
759 case SND_SOC_DAPM_PRE_PMU:
760 /* audio clk source from internal dcxo */
761 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
762 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
772 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
773 struct snd_kcontrol *kcontrol,
776 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
777 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
779 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
782 case SND_SOC_DAPM_PRE_PMU:
783 /* sdm audio fifo clock power on */
784 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
785 /* scrambler clock on enable */
786 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
788 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
789 /* sdm fifo enable */
790 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
792 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
795 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
799 case SND_SOC_DAPM_POST_PMD:
800 /* DL scrambler disabling sequence */
801 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
802 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
811 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
812 struct snd_kcontrol *kcontrol,
815 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
816 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
818 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
819 __func__, event, priv->dl_rate);
822 case SND_SOC_DAPM_PRE_PMU:
823 playback_gpio_set(priv);
825 /* sdm audio fifo clock power on */
826 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
827 /* scrambler clock on enable */
828 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
830 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
831 /* sdm fifo enable */
832 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
834 case SND_SOC_DAPM_POST_PMD:
835 /* DL scrambler disabling sequence */
836 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
837 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
839 playback_gpio_reset(priv);
848 static int mtk_hp_enable(struct mt6358_priv *priv)
850 /* Pull-down HPL/R to AVSS28_AUD */
851 hp_pull_down(priv, true);
852 /* release HP CMFB gate rstb */
853 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
856 /* Reduce ESD resistance of AU_REFN */
857 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
859 /* Set HPR/HPL gain as minimum (~ -40dB) */
860 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
862 /* Turn on DA_600K_NCP_VA18 */
863 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
864 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
865 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
866 /* Toggle RG_DIVCKS_CHG */
867 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
868 /* Set NCP soft start mode as default mode: 100us */
869 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
871 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
872 usleep_range(250, 270);
874 /* Enable cap-less LDOs (1.5V) */
875 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
877 /* Enable NV regulator (-1.2V) */
878 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
879 usleep_range(100, 120);
881 /* Disable AUD_ZCD */
882 hp_zcd_disable(priv);
884 /* Disable headphone short-circuit protection */
885 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
888 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
890 /* Set HP DR bias current optimization, 010: 6uA */
891 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
892 /* Set HP & ZCD bias current optimization */
893 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
894 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
895 /* Set HPP/N STB enhance circuits */
896 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
898 /* Enable HP aux output stage */
899 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
900 /* Enable HP aux feedback loop */
901 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
902 /* Enable HP aux CMFB loop */
903 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
904 /* Enable HP driver bias circuits */
905 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
906 /* Enable HP driver core circuits */
907 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
908 /* Short HP main output to HP aux output stage */
909 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
911 /* Enable HP main CMFB loop */
912 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
913 /* Disable HP aux CMFB loop */
914 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
916 /* Select CMFB resistor bulk to AC mode */
917 /* Selec HS/LO cap size (6.5pF default) */
918 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
920 /* Enable HP main output stage */
921 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
922 /* Enable HPR/L main output stage step by step */
923 hp_main_output_ramp(priv, true);
925 /* Reduce HP aux feedback loop gain */
926 hp_aux_feedback_loop_gain_ramp(priv, true);
927 /* Disable HP aux feedback loop */
928 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
930 /* apply volume setting */
931 headset_volume_ramp(priv,
933 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
935 /* Disable HP aux output stage */
936 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
937 /* Unshort HP main output to HP aux output stage */
938 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
939 usleep_range(100, 120);
942 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
943 /* Enable Audio DAC */
944 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
945 /* Enable low-noise mode of DAC */
946 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
947 usleep_range(100, 120);
949 /* Switch HPL MUX to audio DAC */
950 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
951 /* Switch HPR MUX to audio DAC */
952 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
954 /* Disable Pull-down HPL/R to AVSS28_AUD */
955 hp_pull_down(priv, false);
960 static int mtk_hp_disable(struct mt6358_priv *priv)
962 /* Pull-down HPL/R to AVSS28_AUD */
963 hp_pull_down(priv, true);
965 /* HPR/HPL mux to open */
966 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
969 /* Disable low-noise mode of DAC */
970 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
973 /* Disable Audio DAC */
974 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
977 /* Disable AUD_CLK */
978 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
980 /* Short HP main output to HP aux output stage */
981 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
982 /* Enable HP aux output stage */
983 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
985 /* decrease HPL/R gain to normal gain step by step */
986 headset_volume_ramp(priv,
987 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
990 /* Enable HP aux feedback loop */
991 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
993 /* Reduce HP aux feedback loop gain */
994 hp_aux_feedback_loop_gain_ramp(priv, false);
996 /* decrease HPR/L main output stage step by step */
997 hp_main_output_ramp(priv, false);
999 /* Disable HP main output stage */
1000 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1002 /* Enable HP aux CMFB loop */
1003 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1005 /* Disable HP main CMFB loop */
1006 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1008 /* Unshort HP main output to HP aux output stage */
1009 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1012 /* Disable HP driver core circuits */
1013 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1016 /* Disable HP driver bias circuits */
1017 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1020 /* Disable HP aux CMFB loop */
1021 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1023 /* Disable HP aux feedback loop */
1024 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1027 /* Disable HP aux output stage */
1028 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1032 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1033 0x1 << 8, 0x1 << 8);
1035 /* Disable NV regulator (-1.2V) */
1036 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1037 /* Disable cap-less LDOs (1.5V) */
1038 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1041 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1044 /* Increase ESD resistance of AU_REFN */
1045 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1048 /* Set HP CMFB gate rstb */
1049 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1051 /* disable Pull-down HPL/R to AVSS28_AUD */
1052 hp_pull_down(priv, false);
1057 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1059 /* Pull-down HPL/R to AVSS28_AUD */
1060 hp_pull_down(priv, true);
1061 /* release HP CMFB gate rstb */
1062 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1063 0x1 << 6, 0x1 << 6);
1065 /* Reduce ESD resistance of AU_REFN */
1066 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1068 /* Set HPR/HPL gain to -10dB */
1069 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1071 /* Turn on DA_600K_NCP_VA18 */
1072 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1073 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1074 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1075 /* Toggle RG_DIVCKS_CHG */
1076 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1077 /* Set NCP soft start mode as default mode: 100us */
1078 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1080 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1081 usleep_range(250, 270);
1083 /* Enable cap-less LDOs (1.5V) */
1084 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1086 /* Enable NV regulator (-1.2V) */
1087 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1088 usleep_range(100, 120);
1090 /* Disable AUD_ZCD */
1091 hp_zcd_disable(priv);
1093 /* Disable headphone short-circuit protection */
1094 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1097 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1099 /* Set HP DR bias current optimization, 010: 6uA */
1100 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1101 /* Set HP & ZCD bias current optimization */
1102 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1103 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1104 /* Set HPP/N STB enhance circuits */
1105 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1107 /* Disable Pull-down HPL/R to AVSS28_AUD */
1108 hp_pull_down(priv, false);
1110 /* Enable HP driver bias circuits */
1111 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1112 /* Enable HP driver core circuits */
1113 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1114 /* Enable HP main CMFB loop */
1115 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1117 /* Select CMFB resistor bulk to AC mode */
1118 /* Selec HS/LO cap size (6.5pF default) */
1119 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1121 /* Enable HP main output stage */
1122 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1123 /* Enable HPR/L main output stage step by step */
1124 hp_main_output_ramp(priv, true);
1126 /* Set LO gain as minimum (~ -40dB) */
1127 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1128 /* apply volume setting */
1129 headset_volume_ramp(priv,
1131 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1133 /* Set LO STB enhance circuits */
1134 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1135 /* Enable LO driver bias circuits */
1136 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1137 /* Enable LO driver core circuits */
1138 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1140 /* Set LOL gain to normal gain step by step */
1141 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1142 RG_AUDLOLGAIN_MASK_SFT,
1143 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1145 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1146 RG_AUDLORGAIN_MASK_SFT,
1147 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1150 /* Enable AUD_CLK */
1151 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1152 /* Enable Audio DAC */
1153 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1154 /* Enable low-noise mode of DAC */
1155 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1156 /* Switch LOL MUX to audio DAC */
1157 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1158 /* Switch HPL/R MUX to Line-out */
1159 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1164 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1166 /* HPR/HPL mux to open */
1167 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1169 /* LOL mux to open */
1170 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1173 /* Disable Audio DAC */
1174 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1177 /* Disable AUD_CLK */
1178 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1180 /* decrease HPL/R gain to normal gain step by step */
1181 headset_volume_ramp(priv,
1182 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1185 /* decrease LOL gain to minimum gain step by step */
1186 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1187 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1189 /* decrease HPR/L main output stage step by step */
1190 hp_main_output_ramp(priv, false);
1192 /* Disable HP main output stage */
1193 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1195 /* Short HP main output to HP aux output stage */
1196 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1197 /* Enable HP aux output stage */
1198 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1200 /* Enable HP aux feedback loop */
1201 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1203 /* Reduce HP aux feedback loop gain */
1204 hp_aux_feedback_loop_gain_ramp(priv, false);
1206 /* Disable HP driver core circuits */
1207 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1209 /* Disable LO driver core circuits */
1210 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1213 /* Disable HP driver bias circuits */
1214 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1216 /* Disable LO driver bias circuits */
1217 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1220 /* Disable HP aux CMFB loop */
1221 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1225 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1226 0x1 << 8, 0x1 << 8);
1227 /* Disable NV regulator (-1.2V) */
1228 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1229 /* Disable cap-less LDOs (1.5V) */
1230 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1232 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1234 /* Set HP CMFB gate rstb */
1235 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1237 /* disable Pull-down HPL/R to AVSS28_AUD */
1238 hp_pull_down(priv, false);
1243 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1244 struct snd_kcontrol *kcontrol,
1247 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1248 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1249 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1250 int device = DEVICE_HP;
1252 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1255 priv->dev_counter[device],
1259 case SND_SOC_DAPM_PRE_PMU:
1260 priv->dev_counter[device]++;
1261 if (priv->dev_counter[device] > 1)
1262 break; /* already enabled, do nothing */
1263 else if (priv->dev_counter[device] <= 0)
1264 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1266 priv->dev_counter[device]);
1268 priv->mux_select[MUX_HP_L] = mux;
1270 if (mux == HP_MUX_HP)
1271 mtk_hp_enable(priv);
1272 else if (mux == HP_MUX_HPSPK)
1273 mtk_hp_spk_enable(priv);
1275 case SND_SOC_DAPM_PRE_PMD:
1276 priv->dev_counter[device]--;
1277 if (priv->dev_counter[device] > 0) {
1278 break; /* still being used, don't close */
1279 } else if (priv->dev_counter[device] < 0) {
1280 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1282 priv->dev_counter[device]);
1283 priv->dev_counter[device] = 0;
1287 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1288 mtk_hp_disable(priv);
1289 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1290 mtk_hp_spk_disable(priv);
1292 priv->mux_select[MUX_HP_L] = mux;
1301 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1302 struct snd_kcontrol *kcontrol,
1305 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1306 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1308 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1311 dapm_kcontrol_get_value(w->kcontrols[0]));
1314 case SND_SOC_DAPM_PRE_PMU:
1315 /* Reduce ESD resistance of AU_REFN */
1316 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1318 /* Turn on DA_600K_NCP_VA18 */
1319 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1320 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1321 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1322 /* Toggle RG_DIVCKS_CHG */
1323 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1324 /* Set NCP soft start mode as default mode: 100us */
1325 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1327 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1328 usleep_range(250, 270);
1330 /* Enable cap-less LDOs (1.5V) */
1331 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1333 /* Enable NV regulator (-1.2V) */
1334 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1335 usleep_range(100, 120);
1337 /* Disable AUD_ZCD */
1338 hp_zcd_disable(priv);
1340 /* Disable handset short-circuit protection */
1341 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1344 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1345 /* Set HP DR bias current optimization, 010: 6uA */
1346 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1347 /* Set HP & ZCD bias current optimization */
1348 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1349 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1350 /* Set HS STB enhance circuits */
1351 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1353 /* Disable HP main CMFB loop */
1354 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1355 /* Select CMFB resistor bulk to AC mode */
1356 /* Selec HS/LO cap size (6.5pF default) */
1357 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1359 /* Enable HS driver bias circuits */
1360 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1361 /* Enable HS driver core circuits */
1362 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1364 /* Enable AUD_CLK */
1365 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1368 /* Enable Audio DAC */
1369 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1370 /* Enable low-noise mode of DAC */
1371 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1372 /* Switch HS MUX to audio DAC */
1373 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1375 case SND_SOC_DAPM_PRE_PMD:
1376 /* HS mux to open */
1377 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1378 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1381 /* Disable Audio DAC */
1382 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1385 /* Disable AUD_CLK */
1386 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1389 /* decrease HS gain to minimum gain step by step */
1390 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1392 /* Disable HS driver core circuits */
1393 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1396 /* Disable HS driver bias circuits */
1397 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1400 /* Disable HP aux CMFB loop */
1401 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1404 /* Enable HP main CMFB Switch */
1405 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1406 0xff << 8, 0x2 << 8);
1409 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1410 0x1 << 8, 0x1 << 8);
1412 /* Disable NV regulator (-1.2V) */
1413 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1415 /* Disable cap-less LDOs (1.5V) */
1416 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1419 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1429 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1430 struct snd_kcontrol *kcontrol,
1433 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1434 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1436 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1437 __func__, event, priv->ul_rate);
1440 case SND_SOC_DAPM_PRE_PMU:
1441 capture_gpio_set(priv);
1443 case SND_SOC_DAPM_POST_PMD:
1444 capture_gpio_reset(priv);
1453 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1454 struct snd_kcontrol *kcontrol,
1457 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1458 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1460 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1464 case SND_SOC_DAPM_PRE_PMU:
1465 /* Enable audio ADC CLKGEN */
1466 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1467 0x1 << 5, 0x1 << 5);
1468 /* ADC CLK from CLKGEN (13MHz) */
1469 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1471 /* Enable LCLDO_ENC 1P8V */
1472 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1474 /* LCLDO_ENC remote sense */
1475 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1478 case SND_SOC_DAPM_POST_PMD:
1479 /* LCLDO_ENC remote sense off */
1480 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1482 /* disable LCLDO_ENC 1P8V */
1483 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1486 /* ADC CLK from CLKGEN (13MHz) */
1487 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1488 /* disable audio ADC CLKGEN */
1489 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1490 0x1 << 5, 0x0 << 5);
1499 static int mt6358_amic_enable(struct mt6358_priv *priv)
1501 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1502 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1503 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1505 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1506 __func__, mic_type, mux_pga_l, mux_pga_r);
1508 if (IS_DCC_BASE(mic_type)) {
1509 /* DCC 50k CLK (from 26M) */
1510 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1511 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1512 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1513 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1514 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1518 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1519 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1521 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1522 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1525 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1526 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1530 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1534 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1535 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1540 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1541 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1542 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1543 regmap_write(priv->regmap,
1544 MT6358_AUDENC_ANA_CON10, 0x0161);
1546 regmap_write(priv->regmap,
1547 MT6358_AUDENC_ANA_CON10, 0x0061);
1550 if (IS_DCC_BASE(mic_type)) {
1551 /* Audio L/R preamplifier DCC precharge */
1552 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1554 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1558 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1560 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1564 if (mux_pga_l != PGA_MUX_NONE) {
1565 /* L preamplifier input sel */
1566 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1567 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1568 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1570 /* L preamplifier enable */
1571 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1572 RG_AUDPREAMPLON_MASK_SFT,
1573 0x1 << RG_AUDPREAMPLON_SFT);
1575 if (IS_DCC_BASE(mic_type)) {
1576 /* L preamplifier DCCEN */
1577 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1578 RG_AUDPREAMPLDCCEN_MASK_SFT,
1579 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1582 /* L ADC input sel : L PGA. Enable audio L ADC */
1583 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1584 RG_AUDADCLINPUTSEL_MASK_SFT,
1585 ADC_MUX_PREAMPLIFIER <<
1586 RG_AUDADCLINPUTSEL_SFT);
1587 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1588 RG_AUDADCLPWRUP_MASK_SFT,
1589 0x1 << RG_AUDADCLPWRUP_SFT);
1592 if (mux_pga_r != PGA_MUX_NONE) {
1593 /* R preamplifier input sel */
1594 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1595 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1596 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1598 /* R preamplifier enable */
1599 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1600 RG_AUDPREAMPRON_MASK_SFT,
1601 0x1 << RG_AUDPREAMPRON_SFT);
1603 if (IS_DCC_BASE(mic_type)) {
1604 /* R preamplifier DCCEN */
1605 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1606 RG_AUDPREAMPRDCCEN_MASK_SFT,
1607 0x1 << RG_AUDPREAMPRDCCEN_SFT);
1610 /* R ADC input sel : R PGA. Enable audio R ADC */
1611 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1612 RG_AUDADCRINPUTSEL_MASK_SFT,
1613 ADC_MUX_PREAMPLIFIER <<
1614 RG_AUDADCRINPUTSEL_SFT);
1615 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1616 RG_AUDADCRPWRUP_MASK_SFT,
1617 0x1 << RG_AUDADCRPWRUP_SFT);
1620 if (IS_DCC_BASE(mic_type)) {
1621 usleep_range(100, 150);
1622 /* Audio L preamplifier DCC precharge off */
1623 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1624 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1625 /* Audio R preamplifier DCC precharge off */
1626 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1627 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1629 /* Short body to ground in PGA */
1630 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1634 /* here to set digital part */
1635 mt6358_mtkaif_tx_enable(priv);
1637 /* UL dmic setting off */
1638 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1641 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1646 static void mt6358_amic_disable(struct mt6358_priv *priv)
1648 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1649 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1650 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1652 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1653 __func__, mic_type, mux_pga_l, mux_pga_r);
1656 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1659 /* disable aud_pad TX fifos */
1660 mt6358_mtkaif_tx_disable(priv);
1662 /* L ADC input sel : off, disable L ADC */
1663 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1665 /* L preamplifier DCCEN */
1666 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1668 /* L preamplifier input sel : off, L PGA 0 dB gain */
1669 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1672 /* disable L preamplifier DCC precharge */
1673 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1676 /* R ADC input sel : off, disable R ADC */
1677 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1679 /* R preamplifier DCCEN */
1680 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1682 /* R preamplifier input sel : off, R PGA 0 dB gain */
1683 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1686 /* disable R preamplifier DCC precharge */
1687 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1691 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1692 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1694 /* Disable MICBIAS1 */
1695 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1698 if (IS_DCC_BASE(mic_type)) {
1699 /* dcclk_gen_on=1'b0 */
1700 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1701 /* dcclk_pdn=1'b1 */
1702 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1703 /* dcclk_ref_ck_sel=2'b00 */
1704 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1705 /* dcclk_div=11'b00100000011 */
1706 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1710 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1712 dev_info(priv->dev, "%s()\n", __func__);
1715 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1716 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1718 /* RG_BANDGAPGEN=1'b0 */
1719 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1723 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1725 /* here to set digital part */
1726 mt6358_mtkaif_tx_enable(priv);
1728 /* UL dmic setting */
1729 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1732 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1736 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1738 dev_info(priv->dev, "%s()\n", __func__);
1741 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1744 /* disable aud_pad TX fifos */
1745 mt6358_mtkaif_tx_disable(priv);
1748 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1751 /* MISBIAS0 = 1P7V */
1752 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1754 /* RG_BANDGAPGEN=1'b0 */
1755 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1758 /* MICBIA0 disable */
1759 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1762 static void mt6358_restore_pga(struct mt6358_priv *priv)
1764 unsigned int gain_l, gain_r;
1766 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1767 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1769 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1770 RG_AUDPREAMPLGAIN_MASK_SFT,
1771 gain_l << RG_AUDPREAMPLGAIN_SFT);
1772 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1773 RG_AUDPREAMPRGAIN_MASK_SFT,
1774 gain_r << RG_AUDPREAMPRGAIN_SFT);
1777 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1778 struct snd_kcontrol *kcontrol,
1781 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1782 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1783 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1785 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1786 __func__, event, mux);
1789 case SND_SOC_DAPM_WILL_PMU:
1790 priv->mux_select[MUX_MIC_TYPE] = mux;
1792 case SND_SOC_DAPM_PRE_PMU:
1794 case MIC_TYPE_MUX_DMIC:
1795 mt6358_dmic_enable(priv);
1798 mt6358_amic_enable(priv);
1801 mt6358_restore_pga(priv);
1804 case SND_SOC_DAPM_POST_PMD:
1805 switch (priv->mux_select[MUX_MIC_TYPE]) {
1806 case MIC_TYPE_MUX_DMIC:
1807 mt6358_dmic_disable(priv);
1810 mt6358_amic_disable(priv);
1814 priv->mux_select[MUX_MIC_TYPE] = mux;
1823 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1824 struct snd_kcontrol *kcontrol,
1827 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1828 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1829 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1831 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1832 __func__, event, mux);
1834 priv->mux_select[MUX_ADC_L] = mux;
1839 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1840 struct snd_kcontrol *kcontrol,
1843 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1844 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1845 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1847 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1848 __func__, event, mux);
1850 priv->mux_select[MUX_ADC_R] = mux;
1855 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1856 struct snd_kcontrol *kcontrol,
1859 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1860 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1861 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1863 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1864 __func__, event, mux);
1866 priv->mux_select[MUX_PGA_L] = mux;
1871 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1872 struct snd_kcontrol *kcontrol,
1875 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1876 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1877 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1879 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1880 __func__, event, mux);
1882 priv->mux_select[MUX_PGA_R] = mux;
1887 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1888 struct snd_kcontrol *kcontrol,
1892 case SND_SOC_DAPM_POST_PMU:
1893 usleep_range(250, 270);
1895 case SND_SOC_DAPM_PRE_PMD:
1896 usleep_range(250, 270);
1906 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
1908 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1910 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1911 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1912 MT6358_AUDDEC_ANA_CON13,
1913 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1914 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1915 MT6358_AUDENC_ANA_CON6,
1918 SND_SOC_DAPM_PRE_PMU),
1919 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1920 MT6358_AUD_TOP_CKPDN_CON0,
1921 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1922 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1923 MT6358_AUD_TOP_CKPDN_CON0,
1924 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1925 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1926 MT6358_AUD_TOP_CKPDN_CON0,
1927 RG_AUD_CK_PDN_SFT, 1,
1929 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1930 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1931 MT6358_AUD_TOP_CKPDN_CON0,
1932 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1935 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1936 MT6358_AUDIO_TOP_CON0,
1939 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1940 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1941 MT6358_AUDIO_TOP_CON0,
1942 PDN_DAC_CTL_SFT, 1, NULL, 0),
1943 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1944 MT6358_AUDIO_TOP_CON0,
1945 PDN_ADC_CTL_SFT, 1, NULL, 0),
1946 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1947 MT6358_AUDIO_TOP_CON0,
1948 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1949 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1950 MT6358_AUDIO_TOP_CON0,
1951 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1952 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1953 MT6358_AUDIO_TOP_CON0,
1954 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1955 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1956 MT6358_AUDIO_TOP_CON0,
1957 PDN_RESERVED_SFT, 1, NULL, 0),
1959 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1963 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
1964 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
1968 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1969 MT6358_AFE_DL_SRC2_CON0_L,
1970 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
1972 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1975 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1979 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1981 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
1983 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1988 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
1989 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
1991 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
1992 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
1995 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
1996 &hpl_in_mux_control,
1998 SND_SOC_DAPM_PRE_PMU |
1999 SND_SOC_DAPM_PRE_PMD),
2001 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2002 &hpr_in_mux_control,
2004 SND_SOC_DAPM_PRE_PMU |
2005 SND_SOC_DAPM_PRE_PMD),
2008 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2009 &rcv_in_mux_control,
2011 SND_SOC_DAPM_PRE_PMU |
2012 SND_SOC_DAPM_PRE_PMD),
2015 SND_SOC_DAPM_OUTPUT("Receiver"),
2016 SND_SOC_DAPM_OUTPUT("Headphone L"),
2017 SND_SOC_DAPM_OUTPUT("Headphone R"),
2018 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2019 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2020 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2021 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2024 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2025 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2026 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2027 SGEN_MUTE_SW_CTL_SFT, 1,
2029 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2030 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2031 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2033 SND_SOC_DAPM_INPUT("SGEN DL"),
2036 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2039 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2041 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2043 mt_adc_supply_event,
2044 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2047 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2048 &aif_out_mux_control),
2050 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2051 &mic_type_mux_control,
2053 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2054 SND_SOC_DAPM_WILL_PMU),
2056 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2057 &adc_left_mux_control,
2059 SND_SOC_DAPM_WILL_PMU),
2060 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2061 &adc_right_mux_control,
2063 SND_SOC_DAPM_WILL_PMU),
2065 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2066 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2068 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2069 &pga_left_mux_control,
2071 SND_SOC_DAPM_WILL_PMU),
2072 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2073 &pga_right_mux_control,
2075 SND_SOC_DAPM_WILL_PMU),
2077 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2078 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2081 SND_SOC_DAPM_INPUT("AIN0"),
2082 SND_SOC_DAPM_INPUT("AIN1"),
2083 SND_SOC_DAPM_INPUT("AIN2"),
2086 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2088 {"AIF1TX", NULL, "AIF Out Mux"},
2089 {"AIF1TX", NULL, "CLK_BUF"},
2090 {"AIF1TX", NULL, "AUDGLB"},
2091 {"AIF1TX", NULL, "CLKSQ Audio"},
2093 {"AIF1TX", NULL, "AUD_CK"},
2094 {"AIF1TX", NULL, "AUDIF_CK"},
2096 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2097 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2098 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2099 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2100 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2102 {"AIF1TX", NULL, "AFE_ON"},
2104 {"AIF Out Mux", NULL, "Mic Type Mux"},
2106 {"Mic Type Mux", "ACC", "ADC L"},
2107 {"Mic Type Mux", "ACC", "ADC R"},
2108 {"Mic Type Mux", "DCC", "ADC L"},
2109 {"Mic Type Mux", "DCC", "ADC R"},
2110 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2111 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2112 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2113 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2114 {"Mic Type Mux", "DMIC", "AIN0"},
2115 {"Mic Type Mux", "DMIC", "AIN2"},
2117 {"ADC L", NULL, "ADC L Mux"},
2118 {"ADC L", NULL, "ADC Supply"},
2119 {"ADC R", NULL, "ADC R Mux"},
2120 {"ADC R", NULL, "ADC Supply"},
2122 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2124 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2126 {"PGA L", NULL, "PGA L Mux"},
2127 {"PGA R", NULL, "PGA R Mux"},
2129 {"PGA L Mux", "AIN0", "AIN0"},
2130 {"PGA L Mux", "AIN1", "AIN1"},
2131 {"PGA L Mux", "AIN2", "AIN2"},
2133 {"PGA R Mux", "AIN0", "AIN0"},
2134 {"PGA R Mux", "AIN1", "AIN1"},
2135 {"PGA R Mux", "AIN2", "AIN2"},
2138 {"DL Power Supply", NULL, "CLK_BUF"},
2139 {"DL Power Supply", NULL, "AUDGLB"},
2140 {"DL Power Supply", NULL, "CLKSQ Audio"},
2142 {"DL Power Supply", NULL, "AUDNCP_CK"},
2143 {"DL Power Supply", NULL, "ZCD13M_CK"},
2144 {"DL Power Supply", NULL, "AUD_CK"},
2145 {"DL Power Supply", NULL, "AUDIF_CK"},
2147 /* DL Digital Supply */
2148 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2149 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2150 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2152 {"DL Digital Clock", NULL, "AFE_ON"},
2154 {"AIF_RX", NULL, "DL Digital Clock"},
2157 {"DAC In Mux", "Normal Path", "AIF_RX"},
2159 {"DAC In Mux", "Sgen", "SGEN DL"},
2160 {"SGEN DL", NULL, "SGEN DL SRC"},
2161 {"SGEN DL", NULL, "SGEN MUTE"},
2162 {"SGEN DL", NULL, "SGEN DL Enable"},
2163 {"SGEN DL", NULL, "DL Digital Clock"},
2164 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2166 {"DACL", NULL, "DAC In Mux"},
2167 {"DACL", NULL, "DL Power Supply"},
2169 {"DACR", NULL, "DAC In Mux"},
2170 {"DACR", NULL, "DL Power Supply"},
2173 {"LOL Mux", "Playback", "DACL"},
2175 {"LOL Buffer", NULL, "LOL Mux"},
2176 {"LOL Buffer", NULL, "LO Stability Enh"},
2178 {"LINEOUT L", NULL, "LOL Buffer"},
2180 /* Headphone Path */
2181 {"HPL Mux", "Audio Playback", "DACL"},
2182 {"HPR Mux", "Audio Playback", "DACR"},
2183 {"HPL Mux", "HP Impedance", "DACL"},
2184 {"HPR Mux", "HP Impedance", "DACR"},
2185 {"HPL Mux", "LoudSPK Playback", "DACL"},
2186 {"HPR Mux", "LoudSPK Playback", "DACR"},
2188 {"Headphone L", NULL, "HPL Mux"},
2189 {"Headphone R", NULL, "HPR Mux"},
2190 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2191 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2192 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2195 {"RCV Mux", "Voice Playback", "DACL"},
2196 {"Receiver", NULL, "RCV Mux"},
2199 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2200 struct snd_pcm_hw_params *params,
2201 struct snd_soc_dai *dai)
2203 struct snd_soc_component *cmpnt = dai->component;
2204 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2205 unsigned int rate = params_rate(params);
2207 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2213 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2214 priv->dl_rate = rate;
2215 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2216 priv->ul_rate = rate;
2221 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2222 .hw_params = mt6358_codec_dai_hw_params,
2225 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2226 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2227 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2228 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2229 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2230 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2232 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2234 .name = "mt6358-snd-codec-aif1",
2236 .stream_name = "AIF1 Playback",
2239 .rates = SNDRV_PCM_RATE_8000_48000 |
2240 SNDRV_PCM_RATE_96000 |
2241 SNDRV_PCM_RATE_192000,
2242 .formats = MT6358_FORMATS,
2245 .stream_name = "AIF1 Capture",
2248 .rates = SNDRV_PCM_RATE_8000 |
2249 SNDRV_PCM_RATE_16000 |
2250 SNDRV_PCM_RATE_32000 |
2251 SNDRV_PCM_RATE_48000,
2252 .formats = MT6358_FORMATS,
2254 .ops = &mt6358_codec_dai_ops,
2258 static int mt6358_codec_init_reg(struct mt6358_priv *priv)
2262 /* Disable HeadphoneL/HeadphoneR short circuit protection */
2263 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2264 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2265 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2266 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2267 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2268 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2269 /* Disable voice short circuit protection */
2270 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2271 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2272 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2273 /* disable LO buffer left short circuit protection */
2274 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2275 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2276 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2278 /* accdet s/w enable */
2279 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2282 /* gpio miso driving set to 4mA */
2283 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2286 playback_gpio_reset(priv);
2287 capture_gpio_reset(priv);
2292 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2294 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2297 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2299 mt6358_codec_init_reg(priv);
2301 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2302 if (IS_ERR(priv->avdd_reg)) {
2303 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2304 return PTR_ERR(priv->avdd_reg);
2307 ret = regulator_enable(priv->avdd_reg);
2314 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2315 .probe = mt6358_codec_probe,
2316 .controls = mt6358_snd_controls,
2317 .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2318 .dapm_widgets = mt6358_dapm_widgets,
2319 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2320 .dapm_routes = mt6358_dapm_routes,
2321 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2324 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2326 struct mt6358_priv *priv;
2327 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2329 priv = devm_kzalloc(&pdev->dev,
2330 sizeof(struct mt6358_priv),
2335 dev_set_drvdata(&pdev->dev, priv);
2337 priv->dev = &pdev->dev;
2339 priv->regmap = mt6397->regmap;
2340 if (IS_ERR(priv->regmap))
2341 return PTR_ERR(priv->regmap);
2343 dev_info(priv->dev, "%s(), dev name %s\n",
2344 __func__, dev_name(&pdev->dev));
2346 return devm_snd_soc_register_component(&pdev->dev,
2347 &mt6358_soc_component_driver,
2349 ARRAY_SIZE(mt6358_dai_driver));
2352 static const struct of_device_id mt6358_of_match[] = {
2353 {.compatible = "mediatek,mt6358-sound",},
2356 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2358 static struct platform_driver mt6358_platform_driver = {
2360 .name = "mt6358-sound",
2361 .of_match_table = mt6358_of_match,
2363 .probe = mt6358_platform_driver_probe,
2366 module_platform_driver(mt6358_platform_driver)
2368 /* Module information */
2369 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2370 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2371 MODULE_LICENSE("GPL v2");