sound/soc/codecs/mt6358.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // mt6358.c  --  mt6358 ALSA SoC audio codec driver
   4 //
   5 // Copyright (c) 2018 MediaTek Inc.
   6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/delay.h>
  12 #include <linux/kthread.h>
  13 #include <linux/sched.h>
  14 #include <linux/mfd/mt6397/core.h>
  15 #include <linux/regulator/consumer.h>
  16
  17 #include <sound/soc.h>
  18 #include <sound/tlv.h>
  19
  20 #include "mt6358.h"
  21
  22 enum {
  23         AUDIO_ANALOG_VOLUME_HSOUTL,
  24         AUDIO_ANALOG_VOLUME_HSOUTR,
  25         AUDIO_ANALOG_VOLUME_HPOUTL,
  26         AUDIO_ANALOG_VOLUME_HPOUTR,
  27         AUDIO_ANALOG_VOLUME_LINEOUTL,
  28         AUDIO_ANALOG_VOLUME_LINEOUTR,
  29         AUDIO_ANALOG_VOLUME_MICAMP1,
  30         AUDIO_ANALOG_VOLUME_MICAMP2,
  31         AUDIO_ANALOG_VOLUME_TYPE_MAX
  32 };
  33
  34 enum {
  35         MUX_ADC_L,
  36         MUX_ADC_R,
  37         MUX_PGA_L,
  38         MUX_PGA_R,
  39         MUX_MIC_TYPE,
  40         MUX_HP_L,
  41         MUX_HP_R,
  42         MUX_NUM,
  43 };
  44
  45 enum {
  46         DEVICE_HP,
  47         DEVICE_LO,
  48         DEVICE_RCV,
  49         DEVICE_MIC1,
  50         DEVICE_MIC2,
  51         DEVICE_NUM
  52 };
  53
  54 /* Supply widget subseq */
  55 enum {
  56         /* common */
  57         SUPPLY_SEQ_CLK_BUF,
  58         SUPPLY_SEQ_AUD_GLB,
  59         SUPPLY_SEQ_CLKSQ,
  60         SUPPLY_SEQ_VOW_AUD_LPW,
  61         SUPPLY_SEQ_AUD_VOW,
  62         SUPPLY_SEQ_VOW_CLK,
  63         SUPPLY_SEQ_VOW_LDO,
  64         SUPPLY_SEQ_TOP_CK,
  65         SUPPLY_SEQ_TOP_CK_LAST,
  66         SUPPLY_SEQ_AUD_TOP,
  67         SUPPLY_SEQ_AUD_TOP_LAST,
  68         SUPPLY_SEQ_AFE,
  69         /* capture */
  70         SUPPLY_SEQ_ADC_SUPPLY,
  71 };
  72
  73 enum {
  74         CH_L = 0,
  75         CH_R,
  76         NUM_CH,
  77 };
  78
  79 #define REG_STRIDE 2
  80
  81 struct mt6358_priv {
  82         struct device *dev;
  83         struct regmap *regmap;
  84
  85         unsigned int dl_rate;
  86         unsigned int ul_rate;
  87
  88         int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  89         unsigned int mux_select[MUX_NUM];
  90
  91         int dev_counter[DEVICE_NUM];
  92
  93         int mtkaif_protocol;
  94
  95         struct regulator *avdd_reg;
  96 };
  97
  98 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
  99                                int mtkaif_protocol)
 100 {
 101         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 102
 103         priv->mtkaif_protocol = mtkaif_protocol;
 104         return 0;
 105 }
 106
 107 static void playback_gpio_set(struct mt6358_priv *priv)
 108 {
 109         /* set gpio mosi mode */
 110         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
 111                            0x01f8, 0x01f8);
 112         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
 113                            0xffff, 0x0249);
 114         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
 115                            0xffff, 0x0249);
 116 }
 117
 118 static void playback_gpio_reset(struct mt6358_priv *priv)
 119 {
 120         /* set pad_aud_*_mosi to GPIO mode and dir input
 121          * reason:
 122          * pad_aud_dat_mosi*, because the pin is used as boot strap
 123          * don't clean clk/sync, for mtkaif protocol 2
 124          */
 125         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
 126                            0x01f8, 0x01f8);
 127         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
 128                            0x01f8, 0x0000);
 129         regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
 130                            0xf << 8, 0x0);
 131 }
 132
 133 static void capture_gpio_set(struct mt6358_priv *priv)
 134 {
 135         /* set gpio miso mode */
 136         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
 137                            0xffff, 0xffff);
 138         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
 139                            0xffff, 0x0249);
 140         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
 141                            0xffff, 0x0249);
 142 }
 143
 144 static void capture_gpio_reset(struct mt6358_priv *priv)
 145 {
 146         /* set pad_aud_*_miso to GPIO mode and dir input
 147          * reason:
 148          * pad_aud_clk_miso, because when playback only the miso_clk
 149          * will also have 26m, so will have power leak
 150          * pad_aud_dat_miso*, because the pin is used as boot strap
 151          */
 152         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
 153                            0xffff, 0xffff);
 154         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
 155                            0xffff, 0x0000);
 156         regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
 157                            0xf << 12, 0x0);
 158 }
 159
 160 /* use only when not govern by DAPM */
 161 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
 162 {
 163         regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
 164                            0x1 << RG_XO_AUDIO_EN_M_SFT,
 165                            (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
 166         return 0;
 167 }
 168
 169 /* use only when not govern by DAPM */
 170 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
 171 {
 172         /* audio clk source from internal dcxo */
 173         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 174                            RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
 175                            0x0);
 176
 177         /* Enable/disable CLKSQ 26MHz */
 178         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 179                            RG_CLKSQ_EN_MASK_SFT,
 180                            (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
 181         return 0;
 182 }
 183
 184 /* use only when not govern by DAPM */
 185 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
 186 {
 187         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
 188                            RG_AUDGLB_PWRDN_VA28_MASK_SFT,
 189                            (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
 190         return 0;
 191 }
 192
 193 /* use only when not govern by DAPM */
 194 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
 195 {
 196         regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
 197                            0x0066, enable ? 0x0 : 0x66);
 198         return 0;
 199 }
 200
 201 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
 202 {
 203         switch (priv->mtkaif_protocol) {
 204         case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
 205                 /* MTKAIF TX format setting */
 206                 regmap_update_bits(priv->regmap,
 207                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 208                                    0xffff, 0x0010);
 209                 /* enable aud_pad TX fifos */
 210                 regmap_update_bits(priv->regmap,
 211                                    MT6358_AFE_AUD_PAD_TOP,
 212                                    0xff00, 0x3800);
 213                 regmap_update_bits(priv->regmap,
 214                                    MT6358_AFE_AUD_PAD_TOP,
 215                                    0xff00, 0x3900);
 216                 break;
 217         case MT6358_MTKAIF_PROTOCOL_2:
 218                 /* MTKAIF TX format setting */
 219                 regmap_update_bits(priv->regmap,
 220                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 221                                    0xffff, 0x0010);
 222                 /* enable aud_pad TX fifos */
 223                 regmap_update_bits(priv->regmap,
 224                                    MT6358_AFE_AUD_PAD_TOP,
 225                                    0xff00, 0x3100);
 226                 break;
 227         case MT6358_MTKAIF_PROTOCOL_1:
 228         default:
 229                 /* MTKAIF TX format setting */
 230                 regmap_update_bits(priv->regmap,
 231                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 232                                    0xffff, 0x0000);
 233                 /* enable aud_pad TX fifos */
 234                 regmap_update_bits(priv->regmap,
 235                                    MT6358_AFE_AUD_PAD_TOP,
 236                                    0xff00, 0x3100);
 237                 break;
 238         }
 239         return 0;
 240 }
 241
 242 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
 243 {
 244         /* disable aud_pad TX fifos */
 245         regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
 246                            0xff00, 0x3000);
 247         return 0;
 248 }
 249
 250 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
 251 {
 252         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 253
 254         playback_gpio_set(priv);
 255         capture_gpio_set(priv);
 256         mt6358_mtkaif_tx_enable(priv);
 257
 258         mt6358_set_dcxo(priv, true);
 259         mt6358_set_aud_global_bias(priv, true);
 260         mt6358_set_clksq(priv, true);
 261         mt6358_set_topck(priv, true);
 262
 263         /* set dat_miso_loopback on */
 264         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 265                            RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 266                            1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 267         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 268                            RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 269                            1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 270         return 0;
 271 }
 272
 273 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
 274 {
 275         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 276
 277         /* set dat_miso_loopback off */
 278         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 279                            RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 280                            0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 281         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 282                            RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 283                            0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 284
 285         mt6358_set_topck(priv, false);
 286         mt6358_set_clksq(priv, false);
 287         mt6358_set_aud_global_bias(priv, false);
 288         mt6358_set_dcxo(priv, false);
 289
 290         mt6358_mtkaif_tx_disable(priv);
 291         playback_gpio_reset(priv);
 292         capture_gpio_reset(priv);
 293         return 0;
 294 }
 295
 296 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
 297                                         int phase_1, int phase_2)
 298 {
 299         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 300
 301         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 302                            RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
 303                            phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
 304         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 305                            RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
 306                            phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
 307         return 0;
 308 }
 309
 310 /* dl pga gain */
 311 enum {
 312         DL_GAIN_8DB = 0,
 313         DL_GAIN_0DB = 8,
 314         DL_GAIN_N_1DB = 9,
 315         DL_GAIN_N_10DB = 18,
 316         DL_GAIN_N_40DB = 0x1f,
 317 };
 318
 319 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
 320 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
 321 #define DL_GAIN_REG_MASK 0x0f9f
 322
 323 static void hp_zcd_disable(struct mt6358_priv *priv)
 324 {
 325         regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
 326 }
 327
 328 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
 329 {
 330         int i = 0, stage = 0;
 331         int target = 7;
 332
 333         /* Enable/Reduce HPL/R main output stage step by step */
 334         for (i = 0; i <= target; i++) {
 335                 stage = up ? i : target - i;
 336                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
 337                                    0x7 << 8, stage << 8);
 338                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
 339                                    0x7 << 11, stage << 11);
 340                 usleep_range(100, 150);
 341         }
 342 }
 343
 344 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
 345 {
 346         int i = 0, stage = 0;
 347
 348         /* Reduce HP aux feedback loop gain step by step */
 349         for (i = 0; i <= 0xf; i++) {
 350                 stage = up ? i : 0xf - i;
 351                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
 352                                    0xf << 12, stage << 12);
 353                 usleep_range(100, 150);
 354         }
 355 }
 356
 357 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
 358 {
 359         int i;
 360
 361         if (enable) {
 362                 for (i = 0x0; i <= 0x6; i++) {
 363                         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 364                                            0x7, i);
 365                         usleep_range(600, 700);
 366                 }
 367         } else {
 368                 for (i = 0x6; i >= 0x1; i--) {
 369                         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 370                                            0x7, i);
 371                         usleep_range(600, 700);
 372                 }
 373         }
 374 }
 375
 376 static bool is_valid_hp_pga_idx(int reg_idx)
 377 {
 378         return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
 379                reg_idx == DL_GAIN_N_40DB;
 380 }
 381
 382 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
 383 {
 384         int offset = 0, count = 0, reg_idx;
 385
 386         if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
 387                 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
 388                          __func__, from, to);
 389
 390         dev_info(priv->dev, "%s(), from %d, to %d\n",
 391                  __func__, from, to);
 392
 393         if (to > from)
 394                 offset = to - from;
 395         else
 396                 offset = from - to;
 397
 398         while (offset >= 0) {
 399                 if (to > from)
 400                         reg_idx = from + count;
 401                 else
 402                         reg_idx = from - count;
 403
 404                 if (is_valid_hp_pga_idx(reg_idx)) {
 405                         regmap_update_bits(priv->regmap,
 406                                            MT6358_ZCD_CON2,
 407                                            DL_GAIN_REG_MASK,
 408                                            (reg_idx << 7) | reg_idx);
 409                         usleep_range(200, 300);
 410                 }
 411                 offset--;
 412                 count++;
 413         }
 414 }
 415
 416 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
 417                             struct snd_ctl_elem_value *ucontrol)
 418 {
 419         struct snd_soc_component *component =
 420                         snd_soc_kcontrol_component(kcontrol);
 421         struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
 422         struct soc_mixer_control *mc =
 423                         (struct soc_mixer_control *)kcontrol->private_value;
 424         unsigned int reg;
 425         int ret;
 426
 427         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 428         if (ret < 0)
 429                 return ret;
 430
 431         switch (mc->reg) {
 432         case MT6358_ZCD_CON2:
 433                 regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
 434                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
 435                         (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
 436                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
 437                         (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
 438                 break;
 439         case MT6358_ZCD_CON1:
 440                 regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
 441                 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
 442                         (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
 443                 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
 444                         (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
 445                 break;
 446         case MT6358_ZCD_CON3:
 447                 regmap_read(priv->regmap, MT6358_ZCD_CON3, &reg);
 448                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
 449                         (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
 450                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
 451                         (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
 452                 break;
 453         case MT6358_AUDENC_ANA_CON0:
 454         case MT6358_AUDENC_ANA_CON1:
 455                 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &reg);
 456                 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
 457                         (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
 458                 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &reg);
 459                 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
 460                         (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
 461                 break;
 462         }
 463
 464         return ret;
 465 }
 466
 467 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
 468 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
 469
 470 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
 471         /* dl pga gain */
 472         SOC_DOUBLE_EXT_TLV("Headphone Volume",
 473                            MT6358_ZCD_CON2, 0, 7, 0x12, 1,
 474                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 475         SOC_DOUBLE_EXT_TLV("Lineout Volume",
 476                            MT6358_ZCD_CON1, 0, 7, 0x12, 1,
 477                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 478         SOC_SINGLE_EXT_TLV("Handset Volume",
 479                            MT6358_ZCD_CON3, 0, 0x12, 1,
 480                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 481         /* ul pga gain */
 482         SOC_DOUBLE_R_EXT_TLV("PGA Volume",
 483                              MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
 484                              8, 4, 0,
 485                              snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
 486 };
 487
 488 /* MUX */
 489 /* LOL MUX */
 490 static const char * const lo_in_mux_map[] = {
 491         "Open", "Mute", "Playback", "Test Mode"
 492 };
 493
 494 static int lo_in_mux_map_value[] = {
 495         0x0, 0x1, 0x2, 0x3,
 496 };
 497
 498 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
 499                                   MT6358_AUDDEC_ANA_CON7,
 500                                   RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
 501                                   RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
 502                                   lo_in_mux_map,
 503                                   lo_in_mux_map_value);
 504
 505 static const struct snd_kcontrol_new lo_in_mux_control =
 506         SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
 507
 508 /*HP MUX */
 509 enum {
 510         HP_MUX_OPEN = 0,
 511         HP_MUX_HPSPK,
 512         HP_MUX_HP,
 513         HP_MUX_TEST_MODE,
 514         HP_MUX_HP_IMPEDANCE,
 515         HP_MUX_MASK = 0x7,
 516 };
 517
 518 static const char * const hp_in_mux_map[] = {
 519         "Open",
 520         "LoudSPK Playback",
 521         "Audio Playback",
 522         "Test Mode",
 523         "HP Impedance",
 524         "undefined1",
 525         "undefined2",
 526         "undefined3",
 527 };
 528
 529 static int hp_in_mux_map_value[] = {
 530         HP_MUX_OPEN,
 531         HP_MUX_HPSPK,
 532         HP_MUX_HP,
 533         HP_MUX_TEST_MODE,
 534         HP_MUX_HP_IMPEDANCE,
 535         HP_MUX_OPEN,
 536         HP_MUX_OPEN,
 537         HP_MUX_OPEN,
 538 };
 539
 540 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
 541                                   SND_SOC_NOPM,
 542                                   0,
 543                                   HP_MUX_MASK,
 544                                   hp_in_mux_map,
 545                                   hp_in_mux_map_value);
 546
 547 static const struct snd_kcontrol_new hpl_in_mux_control =
 548         SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
 549
 550 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
 551                                   SND_SOC_NOPM,
 552                                   0,
 553                                   HP_MUX_MASK,
 554                                   hp_in_mux_map,
 555                                   hp_in_mux_map_value);
 556
 557 static const struct snd_kcontrol_new hpr_in_mux_control =
 558         SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
 559
 560 /* RCV MUX */
 561 enum {
 562         RCV_MUX_OPEN = 0,
 563         RCV_MUX_MUTE,
 564         RCV_MUX_VOICE_PLAYBACK,
 565         RCV_MUX_TEST_MODE,
 566         RCV_MUX_MASK = 0x3,
 567 };
 568
 569 static const char * const rcv_in_mux_map[] = {
 570         "Open", "Mute", "Voice Playback", "Test Mode"
 571 };
 572
 573 static int rcv_in_mux_map_value[] = {
 574         RCV_MUX_OPEN,
 575         RCV_MUX_MUTE,
 576         RCV_MUX_VOICE_PLAYBACK,
 577         RCV_MUX_TEST_MODE,
 578 };
 579
 580 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
 581                                   SND_SOC_NOPM,
 582                                   0,
 583                                   RCV_MUX_MASK,
 584                                   rcv_in_mux_map,
 585                                   rcv_in_mux_map_value);
 586
 587 static const struct snd_kcontrol_new rcv_in_mux_control =
 588         SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
 589
 590 /* DAC In MUX */
 591 static const char * const dac_in_mux_map[] = {
 592         "Normal Path", "Sgen"
 593 };
 594
 595 static int dac_in_mux_map_value[] = {
 596         0x0, 0x1,
 597 };
 598
 599 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
 600                                   MT6358_AFE_TOP_CON0,
 601                                   DL_SINE_ON_SFT,
 602                                   DL_SINE_ON_MASK,
 603                                   dac_in_mux_map,
 604                                   dac_in_mux_map_value);
 605
 606 static const struct snd_kcontrol_new dac_in_mux_control =
 607         SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
 608
 609 /* AIF Out MUX */
 610 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
 611                                   MT6358_AFE_TOP_CON0,
 612                                   UL_SINE_ON_SFT,
 613                                   UL_SINE_ON_MASK,
 614                                   dac_in_mux_map,
 615                                   dac_in_mux_map_value);
 616
 617 static const struct snd_kcontrol_new aif_out_mux_control =
 618         SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
 619
 620 /* Mic Type MUX */
 621 enum {
 622         MIC_TYPE_MUX_IDLE = 0,
 623         MIC_TYPE_MUX_ACC,
 624         MIC_TYPE_MUX_DMIC,
 625         MIC_TYPE_MUX_DCC,
 626         MIC_TYPE_MUX_DCC_ECM_DIFF,
 627         MIC_TYPE_MUX_DCC_ECM_SINGLE,
 628         MIC_TYPE_MUX_MASK = 0x7,
 629 };
 630
 631 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
 632                         (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
 633                         (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
 634
 635 static const char * const mic_type_mux_map[] = {
 636         "Idle",
 637         "ACC",
 638         "DMIC",
 639         "DCC",
 640         "DCC_ECM_DIFF",
 641         "DCC_ECM_SINGLE",
 642 };
 643
 644 static int mic_type_mux_map_value[] = {
 645         MIC_TYPE_MUX_IDLE,
 646         MIC_TYPE_MUX_ACC,
 647         MIC_TYPE_MUX_DMIC,
 648         MIC_TYPE_MUX_DCC,
 649         MIC_TYPE_MUX_DCC_ECM_DIFF,
 650         MIC_TYPE_MUX_DCC_ECM_SINGLE,
 651 };
 652
 653 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
 654                                   SND_SOC_NOPM,
 655                                   0,
 656                                   MIC_TYPE_MUX_MASK,
 657                                   mic_type_mux_map,
 658                                   mic_type_mux_map_value);
 659
 660 static const struct snd_kcontrol_new mic_type_mux_control =
 661         SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
 662
 663 /* ADC L MUX */
 664 enum {
 665         ADC_MUX_IDLE = 0,
 666         ADC_MUX_AIN0,
 667         ADC_MUX_PREAMPLIFIER,
 668         ADC_MUX_IDLE1,
 669         ADC_MUX_MASK = 0x3,
 670 };
 671
 672 static const char * const adc_left_mux_map[] = {
 673         "Idle", "AIN0", "Left Preamplifier", "Idle_1"
 674 };
 675
 676 static int adc_mux_map_value[] = {
 677         ADC_MUX_IDLE,
 678         ADC_MUX_AIN0,
 679         ADC_MUX_PREAMPLIFIER,
 680         ADC_MUX_IDLE1,
 681 };
 682
 683 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
 684                                   SND_SOC_NOPM,
 685                                   0,
 686                                   ADC_MUX_MASK,
 687                                   adc_left_mux_map,
 688                                   adc_mux_map_value);
 689
 690 static const struct snd_kcontrol_new adc_left_mux_control =
 691         SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
 692
 693 /* ADC R MUX */
 694 static const char * const adc_right_mux_map[] = {
 695         "Idle", "AIN0", "Right Preamplifier", "Idle_1"
 696 };
 697
 698 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
 699                                   SND_SOC_NOPM,
 700                                   0,
 701                                   ADC_MUX_MASK,
 702                                   adc_right_mux_map,
 703                                   adc_mux_map_value);
 704
 705 static const struct snd_kcontrol_new adc_right_mux_control =
 706         SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
 707
 708 /* PGA L MUX */
 709 enum {
 710         PGA_MUX_NONE = 0,
 711         PGA_MUX_AIN0,
 712         PGA_MUX_AIN1,
 713         PGA_MUX_AIN2,
 714         PGA_MUX_MASK = 0x3,
 715 };
 716
 717 static const char * const pga_mux_map[] = {
 718         "None", "AIN0", "AIN1", "AIN2"
 719 };
 720
 721 static int pga_mux_map_value[] = {
 722         PGA_MUX_NONE,
 723         PGA_MUX_AIN0,
 724         PGA_MUX_AIN1,
 725         PGA_MUX_AIN2,
 726 };
 727
 728 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
 729                                   SND_SOC_NOPM,
 730                                   0,
 731                                   PGA_MUX_MASK,
 732                                   pga_mux_map,
 733                                   pga_mux_map_value);
 734
 735 static const struct snd_kcontrol_new pga_left_mux_control =
 736         SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
 737
 738 /* PGA R MUX */
 739 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
 740                                   SND_SOC_NOPM,
 741                                   0,
 742                                   PGA_MUX_MASK,
 743                                   pga_mux_map,
 744                                   pga_mux_map_value);
 745
 746 static const struct snd_kcontrol_new pga_right_mux_control =
 747         SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
 748
 749 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
 750                           struct snd_kcontrol *kcontrol,
 751                           int event)
 752 {
 753         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 754         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 755
 756         dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
 757
 758         switch (event) {
 759         case SND_SOC_DAPM_PRE_PMU:
 760                 /* audio clk source from internal dcxo */
 761                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 762                                    RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
 763                                    0x0);
 764                 break;
 765         default:
 766                 break;
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
 773                          struct snd_kcontrol *kcontrol,
 774                          int event)
 775 {
 776         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 777         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 778
 779         dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
 780
 781         switch (event) {
 782         case SND_SOC_DAPM_PRE_PMU:
 783                 /* sdm audio fifo clock power on */
 784                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
 785                 /* scrambler clock on enable */
 786                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
 787                 /* sdm power on */
 788                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
 789                 /* sdm fifo enable */
 790                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
 791
 792                 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
 793                                    0xff3f,
 794                                    0x0000);
 795                 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
 796                                    0xffff,
 797                                    0x0001);
 798                 break;
 799         case SND_SOC_DAPM_POST_PMD:
 800                 /* DL scrambler disabling sequence */
 801                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
 802                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         return 0;
 809 }
 810
 811 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
 812                            struct snd_kcontrol *kcontrol,
 813                            int event)
 814 {
 815         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 816         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 817
 818         dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
 819                  __func__, event, priv->dl_rate);
 820
 821         switch (event) {
 822         case SND_SOC_DAPM_PRE_PMU:
 823                 playback_gpio_set(priv);
 824
 825                 /* sdm audio fifo clock power on */
 826                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
 827                 /* scrambler clock on enable */
 828                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
 829                 /* sdm power on */
 830                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
 831                 /* sdm fifo enable */
 832                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
 833                 break;
 834         case SND_SOC_DAPM_POST_PMD:
 835                 /* DL scrambler disabling sequence */
 836                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
 837                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
 838
 839                 playback_gpio_reset(priv);
 840                 break;
 841         default:
 842                 break;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int mtk_hp_enable(struct mt6358_priv *priv)
 849 {
 850         /* Pull-down HPL/R to AVSS28_AUD */
 851         hp_pull_down(priv, true);
 852         /* release HP CMFB gate rstb */
 853         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 854                            0x1 << 6, 0x1 << 6);
 855
 856         /* Reduce ESD resistance of AU_REFN */
 857         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
 858
 859         /* Set HPR/HPL gain as minimum (~ -40dB) */
 860         regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
 861
 862         /* Turn on DA_600K_NCP_VA18 */
 863         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
 864         /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
 865         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
 866         /* Toggle RG_DIVCKS_CHG */
 867         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
 868         /* Set NCP soft start mode as default mode: 100us */
 869         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
 870         /* Enable NCP */
 871         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
 872         usleep_range(250, 270);
 873
 874         /* Enable cap-less LDOs (1.5V) */
 875         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
 876                            0x1055, 0x1055);
 877         /* Enable NV regulator (-1.2V) */
 878         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
 879         usleep_range(100, 120);
 880
 881         /* Disable AUD_ZCD */
 882         hp_zcd_disable(priv);
 883
 884         /* Disable headphone short-circuit protection */
 885         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
 886
 887         /* Enable IBIST */
 888         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
 889
 890         /* Set HP DR bias current optimization, 010: 6uA */
 891         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
 892         /* Set HP & ZCD bias current optimization */
 893         /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
 894         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
 895         /* Set HPP/N STB enhance circuits */
 896         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
 897
 898         /* Enable HP aux output stage */
 899         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
 900         /* Enable HP aux feedback loop */
 901         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
 902         /* Enable HP aux CMFB loop */
 903         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
 904         /* Enable HP driver bias circuits */
 905         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
 906         /* Enable HP driver core circuits */
 907         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
 908         /* Short HP main output to HP aux output stage */
 909         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
 910
 911         /* Enable HP main CMFB loop */
 912         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
 913         /* Disable HP aux CMFB loop */
 914         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
 915
 916         /* Select CMFB resistor bulk to AC mode */
 917         /* Selec HS/LO cap size (6.5pF default) */
 918         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
 919
 920         /* Enable HP main output stage */
 921         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
 922         /* Enable HPR/L main output stage step by step */
 923         hp_main_output_ramp(priv, true);
 924
 925         /* Reduce HP aux feedback loop gain */
 926         hp_aux_feedback_loop_gain_ramp(priv, true);
 927         /* Disable HP aux feedback loop */
 928         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
 929
 930         /* apply volume setting */
 931         headset_volume_ramp(priv,
 932                             DL_GAIN_N_10DB,
 933                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
 934
 935         /* Disable HP aux output stage */
 936         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
 937         /* Unshort HP main output to HP aux output stage */
 938         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
 939         usleep_range(100, 120);
 940
 941         /* Enable AUD_CLK */
 942         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
 943         /* Enable Audio DAC  */
 944         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
 945         /* Enable low-noise mode of DAC */
 946         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
 947         usleep_range(100, 120);
 948
 949         /* Switch HPL MUX to audio DAC */
 950         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
 951         /* Switch HPR MUX to audio DAC */
 952         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
 953
 954         /* Disable Pull-down HPL/R to AVSS28_AUD */
 955         hp_pull_down(priv, false);
 956
 957         return 0;
 958 }
 959
 960 static int mtk_hp_disable(struct mt6358_priv *priv)
 961 {
 962         /* Pull-down HPL/R to AVSS28_AUD */
 963         hp_pull_down(priv, true);
 964
 965         /* HPR/HPL mux to open */
 966         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
 967                            0x0f00, 0x0000);
 968
 969         /* Disable low-noise mode of DAC */
 970         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
 971                            0x0001, 0x0000);
 972
 973         /* Disable Audio DAC */
 974         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
 975                            0x000f, 0x0000);
 976
 977         /* Disable AUD_CLK */
 978         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
 979
 980         /* Short HP main output to HP aux output stage */
 981         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
 982         /* Enable HP aux output stage */
 983         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
 984
 985         /* decrease HPL/R gain to normal gain step by step */
 986         headset_volume_ramp(priv,
 987                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
 988                             DL_GAIN_N_40DB);
 989
 990         /* Enable HP aux feedback loop */
 991         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
 992
 993         /* Reduce HP aux feedback loop gain */
 994         hp_aux_feedback_loop_gain_ramp(priv, false);
 995
 996         /* decrease HPR/L main output stage step by step */
 997         hp_main_output_ramp(priv, false);
 998
 999         /* Disable HP main output stage */
1000         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1001
1002         /* Enable HP aux CMFB loop */
1003         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1004
1005         /* Disable HP main CMFB loop */
1006         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1007
1008         /* Unshort HP main output to HP aux output stage */
1009         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1010                            0x3 << 6, 0x0);
1011
1012         /* Disable HP driver core circuits */
1013         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1014                            0x3 << 4, 0x0);
1015
1016         /* Disable HP driver bias circuits */
1017         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1018                            0x3 << 6, 0x0);
1019
1020         /* Disable HP aux CMFB loop */
1021         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1022
1023         /* Disable HP aux feedback loop */
1024         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1025                            0x3 << 4, 0x0);
1026
1027         /* Disable HP aux output stage */
1028         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1029                            0x3 << 2, 0x0);
1030
1031         /* Disable IBIST */
1032         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1033                            0x1 << 8, 0x1 << 8);
1034
1035         /* Disable NV regulator (-1.2V) */
1036         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1037         /* Disable cap-less LDOs (1.5V) */
1038         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1039                            0x1055, 0x0);
1040         /* Disable NCP */
1041         regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1042                            0x1, 0x1);
1043
1044         /* Increase ESD resistance of AU_REFN */
1045         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1046                            0x1 << 14, 0x0);
1047
1048         /* Set HP CMFB gate rstb */
1049         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1050                            0x1 << 6, 0x0);
1051         /* disable Pull-down HPL/R to AVSS28_AUD */
1052         hp_pull_down(priv, false);
1053
1054         return 0;
1055 }
1056
1057 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1058 {
1059         /* Pull-down HPL/R to AVSS28_AUD */
1060         hp_pull_down(priv, true);
1061         /* release HP CMFB gate rstb */
1062         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1063                            0x1 << 6, 0x1 << 6);
1064
1065         /* Reduce ESD resistance of AU_REFN */
1066         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1067
1068         /* Set HPR/HPL gain to -10dB */
1069         regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1070
1071         /* Turn on DA_600K_NCP_VA18 */
1072         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1073         /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1074         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1075         /* Toggle RG_DIVCKS_CHG */
1076         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1077         /* Set NCP soft start mode as default mode: 100us */
1078         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1079         /* Enable NCP */
1080         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1081         usleep_range(250, 270);
1082
1083         /* Enable cap-less LDOs (1.5V) */
1084         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1085                            0x1055, 0x1055);
1086         /* Enable NV regulator (-1.2V) */
1087         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1088         usleep_range(100, 120);
1089
1090         /* Disable AUD_ZCD */
1091         hp_zcd_disable(priv);
1092
1093         /* Disable headphone short-circuit protection */
1094         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1095
1096         /* Enable IBIST */
1097         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1098
1099         /* Set HP DR bias current optimization, 010: 6uA */
1100         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1101         /* Set HP & ZCD bias current optimization */
1102         /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1103         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1104         /* Set HPP/N STB enhance circuits */
1105         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1106
1107         /* Disable Pull-down HPL/R to AVSS28_AUD */
1108         hp_pull_down(priv, false);
1109
1110         /* Enable HP driver bias circuits */
1111         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1112         /* Enable HP driver core circuits */
1113         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1114         /* Enable HP main CMFB loop */
1115         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1116
1117         /* Select CMFB resistor bulk to AC mode */
1118         /* Selec HS/LO cap size (6.5pF default) */
1119         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1120
1121         /* Enable HP main output stage */
1122         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1123         /* Enable HPR/L main output stage step by step */
1124         hp_main_output_ramp(priv, true);
1125
1126         /* Set LO gain as minimum (~ -40dB) */
1127         regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1128         /* apply volume setting */
1129         headset_volume_ramp(priv,
1130                             DL_GAIN_N_10DB,
1131                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1132
1133         /* Set LO STB enhance circuits */
1134         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1135         /* Enable LO driver bias circuits */
1136         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1137         /* Enable LO driver core circuits */
1138         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1139
1140         /* Set LOL gain to normal gain step by step */
1141         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1142                            RG_AUDLOLGAIN_MASK_SFT,
1143                            priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1144                            RG_AUDLOLGAIN_SFT);
1145         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1146                            RG_AUDLORGAIN_MASK_SFT,
1147                            priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1148                            RG_AUDLORGAIN_SFT);
1149
1150         /* Enable AUD_CLK */
1151         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1152         /* Enable Audio DAC  */
1153         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1154         /* Enable low-noise mode of DAC */
1155         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1156         /* Switch LOL MUX to audio DAC */
1157         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1158         /* Switch HPL/R MUX to Line-out */
1159         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1160
1161         return 0;
1162 }
1163
1164 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1165 {
1166         /* HPR/HPL mux to open */
1167         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1168                            0x0f00, 0x0000);
1169         /* LOL mux to open */
1170         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1171                            0x3 << 2, 0x0000);
1172
1173         /* Disable Audio DAC */
1174         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1175                            0x000f, 0x0000);
1176
1177         /* Disable AUD_CLK */
1178         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1179
1180         /* decrease HPL/R gain to normal gain step by step */
1181         headset_volume_ramp(priv,
1182                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1183                             DL_GAIN_N_40DB);
1184
1185         /* decrease LOL gain to minimum gain step by step */
1186         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1187                            DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1188
1189         /* decrease HPR/L main output stage step by step */
1190         hp_main_output_ramp(priv, false);
1191
1192         /* Disable HP main output stage */
1193         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1194
1195         /* Short HP main output to HP aux output stage */
1196         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1197         /* Enable HP aux output stage */
1198         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1199
1200         /* Enable HP aux feedback loop */
1201         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1202
1203         /* Reduce HP aux feedback loop gain */
1204         hp_aux_feedback_loop_gain_ramp(priv, false);
1205
1206         /* Disable HP driver core circuits */
1207         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1208                            0x3 << 4, 0x0);
1209         /* Disable LO driver core circuits */
1210         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1211                            0x1, 0x0);
1212
1213         /* Disable HP driver bias circuits */
1214         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1215                            0x3 << 6, 0x0);
1216         /* Disable LO driver bias circuits */
1217         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1218                            0x1 << 1, 0x0);
1219
1220         /* Disable HP aux CMFB loop */
1221         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1222                            0xff << 8, 0x0000);
1223
1224         /* Disable IBIST */
1225         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1226                            0x1 << 8, 0x1 << 8);
1227         /* Disable NV regulator (-1.2V) */
1228         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1229         /* Disable cap-less LDOs (1.5V) */
1230         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1231         /* Disable NCP */
1232         regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1233
1234         /* Set HP CMFB gate rstb */
1235         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1236                            0x1 << 6, 0x0);
1237         /* disable Pull-down HPL/R to AVSS28_AUD */
1238         hp_pull_down(priv, false);
1239
1240         return 0;
1241 }
1242
1243 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1244                        struct snd_kcontrol *kcontrol,
1245                        int event)
1246 {
1247         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1248         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1249         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1250         int device = DEVICE_HP;
1251
1252         dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1253                  __func__,
1254                  event,
1255                  priv->dev_counter[device],
1256                  mux);
1257
1258         switch (event) {
1259         case SND_SOC_DAPM_PRE_PMU:
1260                 priv->dev_counter[device]++;
1261                 if (priv->dev_counter[device] > 1)
1262                         break;  /* already enabled, do nothing */
1263                 else if (priv->dev_counter[device] <= 0)
1264                         dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1265                                  __func__,
1266                                  priv->dev_counter[device]);
1267
1268                 priv->mux_select[MUX_HP_L] = mux;
1269
1270                 if (mux == HP_MUX_HP)
1271                         mtk_hp_enable(priv);
1272                 else if (mux == HP_MUX_HPSPK)
1273                         mtk_hp_spk_enable(priv);
1274                 break;
1275         case SND_SOC_DAPM_PRE_PMD:
1276                 priv->dev_counter[device]--;
1277                 if (priv->dev_counter[device] > 0) {
1278                         break;  /* still being used, don't close */
1279                 } else if (priv->dev_counter[device] < 0) {
1280                         dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1281                                  __func__,
1282                                  priv->dev_counter[device]);
1283                         priv->dev_counter[device] = 0;
1284                         break;
1285                 }
1286
1287                 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1288                         mtk_hp_disable(priv);
1289                 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1290                         mtk_hp_spk_disable(priv);
1291
1292                 priv->mux_select[MUX_HP_L] = mux;
1293                 break;
1294         default:
1295                 break;
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1302                         struct snd_kcontrol *kcontrol,
1303                         int event)
1304 {
1305         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1306         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1307
1308         dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1309                  __func__,
1310                  event,
1311                  dapm_kcontrol_get_value(w->kcontrols[0]));
1312
1313         switch (event) {
1314         case SND_SOC_DAPM_PRE_PMU:
1315                 /* Reduce ESD resistance of AU_REFN */
1316                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1317
1318                 /* Turn on DA_600K_NCP_VA18 */
1319                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1320                 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1321                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1322                 /* Toggle RG_DIVCKS_CHG */
1323                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1324                 /* Set NCP soft start mode as default mode: 100us */
1325                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1326                 /* Enable NCP */
1327                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1328                 usleep_range(250, 270);
1329
1330                 /* Enable cap-less LDOs (1.5V) */
1331                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1332                                    0x1055, 0x1055);
1333                 /* Enable NV regulator (-1.2V) */
1334                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1335                 usleep_range(100, 120);
1336
1337                 /* Disable AUD_ZCD */
1338                 hp_zcd_disable(priv);
1339
1340                 /* Disable handset short-circuit protection */
1341                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1342
1343                 /* Enable IBIST */
1344                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1345                 /* Set HP DR bias current optimization, 010: 6uA */
1346                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1347                 /* Set HP & ZCD bias current optimization */
1348                 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1349                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1350                 /* Set HS STB enhance circuits */
1351                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1352
1353                 /* Disable HP main CMFB loop */
1354                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1355                 /* Select CMFB resistor bulk to AC mode */
1356                 /* Selec HS/LO cap size (6.5pF default) */
1357                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1358
1359                 /* Enable HS driver bias circuits */
1360                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1361                 /* Enable HS driver core circuits */
1362                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1363
1364                 /* Enable AUD_CLK */
1365                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1366                                    0x1, 0x1);
1367
1368                 /* Enable Audio DAC  */
1369                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1370                 /* Enable low-noise mode of DAC */
1371                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1372                 /* Switch HS MUX to audio DAC */
1373                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1374                 break;
1375         case SND_SOC_DAPM_PRE_PMD:
1376                 /* HS mux to open */
1377                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1378                                    RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1379                                    RCV_MUX_OPEN);
1380
1381                 /* Disable Audio DAC */
1382                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1383                                    0x000f, 0x0000);
1384
1385                 /* Disable AUD_CLK */
1386                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1387                                    0x1, 0x0);
1388
1389                 /* decrease HS gain to minimum gain step by step */
1390                 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1391
1392                 /* Disable HS driver core circuits */
1393                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1394                                    0x1, 0x0);
1395
1396                 /* Disable HS driver bias circuits */
1397                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1398                                    0x1 << 1, 0x0000);
1399
1400                 /* Disable HP aux CMFB loop */
1401                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1402                                    0xff << 8, 0x0);
1403
1404                 /* Enable HP main CMFB Switch */
1405                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1406                                    0xff << 8, 0x2 << 8);
1407
1408                 /* Disable IBIST */
1409                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1410                                    0x1 << 8, 0x1 << 8);
1411
1412                 /* Disable NV regulator (-1.2V) */
1413                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1414                                    0x1, 0x0);
1415                 /* Disable cap-less LDOs (1.5V) */
1416                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1417                                    0x1055, 0x0);
1418                 /* Disable NCP */
1419                 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1420                                    0x1, 0x1);
1421                 break;
1422         default:
1423                 break;
1424         }
1425
1426         return 0;
1427 }
1428
1429 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1430                             struct snd_kcontrol *kcontrol,
1431                             int event)
1432 {
1433         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1434         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1435
1436         dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1437                 __func__, event, priv->ul_rate);
1438
1439         switch (event) {
1440         case SND_SOC_DAPM_PRE_PMU:
1441                 capture_gpio_set(priv);
1442                 break;
1443         case SND_SOC_DAPM_POST_PMD:
1444                 capture_gpio_reset(priv);
1445                 break;
1446         default:
1447                 break;
1448         }
1449
1450         return 0;
1451 }
1452
1453 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1454                                struct snd_kcontrol *kcontrol,
1455                                int event)
1456 {
1457         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1458         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1459
1460         dev_dbg(priv->dev, "%s(), event 0x%x\n",
1461                 __func__, event);
1462
1463         switch (event) {
1464         case SND_SOC_DAPM_PRE_PMU:
1465                 /* Enable audio ADC CLKGEN  */
1466                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1467                                    0x1 << 5, 0x1 << 5);
1468                 /* ADC CLK from CLKGEN (13MHz) */
1469                 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1470                              0x0000);
1471                 /* Enable  LCLDO_ENC 1P8V */
1472                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1473                                    0x2500, 0x0100);
1474                 /* LCLDO_ENC remote sense */
1475                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1476                                    0x2500, 0x2500);
1477                 break;
1478         case SND_SOC_DAPM_POST_PMD:
1479                 /* LCLDO_ENC remote sense off */
1480                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1481                                    0x2500, 0x0100);
1482                 /* disable LCLDO_ENC 1P8V */
1483                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1484                                    0x2500, 0x0000);
1485
1486                 /* ADC CLK from CLKGEN (13MHz) */
1487                 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1488                 /* disable audio ADC CLKGEN  */
1489                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1490                                    0x1 << 5, 0x0 << 5);
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int mt6358_amic_enable(struct mt6358_priv *priv)
1500 {
1501         unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1502         unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1503         unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1504
1505         dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1506                  __func__, mic_type, mux_pga_l, mux_pga_r);
1507
1508         if (IS_DCC_BASE(mic_type)) {
1509                 /* DCC 50k CLK (from 26M) */
1510                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1511                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1512                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1513                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1514                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1515         }
1516
1517         /* mic bias 0 */
1518         if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1519             mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1520                 switch (mic_type) {
1521                 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1522                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1523                                            0xff00, 0x7700);
1524                         break;
1525                 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1526                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1527                                            0xff00, 0x1100);
1528                         break;
1529                 default:
1530                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1531                                            0xff00, 0x0000);
1532                         break;
1533                 }
1534                 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1535                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1536                                    0xff, 0x21);
1537         }
1538
1539         /* mic bias 1 */
1540         if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1541                 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1542                 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1543                         regmap_write(priv->regmap,
1544                                      MT6358_AUDENC_ANA_CON10, 0x0161);
1545                 else
1546                         regmap_write(priv->regmap,
1547                                      MT6358_AUDENC_ANA_CON10, 0x0061);
1548         }
1549
1550         if (IS_DCC_BASE(mic_type)) {
1551                 /* Audio L/R preamplifier DCC precharge */
1552                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1553                                    0xf8ff, 0x0004);
1554                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1555                                    0xf8ff, 0x0004);
1556         } else {
1557                 /* reset reg */
1558                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1559                                    0xf8ff, 0x0000);
1560                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1561                                    0xf8ff, 0x0000);
1562         }
1563
1564         if (mux_pga_l != PGA_MUX_NONE) {
1565                 /* L preamplifier input sel */
1566                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1567                                    RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1568                                    mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1569
1570                 /* L preamplifier enable */
1571                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1572                                    RG_AUDPREAMPLON_MASK_SFT,
1573                                    0x1 << RG_AUDPREAMPLON_SFT);
1574
1575                 if (IS_DCC_BASE(mic_type)) {
1576                         /* L preamplifier DCCEN */
1577                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1578                                            RG_AUDPREAMPLDCCEN_MASK_SFT,
1579                                            0x1 << RG_AUDPREAMPLDCCEN_SFT);
1580                 }
1581
1582                 /* L ADC input sel : L PGA. Enable audio L ADC */
1583                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1584                                    RG_AUDADCLINPUTSEL_MASK_SFT,
1585                                    ADC_MUX_PREAMPLIFIER <<
1586                                    RG_AUDADCLINPUTSEL_SFT);
1587                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1588                                    RG_AUDADCLPWRUP_MASK_SFT,
1589                                    0x1 << RG_AUDADCLPWRUP_SFT);
1590         }
1591
1592         if (mux_pga_r != PGA_MUX_NONE) {
1593                 /* R preamplifier input sel */
1594                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1595                                    RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1596                                    mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1597
1598                 /* R preamplifier enable */
1599                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1600                                    RG_AUDPREAMPRON_MASK_SFT,
1601                                    0x1 << RG_AUDPREAMPRON_SFT);
1602
1603                 if (IS_DCC_BASE(mic_type)) {
1604                         /* R preamplifier DCCEN */
1605                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1606                                            RG_AUDPREAMPRDCCEN_MASK_SFT,
1607                                            0x1 << RG_AUDPREAMPRDCCEN_SFT);
1608                 }
1609
1610                 /* R ADC input sel : R PGA. Enable audio R ADC */
1611                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1612                                    RG_AUDADCRINPUTSEL_MASK_SFT,
1613                                    ADC_MUX_PREAMPLIFIER <<
1614                                    RG_AUDADCRINPUTSEL_SFT);
1615                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1616                                    RG_AUDADCRPWRUP_MASK_SFT,
1617                                    0x1 << RG_AUDADCRPWRUP_SFT);
1618         }
1619
1620         if (IS_DCC_BASE(mic_type)) {
1621                 usleep_range(100, 150);
1622                 /* Audio L preamplifier DCC precharge off */
1623                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1624                                    RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1625                 /* Audio R preamplifier DCC precharge off */
1626                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1627                                    RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1628
1629                 /* Short body to ground in PGA */
1630                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1631                                    0x1 << 12, 0x0);
1632         }
1633
1634         /* here to set digital part */
1635         mt6358_mtkaif_tx_enable(priv);
1636
1637         /* UL dmic setting off */
1638         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1639
1640         /* UL turn on */
1641         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1642
1643         return 0;
1644 }
1645
1646 static void mt6358_amic_disable(struct mt6358_priv *priv)
1647 {
1648         unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1649         unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1650         unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1651
1652         dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1653                  __func__, mic_type, mux_pga_l, mux_pga_r);
1654
1655         /* UL turn off */
1656         regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1657                            0x0001, 0x0000);
1658
1659         /* disable aud_pad TX fifos */
1660         mt6358_mtkaif_tx_disable(priv);
1661
1662         /* L ADC input sel : off, disable L ADC */
1663         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1664                            0xf000, 0x0000);
1665         /* L preamplifier DCCEN */
1666         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1667                            0x1 << 1, 0x0);
1668         /* L preamplifier input sel : off, L PGA 0 dB gain */
1669         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1670                            0xfffb, 0x0000);
1671
1672         /* disable L preamplifier DCC precharge */
1673         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1674                            0x1 << 2, 0x0);
1675
1676         /* R ADC input sel : off, disable R ADC */
1677         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1678                            0xf000, 0x0000);
1679         /* R preamplifier DCCEN */
1680         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1681                            0x1 << 1, 0x0);
1682         /* R preamplifier input sel : off, R PGA 0 dB gain */
1683         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1684                            0x0ffb, 0x0000);
1685
1686         /* disable R preamplifier DCC precharge */
1687         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1688                            0x1 << 2, 0x0);
1689
1690         /* mic bias */
1691         /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1692         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1693
1694         /* Disable MICBIAS1 */
1695         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1696                            0x0001, 0x0000);
1697
1698         if (IS_DCC_BASE(mic_type)) {
1699                 /* dcclk_gen_on=1'b0 */
1700                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1701                 /* dcclk_pdn=1'b1 */
1702                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1703                 /* dcclk_ref_ck_sel=2'b00 */
1704                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1705                 /* dcclk_div=11'b00100000011 */
1706                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1707         }
1708 }
1709
1710 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1711 {
1712         dev_info(priv->dev, "%s()\n", __func__);
1713
1714         /* mic bias */
1715         /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1716         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1717
1718         /* RG_BANDGAPGEN=1'b0 */
1719         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1720                            0x1 << 12, 0x0);
1721
1722         /* DMIC enable */
1723         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1724
1725         /* here to set digital part */
1726         mt6358_mtkaif_tx_enable(priv);
1727
1728         /* UL dmic setting */
1729         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1730
1731         /* UL turn on */
1732         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1733         return 0;
1734 }
1735
1736 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1737 {
1738         dev_info(priv->dev, "%s()\n", __func__);
1739
1740         /* UL turn off */
1741         regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1742                            0x0003, 0x0000);
1743
1744         /* disable aud_pad TX fifos */
1745         mt6358_mtkaif_tx_disable(priv);
1746
1747         /* DMIC disable */
1748         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1749
1750         /* mic bias */
1751         /* MISBIAS0 = 1P7V */
1752         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1753
1754         /* RG_BANDGAPGEN=1'b0 */
1755         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1756                            0x1 << 12, 0x0);
1757
1758         /* MICBIA0 disable */
1759         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1760 }
1761
1762 static void mt6358_restore_pga(struct mt6358_priv *priv)
1763 {
1764         unsigned int gain_l, gain_r;
1765
1766         gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1767         gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1768
1769         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1770                            RG_AUDPREAMPLGAIN_MASK_SFT,
1771                            gain_l << RG_AUDPREAMPLGAIN_SFT);
1772         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1773                            RG_AUDPREAMPRGAIN_MASK_SFT,
1774                            gain_r << RG_AUDPREAMPRGAIN_SFT);
1775 }
1776
1777 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1778                              struct snd_kcontrol *kcontrol,
1779                              int event)
1780 {
1781         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1782         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1783         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1784
1785         dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1786                 __func__, event, mux);
1787
1788         switch (event) {
1789         case SND_SOC_DAPM_WILL_PMU:
1790                 priv->mux_select[MUX_MIC_TYPE] = mux;
1791                 break;
1792         case SND_SOC_DAPM_PRE_PMU:
1793                 switch (mux) {
1794                 case MIC_TYPE_MUX_DMIC:
1795                         mt6358_dmic_enable(priv);
1796                         break;
1797                 default:
1798                         mt6358_amic_enable(priv);
1799                         break;
1800                 }
1801                 mt6358_restore_pga(priv);
1802
1803                 break;
1804         case SND_SOC_DAPM_POST_PMD:
1805                 switch (priv->mux_select[MUX_MIC_TYPE]) {
1806                 case MIC_TYPE_MUX_DMIC:
1807                         mt6358_dmic_disable(priv);
1808                         break;
1809                 default:
1810                         mt6358_amic_disable(priv);
1811                         break;
1812                 }
1813
1814                 priv->mux_select[MUX_MIC_TYPE] = mux;
1815                 break;
1816         default:
1817                 break;
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1824                           struct snd_kcontrol *kcontrol,
1825                           int event)
1826 {
1827         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1828         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1829         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1830
1831         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1832                 __func__, event, mux);
1833
1834         priv->mux_select[MUX_ADC_L] = mux;
1835
1836         return 0;
1837 }
1838
1839 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1840                           struct snd_kcontrol *kcontrol,
1841                           int event)
1842 {
1843         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1844         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1845         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1846
1847         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1848                 __func__, event, mux);
1849
1850         priv->mux_select[MUX_ADC_R] = mux;
1851
1852         return 0;
1853 }
1854
1855 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1856                              struct snd_kcontrol *kcontrol,
1857                              int event)
1858 {
1859         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1860         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1861         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1862
1863         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1864                 __func__, event, mux);
1865
1866         priv->mux_select[MUX_PGA_L] = mux;
1867
1868         return 0;
1869 }
1870
1871 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1872                               struct snd_kcontrol *kcontrol,
1873                               int event)
1874 {
1875         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1876         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1877         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1878
1879         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1880                 __func__, event, mux);
1881
1882         priv->mux_select[MUX_PGA_R] = mux;
1883
1884         return 0;
1885 }
1886
1887 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1888                               struct snd_kcontrol *kcontrol,
1889                               int event)
1890 {
1891         switch (event) {
1892         case SND_SOC_DAPM_POST_PMU:
1893                 usleep_range(250, 270);
1894                 break;
1895         case SND_SOC_DAPM_PRE_PMD:
1896                 usleep_range(250, 270);
1897                 break;
1898         default:
1899                 break;
1900         }
1901
1902         return 0;
1903 }
1904
1905 /* DAPM Widgets */
1906 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
1907         /* Global Supply*/
1908         SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1909                               MT6358_DCXO_CW14,
1910                               RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1911         SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1912                               MT6358_AUDDEC_ANA_CON13,
1913                               RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1914         SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1915                               MT6358_AUDENC_ANA_CON6,
1916                               RG_CLKSQ_EN_SFT, 0,
1917                               mt_clksq_event,
1918                               SND_SOC_DAPM_PRE_PMU),
1919         SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1920                               MT6358_AUD_TOP_CKPDN_CON0,
1921                               RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1922         SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1923                               MT6358_AUD_TOP_CKPDN_CON0,
1924                               RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1925         SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1926                               MT6358_AUD_TOP_CKPDN_CON0,
1927                               RG_AUD_CK_PDN_SFT, 1,
1928                               mt_delay_250_event,
1929                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1930         SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1931                               MT6358_AUD_TOP_CKPDN_CON0,
1932                               RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1933
1934         /* Digital Clock */
1935         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1936                               MT6358_AUDIO_TOP_CON0,
1937                               PDN_AFE_CTL_SFT, 1,
1938                               mt_delay_250_event,
1939                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1940         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1941                               MT6358_AUDIO_TOP_CON0,
1942                               PDN_DAC_CTL_SFT, 1, NULL, 0),
1943         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1944                               MT6358_AUDIO_TOP_CON0,
1945                               PDN_ADC_CTL_SFT, 1, NULL, 0),
1946         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1947                               MT6358_AUDIO_TOP_CON0,
1948                               PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1949         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1950                               MT6358_AUDIO_TOP_CON0,
1951                               PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1952         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1953                               MT6358_AUDIO_TOP_CON0,
1954                               PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1955         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1956                               MT6358_AUDIO_TOP_CON0,
1957                               PDN_RESERVED_SFT, 1, NULL, 0),
1958
1959         SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1960                             0, 0, NULL, 0),
1961
1962         /* AFE ON */
1963         SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
1964                               MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
1965                               NULL, 0),
1966
1967         /* AIF Rx*/
1968         SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1969                               MT6358_AFE_DL_SRC2_CON0_L,
1970                               DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
1971                               mt_aif_in_event,
1972                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1973
1974         /* DL Supply */
1975         SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1976                             0, 0, NULL, 0),
1977
1978         /* DAC */
1979         SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1980
1981         SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
1982
1983         SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
1984
1985         /* LOL */
1986         SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1987
1988         SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
1989                             RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
1990
1991         SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
1992                              RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
1993
1994         /* Headphone */
1995         SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
1996                            &hpl_in_mux_control,
1997                            mt_hp_event,
1998                            SND_SOC_DAPM_PRE_PMU |
1999                            SND_SOC_DAPM_PRE_PMD),
2000
2001         SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2002                            &hpr_in_mux_control,
2003                            mt_hp_event,
2004                            SND_SOC_DAPM_PRE_PMU |
2005                            SND_SOC_DAPM_PRE_PMD),
2006
2007         /* Receiver */
2008         SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2009                            &rcv_in_mux_control,
2010                            mt_rcv_event,
2011                            SND_SOC_DAPM_PRE_PMU |
2012                            SND_SOC_DAPM_PRE_PMD),
2013
2014         /* Outputs */
2015         SND_SOC_DAPM_OUTPUT("Receiver"),
2016         SND_SOC_DAPM_OUTPUT("Headphone L"),
2017         SND_SOC_DAPM_OUTPUT("Headphone R"),
2018         SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2019         SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2020         SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2021         SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2022
2023         /* SGEN */
2024         SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2025                             SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2026         SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2027                             SGEN_MUTE_SW_CTL_SFT, 1,
2028                             mt_sgen_event,
2029                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2030         SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2031                             DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2032
2033         SND_SOC_DAPM_INPUT("SGEN DL"),
2034
2035         /* Uplinks */
2036         SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2037                                SND_SOC_NOPM, 0, 0,
2038                                mt_aif_out_event,
2039                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2040
2041         SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2042                               SND_SOC_NOPM, 0, 0,
2043                               mt_adc_supply_event,
2044                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2045
2046         /* Uplinks MUX */
2047         SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2048                          &aif_out_mux_control),
2049
2050         SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2051                            &mic_type_mux_control,
2052                            mt_mic_type_event,
2053                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2054                            SND_SOC_DAPM_WILL_PMU),
2055
2056         SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2057                            &adc_left_mux_control,
2058                            mt_adc_l_event,
2059                            SND_SOC_DAPM_WILL_PMU),
2060         SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2061                            &adc_right_mux_control,
2062                            mt_adc_r_event,
2063                            SND_SOC_DAPM_WILL_PMU),
2064
2065         SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2066         SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2067
2068         SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2069                            &pga_left_mux_control,
2070                            mt_pga_left_event,
2071                            SND_SOC_DAPM_WILL_PMU),
2072         SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2073                            &pga_right_mux_control,
2074                            mt_pga_right_event,
2075                            SND_SOC_DAPM_WILL_PMU),
2076
2077         SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2078         SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2079
2080         /* UL input */
2081         SND_SOC_DAPM_INPUT("AIN0"),
2082         SND_SOC_DAPM_INPUT("AIN1"),
2083         SND_SOC_DAPM_INPUT("AIN2"),
2084 };
2085
2086 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2087         /* Capture */
2088         {"AIF1TX", NULL, "AIF Out Mux"},
2089         {"AIF1TX", NULL, "CLK_BUF"},
2090         {"AIF1TX", NULL, "AUDGLB"},
2091         {"AIF1TX", NULL, "CLKSQ Audio"},
2092
2093         {"AIF1TX", NULL, "AUD_CK"},
2094         {"AIF1TX", NULL, "AUDIF_CK"},
2095
2096         {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2097         {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2098         {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2099         {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2100         {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2101
2102         {"AIF1TX", NULL, "AFE_ON"},
2103
2104         {"AIF Out Mux", NULL, "Mic Type Mux"},
2105
2106         {"Mic Type Mux", "ACC", "ADC L"},
2107         {"Mic Type Mux", "ACC", "ADC R"},
2108         {"Mic Type Mux", "DCC", "ADC L"},
2109         {"Mic Type Mux", "DCC", "ADC R"},
2110         {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2111         {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2112         {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2113         {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2114         {"Mic Type Mux", "DMIC", "AIN0"},
2115         {"Mic Type Mux", "DMIC", "AIN2"},
2116
2117         {"ADC L", NULL, "ADC L Mux"},
2118         {"ADC L", NULL, "ADC Supply"},
2119         {"ADC R", NULL, "ADC R Mux"},
2120         {"ADC R", NULL, "ADC Supply"},
2121
2122         {"ADC L Mux", "Left Preamplifier", "PGA L"},
2123
2124         {"ADC R Mux", "Right Preamplifier", "PGA R"},
2125
2126         {"PGA L", NULL, "PGA L Mux"},
2127         {"PGA R", NULL, "PGA R Mux"},
2128
2129         {"PGA L Mux", "AIN0", "AIN0"},
2130         {"PGA L Mux", "AIN1", "AIN1"},
2131         {"PGA L Mux", "AIN2", "AIN2"},
2132
2133         {"PGA R Mux", "AIN0", "AIN0"},
2134         {"PGA R Mux", "AIN1", "AIN1"},
2135         {"PGA R Mux", "AIN2", "AIN2"},
2136
2137         /* DL Supply */
2138         {"DL Power Supply", NULL, "CLK_BUF"},
2139         {"DL Power Supply", NULL, "AUDGLB"},
2140         {"DL Power Supply", NULL, "CLKSQ Audio"},
2141
2142         {"DL Power Supply", NULL, "AUDNCP_CK"},
2143         {"DL Power Supply", NULL, "ZCD13M_CK"},
2144         {"DL Power Supply", NULL, "AUD_CK"},
2145         {"DL Power Supply", NULL, "AUDIF_CK"},
2146
2147         /* DL Digital Supply */
2148         {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2149         {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2150         {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2151
2152         {"DL Digital Clock", NULL, "AFE_ON"},
2153
2154         {"AIF_RX", NULL, "DL Digital Clock"},
2155
2156         /* DL Path */
2157         {"DAC In Mux", "Normal Path", "AIF_RX"},
2158
2159         {"DAC In Mux", "Sgen", "SGEN DL"},
2160         {"SGEN DL", NULL, "SGEN DL SRC"},
2161         {"SGEN DL", NULL, "SGEN MUTE"},
2162         {"SGEN DL", NULL, "SGEN DL Enable"},
2163         {"SGEN DL", NULL, "DL Digital Clock"},
2164         {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2165
2166         {"DACL", NULL, "DAC In Mux"},
2167         {"DACL", NULL, "DL Power Supply"},
2168
2169         {"DACR", NULL, "DAC In Mux"},
2170         {"DACR", NULL, "DL Power Supply"},
2171
2172         /* Lineout Path */
2173         {"LOL Mux", "Playback", "DACL"},
2174
2175         {"LOL Buffer", NULL, "LOL Mux"},
2176         {"LOL Buffer", NULL, "LO Stability Enh"},
2177
2178         {"LINEOUT L", NULL, "LOL Buffer"},
2179
2180         /* Headphone Path */
2181         {"HPL Mux", "Audio Playback", "DACL"},
2182         {"HPR Mux", "Audio Playback", "DACR"},
2183         {"HPL Mux", "HP Impedance", "DACL"},
2184         {"HPR Mux", "HP Impedance", "DACR"},
2185         {"HPL Mux", "LoudSPK Playback", "DACL"},
2186         {"HPR Mux", "LoudSPK Playback", "DACR"},
2187
2188         {"Headphone L", NULL, "HPL Mux"},
2189         {"Headphone R", NULL, "HPR Mux"},
2190         {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2191         {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2192         {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2193
2194         /* Receiver Path */
2195         {"RCV Mux", "Voice Playback", "DACL"},
2196         {"Receiver", NULL, "RCV Mux"},
2197 };
2198
2199 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2200                                       struct snd_pcm_hw_params *params,
2201                                       struct snd_soc_dai *dai)
2202 {
2203         struct snd_soc_component *cmpnt = dai->component;
2204         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2205         unsigned int rate = params_rate(params);
2206
2207         dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2208                  __func__,
2209                  substream->stream,
2210                  rate,
2211                  substream->number);
2212
2213         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2214                 priv->dl_rate = rate;
2215         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2216                 priv->ul_rate = rate;
2217
2218         return 0;
2219 }
2220
2221 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2222         .hw_params = mt6358_codec_dai_hw_params,
2223 };
2224
2225 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2226                         SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2227                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2228                         SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2229                         SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2230                         SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2231
2232 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2233         {
2234                 .name = "mt6358-snd-codec-aif1",
2235                 .playback = {
2236                         .stream_name = "AIF1 Playback",
2237                         .channels_min = 1,
2238                         .channels_max = 2,
2239                         .rates = SNDRV_PCM_RATE_8000_48000 |
2240                                  SNDRV_PCM_RATE_96000 |
2241                                  SNDRV_PCM_RATE_192000,
2242                         .formats = MT6358_FORMATS,
2243                 },
2244                 .capture = {
2245                         .stream_name = "AIF1 Capture",
2246                         .channels_min = 1,
2247                         .channels_max = 2,
2248                         .rates = SNDRV_PCM_RATE_8000 |
2249                                  SNDRV_PCM_RATE_16000 |
2250                                  SNDRV_PCM_RATE_32000 |
2251                                  SNDRV_PCM_RATE_48000,
2252                         .formats = MT6358_FORMATS,
2253                 },
2254                 .ops = &mt6358_codec_dai_ops,
2255         },
2256 };
2257
2258 static int mt6358_codec_init_reg(struct mt6358_priv *priv)
2259 {
2260         int ret = 0;
2261
2262         /* Disable HeadphoneL/HeadphoneR short circuit protection */
2263         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2264                            RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2265                            0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2266         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2267                            RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2268                            0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2269         /* Disable voice short circuit protection */
2270         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2271                            RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2272                            0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2273         /* disable LO buffer left short circuit protection */
2274         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2275                            RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2276                            0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2277
2278         /* accdet s/w enable */
2279         regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2280                            0xFFFF, 0x700E);
2281
2282         /* gpio miso driving set to 4mA */
2283         regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2284
2285         /* set gpio */
2286         playback_gpio_reset(priv);
2287         capture_gpio_reset(priv);
2288
2289         return ret;
2290 }
2291
2292 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2293 {
2294         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2295         int ret;
2296
2297         snd_soc_component_init_regmap(cmpnt, priv->regmap);
2298
2299         mt6358_codec_init_reg(priv);
2300
2301         priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2302         if (IS_ERR(priv->avdd_reg)) {
2303                 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2304                 return PTR_ERR(priv->avdd_reg);
2305         }
2306
2307         ret = regulator_enable(priv->avdd_reg);
2308         if (ret)
2309                 return  ret;
2310
2311         return 0;
2312 }
2313
2314 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2315         .probe = mt6358_codec_probe,
2316         .controls = mt6358_snd_controls,
2317         .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2318         .dapm_widgets = mt6358_dapm_widgets,
2319         .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2320         .dapm_routes = mt6358_dapm_routes,
2321         .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2322 };
2323
2324 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2325 {
2326         struct mt6358_priv *priv;
2327         struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2328
2329         priv = devm_kzalloc(&pdev->dev,
2330                             sizeof(struct mt6358_priv),
2331                             GFP_KERNEL);
2332         if (!priv)
2333                 return -ENOMEM;
2334
2335         dev_set_drvdata(&pdev->dev, priv);
2336
2337         priv->dev = &pdev->dev;
2338
2339         priv->regmap = mt6397->regmap;
2340         if (IS_ERR(priv->regmap))
2341                 return PTR_ERR(priv->regmap);
2342
2343         dev_info(priv->dev, "%s(), dev name %s\n",
2344                  __func__, dev_name(&pdev->dev));
2345
2346         return devm_snd_soc_register_component(&pdev->dev,
2347                                       &mt6358_soc_component_driver,
2348                                       mt6358_dai_driver,
2349                                       ARRAY_SIZE(mt6358_dai_driver));
2350 }
2351
2352 static const struct of_device_id mt6358_of_match[] = {
2353         {.compatible = "mediatek,mt6358-sound",},
2354         {}
2355 };
2356 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2357
2358 static struct platform_driver mt6358_platform_driver = {
2359         .driver = {
2360                 .name = "mt6358-sound",
2361                 .of_match_table = mt6358_of_match,
2362         },
2363         .probe = mt6358_platform_driver_probe,
2364 };
2365
2366 module_platform_driver(mt6358_platform_driver)
2367
2368 /* Module information */
2369 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2370 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2371 MODULE_LICENSE("GPL v2");