2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 #define RT5663_DEVICE_ID_2 0x6451
34 #define RT5663_DEVICE_ID_1 0x6406
41 struct impedance_mapping_table {
45 unsigned int dc_offset_l_manual;
46 unsigned int dc_offset_r_manual;
47 unsigned int dc_offset_l_manual_mic;
48 unsigned int dc_offset_r_manual_mic;
52 struct snd_soc_codec *codec;
53 struct rt5663_platform_data pdata;
54 struct regmap *regmap;
55 struct delayed_work jack_detect_work, jd_unplug_work;
56 struct snd_soc_jack *hs_jack;
57 struct timer_list btn_check_timer;
58 struct impedance_mapping_table *imp_table;
72 static const struct reg_sequence rt5663_patch_list[] = {
77 static const struct reg_default rt5663_v2_reg[] = {
479 static const struct reg_default rt5663_reg[] = {
737 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
741 case RT5663_SIL_DET_CTL:
742 case RT5663_HP_IMP_GAIN_2:
743 case RT5663_AD_DA_MIXER:
744 case RT5663_FRAC_DIV_2:
745 case RT5663_MICBIAS_1:
746 case RT5663_ASRC_11_2:
747 case RT5663_ADC_EQ_1:
748 case RT5663_INT_ST_1:
749 case RT5663_INT_ST_2:
750 case RT5663_GPIO_STA1:
751 case RT5663_SIN_GEN_1:
752 case RT5663_IL_CMD_1:
753 case RT5663_IL_CMD_5:
754 case RT5663_IL_CMD_PWRSAV1:
755 case RT5663_EM_JACK_TYPE_1:
756 case RT5663_EM_JACK_TYPE_2:
757 case RT5663_EM_JACK_TYPE_3:
758 case RT5663_JD_CTRL2:
759 case RT5663_VENDOR_ID:
760 case RT5663_VENDOR_ID_1:
761 case RT5663_VENDOR_ID_2:
762 case RT5663_PLL_INT_REG:
763 case RT5663_SOFT_RAMP:
764 case RT5663_STO_DRE_1:
765 case RT5663_STO_DRE_5:
766 case RT5663_STO_DRE_6:
767 case RT5663_STO_DRE_7:
768 case RT5663_MIC_DECRO_1:
769 case RT5663_MIC_DECRO_4:
770 case RT5663_HP_IMP_SEN_1:
771 case RT5663_HP_IMP_SEN_3:
772 case RT5663_HP_IMP_SEN_4:
773 case RT5663_HP_IMP_SEN_5:
774 case RT5663_HP_CALIB_1_1:
775 case RT5663_HP_CALIB_9:
776 case RT5663_HP_CALIB_ST1:
777 case RT5663_HP_CALIB_ST2:
778 case RT5663_HP_CALIB_ST3:
779 case RT5663_HP_CALIB_ST4:
780 case RT5663_HP_CALIB_ST5:
781 case RT5663_HP_CALIB_ST6:
782 case RT5663_HP_CALIB_ST7:
783 case RT5663_HP_CALIB_ST8:
784 case RT5663_HP_CALIB_ST9:
792 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
796 case RT5663_HP_OUT_EN:
797 case RT5663_HP_LCH_DRE:
798 case RT5663_HP_RCH_DRE:
799 case RT5663_CALIB_BST:
801 case RT5663_SIL_DET_CTL:
802 case RT5663_PWR_SAV_SILDET:
803 case RT5663_SIDETONE_CTL:
804 case RT5663_STO1_DAC_DIG_VOL:
805 case RT5663_STO1_ADC_DIG_VOL:
806 case RT5663_STO1_BOOST:
807 case RT5663_HP_IMP_GAIN_1:
808 case RT5663_HP_IMP_GAIN_2:
809 case RT5663_STO1_ADC_MIXER:
810 case RT5663_AD_DA_MIXER:
811 case RT5663_STO_DAC_MIXER:
812 case RT5663_DIG_SIDE_MIXER:
813 case RT5663_BYPASS_STO_DAC:
814 case RT5663_CALIB_REC_MIX:
815 case RT5663_PWR_DIG_1:
816 case RT5663_PWR_DIG_2:
817 case RT5663_PWR_ANLG_1:
818 case RT5663_PWR_ANLG_2:
819 case RT5663_PWR_ANLG_3:
820 case RT5663_PWR_MIXER:
821 case RT5663_SIG_CLK_DET:
822 case RT5663_PRE_DIV_GATING_1:
823 case RT5663_PRE_DIV_GATING_2:
824 case RT5663_I2S1_SDP:
825 case RT5663_ADDA_CLK_1:
826 case RT5663_ADDA_RST:
827 case RT5663_FRAC_DIV_1:
828 case RT5663_FRAC_DIV_2:
840 case RT5663_DUMMY_REG:
847 case RT5663_HP_CHARGE_PUMP_1:
848 case RT5663_HP_CHARGE_PUMP_2:
849 case RT5663_MICBIAS_1:
851 case RT5663_ASRC_11_2:
852 case RT5663_DUMMY_REG_2:
853 case RT5663_REC_PATH_GAIN:
854 case RT5663_AUTO_1MRC_CLK:
855 case RT5663_ADC_EQ_1:
856 case RT5663_ADC_EQ_2:
862 case RT5663_INT_ST_1:
863 case RT5663_INT_ST_2:
866 case RT5663_GPIO_STA1:
867 case RT5663_SIN_GEN_1:
868 case RT5663_SIN_GEN_2:
869 case RT5663_SIN_GEN_3:
870 case RT5663_SOF_VOL_ZC1:
871 case RT5663_IL_CMD_1:
872 case RT5663_IL_CMD_2:
873 case RT5663_IL_CMD_3:
874 case RT5663_IL_CMD_4:
875 case RT5663_IL_CMD_5:
876 case RT5663_IL_CMD_6:
877 case RT5663_IL_CMD_7:
878 case RT5663_IL_CMD_8:
879 case RT5663_IL_CMD_PWRSAV1:
880 case RT5663_IL_CMD_PWRSAV2:
881 case RT5663_EM_JACK_TYPE_1:
882 case RT5663_EM_JACK_TYPE_2:
883 case RT5663_EM_JACK_TYPE_3:
884 case RT5663_EM_JACK_TYPE_4:
885 case RT5663_EM_JACK_TYPE_5:
886 case RT5663_EM_JACK_TYPE_6:
887 case RT5663_STO1_HPF_ADJ1:
888 case RT5663_STO1_HPF_ADJ2:
889 case RT5663_FAST_OFF_MICBIAS:
890 case RT5663_JD_CTRL1:
891 case RT5663_JD_CTRL2:
892 case RT5663_DIG_MISC:
893 case RT5663_VENDOR_ID:
894 case RT5663_VENDOR_ID_1:
895 case RT5663_VENDOR_ID_2:
896 case RT5663_DIG_VOL_ZCD:
897 case RT5663_ANA_BIAS_CUR_1:
898 case RT5663_ANA_BIAS_CUR_2:
899 case RT5663_ANA_BIAS_CUR_3:
900 case RT5663_ANA_BIAS_CUR_4:
901 case RT5663_ANA_BIAS_CUR_5:
902 case RT5663_ANA_BIAS_CUR_6:
903 case RT5663_BIAS_CUR_5:
904 case RT5663_BIAS_CUR_6:
905 case RT5663_BIAS_CUR_7:
906 case RT5663_BIAS_CUR_8:
907 case RT5663_DACREF_LDO:
908 case RT5663_DUMMY_REG_3:
909 case RT5663_BIAS_CUR_9:
910 case RT5663_DUMMY_REG_4:
911 case RT5663_VREFADJ_OP:
912 case RT5663_VREF_RECMIX:
913 case RT5663_CHARGE_PUMP_1:
914 case RT5663_CHARGE_PUMP_1_2:
915 case RT5663_CHARGE_PUMP_1_3:
916 case RT5663_CHARGE_PUMP_2:
917 case RT5663_DIG_IN_PIN1:
918 case RT5663_PAD_DRV_CTL:
919 case RT5663_PLL_INT_REG:
920 case RT5663_CHOP_DAC_L:
921 case RT5663_CHOP_ADC:
922 case RT5663_CALIB_ADC:
923 case RT5663_CHOP_DAC_R:
924 case RT5663_DUMMY_CTL_DACLR:
925 case RT5663_DUMMY_REG_5:
926 case RT5663_SOFT_RAMP:
927 case RT5663_TEST_MODE_1:
928 case RT5663_TEST_MODE_2:
929 case RT5663_TEST_MODE_3:
930 case RT5663_STO_DRE_1:
931 case RT5663_STO_DRE_2:
932 case RT5663_STO_DRE_3:
933 case RT5663_STO_DRE_4:
934 case RT5663_STO_DRE_5:
935 case RT5663_STO_DRE_6:
936 case RT5663_STO_DRE_7:
937 case RT5663_STO_DRE_8:
938 case RT5663_STO_DRE_9:
939 case RT5663_STO_DRE_10:
940 case RT5663_MIC_DECRO_1:
941 case RT5663_MIC_DECRO_2:
942 case RT5663_MIC_DECRO_3:
943 case RT5663_MIC_DECRO_4:
944 case RT5663_MIC_DECRO_5:
945 case RT5663_MIC_DECRO_6:
946 case RT5663_HP_DECRO_1:
947 case RT5663_HP_DECRO_2:
948 case RT5663_HP_DECRO_3:
949 case RT5663_HP_DECRO_4:
950 case RT5663_HP_DECOUP:
951 case RT5663_HP_IMP_SEN_MAP8:
952 case RT5663_HP_IMP_SEN_MAP9:
953 case RT5663_HP_IMP_SEN_MAP10:
954 case RT5663_HP_IMP_SEN_MAP11:
955 case RT5663_HP_IMP_SEN_1:
956 case RT5663_HP_IMP_SEN_2:
957 case RT5663_HP_IMP_SEN_3:
958 case RT5663_HP_IMP_SEN_4:
959 case RT5663_HP_IMP_SEN_5:
960 case RT5663_HP_IMP_SEN_6:
961 case RT5663_HP_IMP_SEN_7:
962 case RT5663_HP_IMP_SEN_8:
963 case RT5663_HP_IMP_SEN_9:
964 case RT5663_HP_IMP_SEN_10:
965 case RT5663_HP_IMP_SEN_11:
966 case RT5663_HP_IMP_SEN_12:
967 case RT5663_HP_IMP_SEN_13:
968 case RT5663_HP_IMP_SEN_14:
969 case RT5663_HP_IMP_SEN_15:
970 case RT5663_HP_IMP_SEN_16:
971 case RT5663_HP_IMP_SEN_17:
972 case RT5663_HP_IMP_SEN_18:
973 case RT5663_HP_IMP_SEN_19:
974 case RT5663_HP_IMPSEN_DIG5:
975 case RT5663_HP_IMPSEN_MAP1:
976 case RT5663_HP_IMPSEN_MAP2:
977 case RT5663_HP_IMPSEN_MAP3:
978 case RT5663_HP_IMPSEN_MAP4:
979 case RT5663_HP_IMPSEN_MAP5:
980 case RT5663_HP_IMPSEN_MAP7:
981 case RT5663_HP_LOGIC_1:
982 case RT5663_HP_LOGIC_2:
983 case RT5663_HP_CALIB_1:
984 case RT5663_HP_CALIB_1_1:
985 case RT5663_HP_CALIB_2:
986 case RT5663_HP_CALIB_3:
987 case RT5663_HP_CALIB_4:
988 case RT5663_HP_CALIB_5:
989 case RT5663_HP_CALIB_5_1:
990 case RT5663_HP_CALIB_6:
991 case RT5663_HP_CALIB_7:
992 case RT5663_HP_CALIB_9:
993 case RT5663_HP_CALIB_10:
994 case RT5663_HP_CALIB_11:
995 case RT5663_HP_CALIB_ST1:
996 case RT5663_HP_CALIB_ST2:
997 case RT5663_HP_CALIB_ST3:
998 case RT5663_HP_CALIB_ST4:
999 case RT5663_HP_CALIB_ST5:
1000 case RT5663_HP_CALIB_ST6:
1001 case RT5663_HP_CALIB_ST7:
1002 case RT5663_HP_CALIB_ST8:
1003 case RT5663_HP_CALIB_ST9:
1004 case RT5663_HP_AMP_DET:
1005 case RT5663_DUMMY_REG_6:
1006 case RT5663_HP_BIAS:
1010 case RT5663_DUMMY_1:
1011 case RT5663_DUMMY_2:
1012 case RT5663_DUMMY_3:
1014 case RT5663_ADC_LCH_LPF1_A1:
1015 case RT5663_ADC_RCH_LPF1_A1:
1016 case RT5663_ADC_LCH_LPF1_H0:
1017 case RT5663_ADC_RCH_LPF1_H0:
1018 case RT5663_ADC_LCH_BPF1_A1:
1019 case RT5663_ADC_RCH_BPF1_A1:
1020 case RT5663_ADC_LCH_BPF1_A2:
1021 case RT5663_ADC_RCH_BPF1_A2:
1022 case RT5663_ADC_LCH_BPF1_H0:
1023 case RT5663_ADC_RCH_BPF1_H0:
1024 case RT5663_ADC_LCH_BPF2_A1:
1025 case RT5663_ADC_RCH_BPF2_A1:
1026 case RT5663_ADC_LCH_BPF2_A2:
1027 case RT5663_ADC_RCH_BPF2_A2:
1028 case RT5663_ADC_LCH_BPF2_H0:
1029 case RT5663_ADC_RCH_BPF2_H0:
1030 case RT5663_ADC_LCH_BPF3_A1:
1031 case RT5663_ADC_RCH_BPF3_A1:
1032 case RT5663_ADC_LCH_BPF3_A2:
1033 case RT5663_ADC_RCH_BPF3_A2:
1034 case RT5663_ADC_LCH_BPF3_H0:
1035 case RT5663_ADC_RCH_BPF3_H0:
1036 case RT5663_ADC_LCH_BPF4_A1:
1037 case RT5663_ADC_RCH_BPF4_A1:
1038 case RT5663_ADC_LCH_BPF4_A2:
1039 case RT5663_ADC_RCH_BPF4_A2:
1040 case RT5663_ADC_LCH_BPF4_H0:
1041 case RT5663_ADC_RCH_BPF4_H0:
1042 case RT5663_ADC_LCH_HPF1_A1:
1043 case RT5663_ADC_RCH_HPF1_A1:
1044 case RT5663_ADC_LCH_HPF1_H0:
1045 case RT5663_ADC_RCH_HPF1_H0:
1046 case RT5663_ADC_EQ_PRE_VOL_L:
1047 case RT5663_ADC_EQ_PRE_VOL_R:
1048 case RT5663_ADC_EQ_POST_VOL_L:
1049 case RT5663_ADC_EQ_POST_VOL_R:
1056 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1060 case RT5663_CBJ_TYPE_2:
1061 case RT5663_PDM_OUT_CTL:
1062 case RT5663_PDM_I2C_DATA_CTL1:
1063 case RT5663_PDM_I2C_DATA_CTL4:
1064 case RT5663_ALC_BK_GAIN:
1066 case RT5663_MICBIAS_1:
1067 case RT5663_ADC_EQ_1:
1068 case RT5663_INT_ST_1:
1069 case RT5663_GPIO_STA2:
1070 case RT5663_IL_CMD_1:
1071 case RT5663_IL_CMD_5:
1072 case RT5663_A_JD_CTRL:
1073 case RT5663_JD_CTRL2:
1074 case RT5663_VENDOR_ID:
1075 case RT5663_VENDOR_ID_1:
1076 case RT5663_VENDOR_ID_2:
1077 case RT5663_STO_DRE_1:
1078 case RT5663_STO_DRE_5:
1079 case RT5663_STO_DRE_6:
1080 case RT5663_STO_DRE_7:
1081 case RT5663_MONO_DYNA_6:
1082 case RT5663_STO1_SIL_DET:
1083 case RT5663_MONOL_SIL_DET:
1084 case RT5663_MONOR_SIL_DET:
1085 case RT5663_STO2_DAC_SIL:
1086 case RT5663_MONO_AMP_CAL_ST1:
1087 case RT5663_MONO_AMP_CAL_ST2:
1088 case RT5663_MONO_AMP_CAL_ST3:
1089 case RT5663_MONO_AMP_CAL_ST4:
1090 case RT5663_HP_IMP_SEN_2:
1091 case RT5663_HP_IMP_SEN_3:
1092 case RT5663_HP_IMP_SEN_4:
1093 case RT5663_HP_IMP_SEN_10:
1094 case RT5663_HP_CALIB_1:
1095 case RT5663_HP_CALIB_10:
1096 case RT5663_HP_CALIB_ST1:
1097 case RT5663_HP_CALIB_ST4:
1098 case RT5663_HP_CALIB_ST5:
1099 case RT5663_HP_CALIB_ST6:
1100 case RT5663_HP_CALIB_ST7:
1101 case RT5663_HP_CALIB_ST8:
1102 case RT5663_HP_CALIB_ST9:
1103 case RT5663_HP_CALIB_ST10:
1104 case RT5663_HP_CALIB_ST11:
1111 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1114 case RT5663_LOUT_CTRL:
1115 case RT5663_HP_AMP_2:
1116 case RT5663_MONO_OUT:
1117 case RT5663_MONO_GAIN:
1118 case RT5663_AEC_BST:
1119 case RT5663_IN1_IN2:
1120 case RT5663_IN3_IN4:
1121 case RT5663_INL1_INR1:
1122 case RT5663_CBJ_TYPE_2:
1123 case RT5663_CBJ_TYPE_3:
1124 case RT5663_CBJ_TYPE_4:
1125 case RT5663_CBJ_TYPE_5:
1126 case RT5663_CBJ_TYPE_8:
1127 case RT5663_DAC3_DIG_VOL:
1128 case RT5663_DAC3_CTRL:
1129 case RT5663_MONO_ADC_DIG_VOL:
1130 case RT5663_STO2_ADC_DIG_VOL:
1131 case RT5663_MONO_ADC_BST_GAIN:
1132 case RT5663_STO2_ADC_BST_GAIN:
1133 case RT5663_SIDETONE_CTRL:
1134 case RT5663_MONO1_ADC_MIXER:
1135 case RT5663_STO2_ADC_MIXER:
1136 case RT5663_MONO_DAC_MIXER:
1137 case RT5663_DAC2_SRC_CTRL:
1138 case RT5663_IF_3_4_DATA_CTL:
1139 case RT5663_IF_5_DATA_CTL:
1140 case RT5663_PDM_OUT_CTL:
1141 case RT5663_PDM_I2C_DATA_CTL1:
1142 case RT5663_PDM_I2C_DATA_CTL2:
1143 case RT5663_PDM_I2C_DATA_CTL3:
1144 case RT5663_PDM_I2C_DATA_CTL4:
1145 case RT5663_RECMIX1_NEW:
1146 case RT5663_RECMIX1L_0:
1147 case RT5663_RECMIX1L:
1148 case RT5663_RECMIX1R_0:
1149 case RT5663_RECMIX1R:
1150 case RT5663_RECMIX2_NEW:
1151 case RT5663_RECMIX2_L_2:
1152 case RT5663_RECMIX2_R:
1153 case RT5663_RECMIX2_R_2:
1154 case RT5663_CALIB_REC_LR:
1155 case RT5663_ALC_BK_GAIN:
1156 case RT5663_MONOMIX_GAIN:
1157 case RT5663_MONOMIX_IN_GAIN:
1158 case RT5663_OUT_MIXL_GAIN:
1159 case RT5663_OUT_LMIX_IN_GAIN:
1160 case RT5663_OUT_RMIX_IN_GAIN:
1161 case RT5663_OUT_RMIX_IN_GAIN1:
1162 case RT5663_LOUT_MIXER_CTRL:
1163 case RT5663_PWR_VOL:
1164 case RT5663_ADCDAC_RST:
1165 case RT5663_I2S34_SDP:
1166 case RT5663_I2S5_SDP:
1174 case RT5663_PLL_TRK_13:
1175 case RT5663_I2S_M_CLK_CTL:
1176 case RT5663_FDIV_I2S34_M_CLK:
1177 case RT5663_FDIV_I2S34_M_CLK2:
1178 case RT5663_FDIV_I2S5_M_CLK:
1179 case RT5663_FDIV_I2S5_M_CLK2:
1180 case RT5663_V2_IRQ_4:
1183 case RT5663_GPIO_STA2:
1184 case RT5663_HP_AMP_DET1:
1185 case RT5663_HP_AMP_DET2:
1186 case RT5663_HP_AMP_DET3:
1187 case RT5663_MID_BD_HP_AMP:
1188 case RT5663_LOW_BD_HP_AMP:
1189 case RT5663_SOF_VOL_ZC2:
1190 case RT5663_ADC_STO2_ADJ1:
1191 case RT5663_ADC_STO2_ADJ2:
1192 case RT5663_A_JD_CTRL:
1193 case RT5663_JD1_TRES_CTRL:
1194 case RT5663_JD2_TRES_CTRL:
1195 case RT5663_V2_JD_CTRL2:
1196 case RT5663_DUM_REG_2:
1197 case RT5663_DUM_REG_3:
1198 case RT5663_VENDOR_ID:
1199 case RT5663_VENDOR_ID_1:
1200 case RT5663_VENDOR_ID_2:
1201 case RT5663_DACADC_DIG_VOL2:
1202 case RT5663_DIG_IN_PIN2:
1203 case RT5663_PAD_DRV_CTL1:
1204 case RT5663_SOF_RAM_DEPOP:
1205 case RT5663_VOL_TEST:
1206 case RT5663_TEST_MODE_4:
1207 case RT5663_TEST_MODE_5:
1208 case RT5663_STO_DRE_9:
1209 case RT5663_MONO_DYNA_1:
1210 case RT5663_MONO_DYNA_2:
1211 case RT5663_MONO_DYNA_3:
1212 case RT5663_MONO_DYNA_4:
1213 case RT5663_MONO_DYNA_5:
1214 case RT5663_MONO_DYNA_6:
1215 case RT5663_STO1_SIL_DET:
1216 case RT5663_MONOL_SIL_DET:
1217 case RT5663_MONOR_SIL_DET:
1218 case RT5663_STO2_DAC_SIL:
1219 case RT5663_PWR_SAV_CTL1:
1220 case RT5663_PWR_SAV_CTL2:
1221 case RT5663_PWR_SAV_CTL3:
1222 case RT5663_PWR_SAV_CTL4:
1223 case RT5663_PWR_SAV_CTL5:
1224 case RT5663_PWR_SAV_CTL6:
1225 case RT5663_MONO_AMP_CAL1:
1226 case RT5663_MONO_AMP_CAL2:
1227 case RT5663_MONO_AMP_CAL3:
1228 case RT5663_MONO_AMP_CAL4:
1229 case RT5663_MONO_AMP_CAL5:
1230 case RT5663_MONO_AMP_CAL6:
1231 case RT5663_MONO_AMP_CAL7:
1232 case RT5663_MONO_AMP_CAL_ST1:
1233 case RT5663_MONO_AMP_CAL_ST2:
1234 case RT5663_MONO_AMP_CAL_ST3:
1235 case RT5663_MONO_AMP_CAL_ST4:
1236 case RT5663_MONO_AMP_CAL_ST5:
1237 case RT5663_V2_HP_IMP_SEN_13:
1238 case RT5663_V2_HP_IMP_SEN_14:
1239 case RT5663_V2_HP_IMP_SEN_6:
1240 case RT5663_V2_HP_IMP_SEN_7:
1241 case RT5663_V2_HP_IMP_SEN_8:
1242 case RT5663_V2_HP_IMP_SEN_9:
1243 case RT5663_V2_HP_IMP_SEN_10:
1244 case RT5663_HP_LOGIC_3:
1245 case RT5663_HP_CALIB_ST10:
1246 case RT5663_HP_CALIB_ST11:
1247 case RT5663_PRO_REG_TBL_4:
1248 case RT5663_PRO_REG_TBL_5:
1249 case RT5663_PRO_REG_TBL_6:
1250 case RT5663_PRO_REG_TBL_7:
1251 case RT5663_PRO_REG_TBL_8:
1252 case RT5663_PRO_REG_TBL_9:
1253 case RT5663_SAR_ADC_INL_1:
1254 case RT5663_SAR_ADC_INL_2:
1255 case RT5663_SAR_ADC_INL_3:
1256 case RT5663_SAR_ADC_INL_4:
1257 case RT5663_SAR_ADC_INL_5:
1258 case RT5663_SAR_ADC_INL_6:
1259 case RT5663_SAR_ADC_INL_7:
1260 case RT5663_SAR_ADC_INL_8:
1261 case RT5663_SAR_ADC_INL_9:
1262 case RT5663_SAR_ADC_INL_10:
1263 case RT5663_SAR_ADC_INL_11:
1264 case RT5663_SAR_ADC_INL_12:
1265 case RT5663_DRC_CTRL_1:
1266 case RT5663_DRC1_CTRL_2:
1267 case RT5663_DRC1_CTRL_3:
1268 case RT5663_DRC1_CTRL_4:
1269 case RT5663_DRC1_CTRL_5:
1270 case RT5663_DRC1_CTRL_6:
1271 case RT5663_DRC1_HD_CTRL_1:
1272 case RT5663_DRC1_HD_CTRL_2:
1273 case RT5663_DRC1_PRI_REG_1:
1274 case RT5663_DRC1_PRI_REG_2:
1275 case RT5663_DRC1_PRI_REG_3:
1276 case RT5663_DRC1_PRI_REG_4:
1277 case RT5663_DRC1_PRI_REG_5:
1278 case RT5663_DRC1_PRI_REG_6:
1279 case RT5663_DRC1_PRI_REG_7:
1280 case RT5663_DRC1_PRI_REG_8:
1281 case RT5663_ALC_PGA_CTL_1:
1282 case RT5663_ALC_PGA_CTL_2:
1283 case RT5663_ALC_PGA_CTL_3:
1284 case RT5663_ALC_PGA_CTL_4:
1285 case RT5663_ALC_PGA_CTL_5:
1286 case RT5663_ALC_PGA_CTL_6:
1287 case RT5663_ALC_PGA_CTL_7:
1288 case RT5663_ALC_PGA_CTL_8:
1289 case RT5663_ALC_PGA_REG_1:
1290 case RT5663_ALC_PGA_REG_2:
1291 case RT5663_ALC_PGA_REG_3:
1292 case RT5663_ADC_EQ_RECOV_1:
1293 case RT5663_ADC_EQ_RECOV_2:
1294 case RT5663_ADC_EQ_RECOV_3:
1295 case RT5663_ADC_EQ_RECOV_4:
1296 case RT5663_ADC_EQ_RECOV_5:
1297 case RT5663_ADC_EQ_RECOV_6:
1298 case RT5663_ADC_EQ_RECOV_7:
1299 case RT5663_ADC_EQ_RECOV_8:
1300 case RT5663_ADC_EQ_RECOV_9:
1301 case RT5663_ADC_EQ_RECOV_10:
1302 case RT5663_ADC_EQ_RECOV_11:
1303 case RT5663_ADC_EQ_RECOV_12:
1304 case RT5663_ADC_EQ_RECOV_13:
1305 case RT5663_VID_HIDDEN:
1306 case RT5663_VID_CUSTOMER:
1307 case RT5663_SCAN_MODE:
1308 case RT5663_I2C_BYPA:
1311 case RT5663_DEPOP_3:
1312 case RT5663_ASRC_11_2:
1313 case RT5663_INT_ST_2:
1314 case RT5663_GPIO_STA1:
1315 case RT5663_SIN_GEN_1:
1316 case RT5663_SIN_GEN_2:
1317 case RT5663_SIN_GEN_3:
1318 case RT5663_IL_CMD_PWRSAV1:
1319 case RT5663_IL_CMD_PWRSAV2:
1320 case RT5663_EM_JACK_TYPE_1:
1321 case RT5663_EM_JACK_TYPE_2:
1322 case RT5663_EM_JACK_TYPE_3:
1323 case RT5663_EM_JACK_TYPE_4:
1324 case RT5663_FAST_OFF_MICBIAS:
1325 case RT5663_ANA_BIAS_CUR_1:
1326 case RT5663_ANA_BIAS_CUR_2:
1327 case RT5663_BIAS_CUR_9:
1328 case RT5663_DUMMY_REG_4:
1329 case RT5663_VREF_RECMIX:
1330 case RT5663_CHARGE_PUMP_1_2:
1331 case RT5663_CHARGE_PUMP_1_3:
1332 case RT5663_CHARGE_PUMP_2:
1333 case RT5663_CHOP_DAC_R:
1334 case RT5663_DUMMY_CTL_DACLR:
1335 case RT5663_DUMMY_REG_5:
1336 case RT5663_SOFT_RAMP:
1337 case RT5663_TEST_MODE_1:
1338 case RT5663_STO_DRE_10:
1339 case RT5663_MIC_DECRO_1:
1340 case RT5663_MIC_DECRO_2:
1341 case RT5663_MIC_DECRO_3:
1342 case RT5663_MIC_DECRO_4:
1343 case RT5663_MIC_DECRO_5:
1344 case RT5663_MIC_DECRO_6:
1345 case RT5663_HP_DECRO_1:
1346 case RT5663_HP_DECRO_2:
1347 case RT5663_HP_DECRO_3:
1348 case RT5663_HP_DECRO_4:
1349 case RT5663_HP_DECOUP:
1350 case RT5663_HP_IMPSEN_MAP4:
1351 case RT5663_HP_IMPSEN_MAP5:
1352 case RT5663_HP_IMPSEN_MAP7:
1353 case RT5663_HP_CALIB_1:
1359 return rt5663_readable_register(dev, reg);
1363 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1364 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1365 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1366 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1368 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1369 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1370 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1371 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1372 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1373 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1374 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1375 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1376 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1379 /* Interface data select */
1380 static const char * const rt5663_if1_adc_data_select[] = {
1381 "L/R", "R/L", "L/L", "R/R"
1384 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1385 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1387 static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1390 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1393 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1394 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1395 /* reset in-line command */
1396 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1397 RT5663_RESET_4BTN_INL_MASK,
1398 RT5663_RESET_4BTN_INL_RESET);
1399 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1400 RT5663_RESET_4BTN_INL_MASK,
1401 RT5663_RESET_4BTN_INL_NOR);
1402 switch (rt5663->codec_ver) {
1404 snd_soc_update_bits(codec, RT5663_IRQ_3,
1405 RT5663_V2_EN_IRQ_INLINE_MASK,
1406 RT5663_V2_EN_IRQ_INLINE_NOR);
1409 snd_soc_update_bits(codec, RT5663_IRQ_2,
1410 RT5663_EN_IRQ_INLINE_MASK,
1411 RT5663_EN_IRQ_INLINE_NOR);
1414 dev_err(codec->dev, "Unknown CODEC Version\n");
1417 switch (rt5663->codec_ver) {
1419 snd_soc_update_bits(codec, RT5663_IRQ_3,
1420 RT5663_V2_EN_IRQ_INLINE_MASK,
1421 RT5663_V2_EN_IRQ_INLINE_BYP);
1424 snd_soc_update_bits(codec, RT5663_IRQ_2,
1425 RT5663_EN_IRQ_INLINE_MASK,
1426 RT5663_EN_IRQ_INLINE_BYP);
1429 dev_err(codec->dev, "Unknown CODEC Version\n");
1431 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1432 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1433 /* reset in-line command */
1434 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1435 RT5663_RESET_4BTN_INL_MASK,
1436 RT5663_RESET_4BTN_INL_RESET);
1437 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1438 RT5663_RESET_4BTN_INL_MASK,
1439 RT5663_RESET_4BTN_INL_NOR);
1444 * rt5663_v2_jack_detect - Detect headset.
1445 * @codec: SoC audio codec device.
1446 * @jack_insert: Jack insert or not.
1448 * Detect whether is headset or not when jack inserted.
1450 * Returns detect status.
1453 static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1455 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1456 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1457 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1459 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1461 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1462 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
1464 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1465 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1466 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1467 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1468 snd_soc_dapm_sync(dapm);
1469 snd_soc_update_bits(codec, RT5663_RC_CLK,
1470 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1471 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1474 msleep(sleep_time[i]);
1475 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
1476 if (val == 0x1 || val == 0x2 || val == 0x3)
1478 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1479 __func__, val, sleep_time[i]);
1482 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1486 rt5663->jack_type = SND_JACK_HEADSET;
1487 rt5663_enable_push_button_irq(codec, true);
1490 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1491 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1492 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1493 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1494 snd_soc_dapm_sync(dapm);
1495 rt5663->jack_type = SND_JACK_HEADPHONE;
1499 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1501 if (rt5663->jack_type == SND_JACK_HEADSET) {
1502 rt5663_enable_push_button_irq(codec, false);
1503 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1504 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1505 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1506 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1507 snd_soc_dapm_sync(dapm);
1509 rt5663->jack_type = 0;
1512 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1513 return rt5663->jack_type;
1517 * rt5663_jack_detect - Detect headset.
1518 * @codec: SoC audio codec device.
1519 * @jack_insert: Jack insert or not.
1521 * Detect whether is headset or not when jack inserted.
1523 * Returns detect status.
1525 static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1527 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1530 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1533 snd_soc_update_bits(codec, RT5663_DIG_MISC,
1534 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1535 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1536 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1537 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1538 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1539 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1540 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1541 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1542 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1543 snd_soc_update_bits(codec, RT5663_CBJ_1,
1544 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1545 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1546 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1547 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1548 /* BST1 power on for JD */
1549 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1550 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1551 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1552 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1553 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1554 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1555 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1556 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1557 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1558 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1559 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
1560 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1561 snd_soc_update_bits(codec, RT5663_IRQ_1,
1562 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1565 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1567 usleep_range(10000, 10005);
1576 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
1577 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1579 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1580 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1581 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1586 rt5663->jack_type = SND_JACK_HEADSET;
1587 rt5663_enable_push_button_irq(codec, true);
1589 if (rt5663->pdata.impedance_sensing_num)
1592 if (rt5663->pdata.dc_offset_l_manual_mic) {
1593 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1594 rt5663->pdata.dc_offset_l_manual_mic >>
1596 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1597 rt5663->pdata.dc_offset_l_manual_mic &
1601 if (rt5663->pdata.dc_offset_r_manual_mic) {
1602 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1603 rt5663->pdata.dc_offset_r_manual_mic >>
1605 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1606 rt5663->pdata.dc_offset_r_manual_mic &
1611 rt5663->jack_type = SND_JACK_HEADPHONE;
1613 if (rt5663->pdata.impedance_sensing_num)
1616 if (rt5663->pdata.dc_offset_l_manual) {
1617 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1618 rt5663->pdata.dc_offset_l_manual >> 16);
1619 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1620 rt5663->pdata.dc_offset_l_manual &
1624 if (rt5663->pdata.dc_offset_r_manual) {
1625 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1626 rt5663->pdata.dc_offset_r_manual >> 16);
1627 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1628 rt5663->pdata.dc_offset_r_manual &
1634 if (rt5663->jack_type == SND_JACK_HEADSET)
1635 rt5663_enable_push_button_irq(codec, false);
1636 rt5663->jack_type = 0;
1639 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1640 return rt5663->jack_type;
1643 static int rt5663_impedance_sensing(struct snd_soc_codec *codec)
1645 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1646 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1648 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1649 if (rt5663->imp_table[i].vol == 7)
1653 if (rt5663->jack_type == SND_JACK_HEADSET) {
1654 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1655 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1656 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1657 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1658 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1659 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1660 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1661 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1663 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1664 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1665 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1666 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1667 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1668 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1669 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1670 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1673 reg84 = snd_soc_read(codec, RT5663_ASRC_2);
1674 reg26 = snd_soc_read(codec, RT5663_STO1_ADC_MIXER);
1675 reg2fa = snd_soc_read(codec, RT5663_DUMMY_1);
1676 reg91 = snd_soc_read(codec, RT5663_HP_CHARGE_PUMP_1);
1677 reg10 = snd_soc_read(codec, RT5663_RECMIX);
1678 reg80 = snd_soc_read(codec, RT5663_GLB_CLK);
1680 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000, 0);
1681 snd_soc_write(codec, RT5663_ASRC_2, 0);
1682 snd_soc_write(codec, RT5663_STO1_ADC_MIXER, 0x4040);
1683 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1684 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1685 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1686 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1687 usleep_range(10000, 10005);
1688 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1689 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1690 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1691 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1692 RT5663_SCLK_SRC_RCCLK);
1693 snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1694 RT5663_DIG_25M_CLK_EN);
1695 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1696 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
1697 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
1698 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1699 snd_soc_write(codec, RT5663_HP_LOGIC_2, 0x0005);
1700 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
1701 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0030);
1702 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0x0003);
1703 snd_soc_update_bits(codec, RT5663_PWR_DIG_2,
1704 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1705 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1706 snd_soc_update_bits(codec, RT5663_PWR_DIG_1,
1707 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1708 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1710 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1711 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1714 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1715 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1716 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1718 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1719 snd_soc_write(codec, RT5663_STO_DAC_MIXER, 0);
1720 snd_soc_write(codec, RT5663_BYPASS_STO_DAC, 0x000c);
1721 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
1722 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
1723 snd_soc_write(codec, RT5663_HP_OUT_EN, 0x8088);
1724 snd_soc_write(codec, RT5663_CHOP_ADC, 0x3000);
1725 snd_soc_write(codec, RT5663_ADDA_RST, 0xc000);
1726 snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0x3320);
1727 snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c9);
1728 snd_soc_write(codec, RT5663_DUMMY_1, 0x004c);
1729 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7733);
1730 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
1731 snd_soc_write(codec, RT5663_STO_DRE_9, 0x0007);
1732 snd_soc_write(codec, RT5663_STO_DRE_10, 0x0007);
1733 snd_soc_write(codec, RT5663_DUMMY_2, 0x02a4);
1734 snd_soc_write(codec, RT5663_RECMIX, 0x0005);
1735 snd_soc_write(codec, RT5663_HP_IMP_SEN_1, 0x4334);
1736 snd_soc_update_bits(codec, RT5663_IRQ_3, 0x0004, 0x0004);
1737 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x2200);
1738 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x3000);
1739 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x6200);
1741 for (i = 0; i < 100; i++) {
1743 if (snd_soc_read(codec, RT5663_INT_ST_1) & 0x2)
1747 value = snd_soc_read(codec, RT5663_HP_IMP_SEN_4);
1749 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0);
1750 snd_soc_write(codec, RT5663_INT_ST_1, 0);
1751 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0);
1752 snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1753 RT5663_DIG_25M_CLK_DIS);
1754 snd_soc_write(codec, RT5663_GLB_CLK, reg80);
1755 snd_soc_write(codec, RT5663_RECMIX, reg10);
1756 snd_soc_write(codec, RT5663_DUMMY_2, 0x00a4);
1757 snd_soc_write(codec, RT5663_DUMMY_1, reg2fa);
1758 snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c8);
1759 snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0xb320);
1760 snd_soc_write(codec, RT5663_ADDA_RST, 0xe400);
1761 snd_soc_write(codec, RT5663_CHOP_ADC, 0x2000);
1762 snd_soc_write(codec, RT5663_HP_OUT_EN, 0x0008);
1763 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1764 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1765 snd_soc_update_bits(codec, RT5663_PWR_DIG_1,
1766 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1767 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1768 RT5663_PWR_ADC_R1, 0);
1769 snd_soc_update_bits(codec, RT5663_PWR_DIG_2,
1770 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1771 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
1772 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
1773 snd_soc_write(codec, RT5663_HP_LOGIC_2, 0);
1774 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, reg91);
1775 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1776 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1777 snd_soc_write(codec, RT5663_STO1_ADC_MIXER, reg26);
1778 snd_soc_write(codec, RT5663_ASRC_2, reg84);
1780 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1781 if (value >= rt5663->imp_table[i].imp_min &&
1782 value <= rt5663->imp_table[i].imp_max)
1786 snd_soc_update_bits(codec, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1787 rt5663->imp_table[i].vol);
1788 snd_soc_update_bits(codec, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1789 rt5663->imp_table[i].vol);
1791 if (rt5663->jack_type == SND_JACK_HEADSET) {
1792 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1793 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1794 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1795 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1796 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1797 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1798 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1799 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1801 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1802 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1803 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1804 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1805 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1806 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1807 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1808 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1814 static int rt5663_button_detect(struct snd_soc_codec *codec)
1818 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1819 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1820 btn_type = val & 0xfff0;
1821 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1826 static irqreturn_t rt5663_irq(int irq, void *data)
1828 struct rt5663_priv *rt5663 = data;
1830 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1833 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1834 msecs_to_jiffies(250));
1839 int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1840 struct snd_soc_jack *hs_jack)
1842 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1844 rt5663->hs_jack = hs_jack;
1846 rt5663_irq(0, rt5663);
1850 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1852 static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1854 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1855 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1857 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1860 switch (rt5663->codec_ver) {
1862 return !(val & 0x2000);
1864 return !(val & 0x1000);
1866 dev_err(codec->dev, "Unknown CODEC Version\n");
1872 static void rt5663_jack_detect_work(struct work_struct *work)
1874 struct rt5663_priv *rt5663 =
1875 container_of(work, struct rt5663_priv, jack_detect_work.work);
1876 struct snd_soc_codec *codec = rt5663->codec;
1877 int btn_type, report = 0;
1882 if (rt5663_check_jd_status(codec)) {
1884 if (rt5663->jack_type == 0) {
1885 /* jack was out, report jack type */
1886 switch (rt5663->codec_ver) {
1888 report = rt5663_v2_jack_detect(
1892 report = rt5663_jack_detect(rt5663->codec, 1);
1893 if (rt5663->pdata.impedance_sensing_num)
1894 rt5663_impedance_sensing(rt5663->codec);
1897 dev_err(codec->dev, "Unknown CODEC Version\n");
1900 /* Delay the jack insert report to avoid pop noise */
1903 /* jack is already in, report button event */
1904 report = SND_JACK_HEADSET;
1905 btn_type = rt5663_button_detect(rt5663->codec);
1907 * rt5663 can report three kinds of button behavior,
1908 * one click, double click and hold. However,
1909 * currently we will report button pressed/released
1910 * event. So all the three button behaviors are
1911 * treated as button pressed.
1917 report |= SND_JACK_BTN_0;
1922 report |= SND_JACK_BTN_1;
1927 report |= SND_JACK_BTN_2;
1932 report |= SND_JACK_BTN_3;
1934 case 0x0000: /* unpressed */
1938 dev_err(rt5663->codec->dev,
1939 "Unexpected button code 0x%04x\n",
1943 /* button release or spurious interrput*/
1944 if (btn_type == 0) {
1945 report = rt5663->jack_type;
1946 cancel_delayed_work_sync(
1947 &rt5663->jd_unplug_work);
1949 queue_delayed_work(system_wq,
1950 &rt5663->jd_unplug_work,
1951 msecs_to_jiffies(500));
1956 switch (rt5663->codec_ver) {
1958 report = rt5663_v2_jack_detect(rt5663->codec, 0);
1961 report = rt5663_jack_detect(rt5663->codec, 0);
1964 dev_err(codec->dev, "Unknown CODEC Version\n");
1967 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1968 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1969 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1970 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1973 static void rt5663_jd_unplug_work(struct work_struct *work)
1975 struct rt5663_priv *rt5663 =
1976 container_of(work, struct rt5663_priv, jd_unplug_work.work);
1977 struct snd_soc_codec *codec = rt5663->codec;
1982 if (!rt5663_check_jd_status(codec)) {
1984 switch (rt5663->codec_ver) {
1986 rt5663_v2_jack_detect(rt5663->codec, 0);
1989 rt5663_jack_detect(rt5663->codec, 0);
1992 dev_err(codec->dev, "Unknown CODEC Version\n");
1995 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
1996 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1997 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1999 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2000 msecs_to_jiffies(500));
2004 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2005 /* DAC Digital Volume */
2006 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2007 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2008 87, 0, dac_vol_tlv),
2009 /* ADC Digital Volume Control */
2010 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2011 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2012 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2013 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2014 63, 0, adc_vol_tlv),
2017 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2018 /* Headphone Output Volume */
2019 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2020 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2021 rt5663_v2_hp_vol_tlv),
2022 /* Mic Boost Volume */
2023 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2024 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2027 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2028 /* Mic Boost Volume*/
2029 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2030 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2031 /* Data Swap for Slot0/1 in ADCDAT1 */
2032 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2035 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2036 /* Headphone Output Volume */
2037 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2038 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2042 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2043 struct snd_soc_dapm_widget *sink)
2046 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2048 val = snd_soc_read(codec, RT5663_GLB_CLK);
2049 val &= RT5663_SCLK_SRC_MASK;
2050 if (val == RT5663_SCLK_SRC_PLL1)
2056 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2057 struct snd_soc_dapm_widget *sink)
2059 unsigned int reg, shift, val;
2060 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2061 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2063 if (rt5663->codec_ver == CODEC_VER_1) {
2065 case RT5663_ADC_STO1_ASRC_SHIFT:
2066 reg = RT5663_ASRC_3;
2067 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2069 case RT5663_DAC_STO1_ASRC_SHIFT:
2070 reg = RT5663_ASRC_2;
2071 shift = RT5663_DA_STO1_TRACK_SHIFT;
2078 case RT5663_ADC_STO1_ASRC_SHIFT:
2079 reg = RT5663_ASRC_2;
2080 shift = RT5663_AD_STO1_TRACK_SHIFT;
2082 case RT5663_DAC_STO1_ASRC_SHIFT:
2083 reg = RT5663_ASRC_2;
2084 shift = RT5663_DA_STO1_TRACK_SHIFT;
2091 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
2099 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2100 struct snd_soc_dapm_widget *sink)
2102 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
2103 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2104 int da_asrc_en, ad_asrc_en;
2106 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
2107 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2108 switch (rt5663->codec_ver) {
2110 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
2111 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2114 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
2115 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2118 dev_err(codec->dev, "Unknown CODEC Version\n");
2122 if (da_asrc_en || ad_asrc_en)
2123 if (rt5663->sysclk > rt5663->lrck * 384)
2126 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2132 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2133 * @codec: SoC audio codec device.
2134 * @filter_mask: mask of filters.
2135 * @clk_src: clock source
2137 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2138 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2139 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2140 * ASRC function will track i2s clock and generate a corresponding system clock
2141 * for codec. This function provides an API to select the clock source for a
2142 * set of filters specified by the mask. And the codec driver will turn on ASRC
2143 * for these filters if ASRC is selected as their clock source.
2145 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
2146 unsigned int filter_mask, unsigned int clk_src)
2148 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2149 unsigned int asrc2_mask = 0;
2150 unsigned int asrc2_value = 0;
2151 unsigned int asrc3_mask = 0;
2152 unsigned int asrc3_value = 0;
2155 case RT5663_CLK_SEL_SYS:
2156 case RT5663_CLK_SEL_I2S1_ASRC:
2163 if (filter_mask & RT5663_DA_STEREO_FILTER) {
2164 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2165 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2168 if (filter_mask & RT5663_AD_STEREO_FILTER) {
2169 switch (rt5663->codec_ver) {
2171 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2172 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2175 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2176 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2179 dev_err(codec->dev, "Unknown CODEC Version\n");
2184 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
2188 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
2193 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2196 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2197 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2198 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2199 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2200 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2203 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2204 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2205 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2209 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2210 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2211 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2212 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2213 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2216 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2217 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2218 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2219 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2220 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2223 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2224 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2225 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2226 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2227 RT5663_M_DAC1_L_SHIFT, 1, 1),
2230 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2231 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2232 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2233 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2234 RT5663_M_DAC1_R_SHIFT, 1, 1),
2237 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2238 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2239 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2242 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2243 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2244 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2248 static const struct snd_kcontrol_new rt5663_hpo_switch =
2249 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2250 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2252 /* Stereo ADC source */
2253 static const char * const rt5663_sto1_adc_src[] = {
2257 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2258 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2260 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2261 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2263 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2264 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2266 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2267 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2269 /* RT5663: Analog DACL1 input source */
2270 static const char * const rt5663_alg_dacl_src[] = {
2271 "DAC L", "STO DAC MIXL"
2274 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2275 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2277 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2278 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2280 /* RT5663: Analog DACR1 input source */
2281 static const char * const rt5663_alg_dacr_src[] = {
2282 "DAC R", "STO DAC MIXR"
2285 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2286 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2288 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2289 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2291 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2292 struct snd_kcontrol *kcontrol, int event)
2294 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2295 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2298 case SND_SOC_DAPM_POST_PMU:
2299 if (rt5663->codec_ver == CODEC_VER_1) {
2300 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2301 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2302 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2303 RT5663_HP_SIG_SRC1_MASK,
2304 RT5663_HP_SIG_SRC1_SILENCE);
2306 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2307 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2308 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2309 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2310 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2311 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2312 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2313 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2314 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2315 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000,
2317 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2322 case SND_SOC_DAPM_PRE_PMD:
2323 if (rt5663->codec_ver == CODEC_VER_1) {
2324 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2325 RT5663_HP_SIG_SRC1_MASK,
2326 RT5663_HP_SIG_SRC1_REG);
2328 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2329 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2330 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2341 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2342 struct snd_kcontrol *kcontrol, int event)
2344 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2345 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2348 case SND_SOC_DAPM_PRE_PMU:
2349 if (rt5663->codec_ver == CODEC_VER_0) {
2350 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2352 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003,
2357 case SND_SOC_DAPM_POST_PMD:
2358 if (rt5663->codec_ver == CODEC_VER_0) {
2359 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
2360 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
2371 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2372 struct snd_kcontrol *kcontrol, int event)
2374 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2377 case SND_SOC_DAPM_POST_PMU:
2378 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2379 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2380 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2383 case SND_SOC_DAPM_PRE_PMD:
2384 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2385 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2395 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2396 struct snd_kcontrol *kcontrol, int event)
2398 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2401 case SND_SOC_DAPM_POST_PMU:
2402 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2403 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2406 case SND_SOC_DAPM_PRE_PMD:
2407 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2408 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2418 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2419 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2423 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2424 RT5663_PWR_MB1_SHIFT, 0),
2425 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2426 RT5663_PWR_MB2_SHIFT, 0),
2429 SND_SOC_DAPM_INPUT("IN1P"),
2430 SND_SOC_DAPM_INPUT("IN1N"),
2432 /* REC Mixer Power */
2433 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2434 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2437 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2438 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2439 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2440 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2441 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2444 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2445 0, 0, rt5663_sto1_adc_l_mix,
2446 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2448 /* ADC Filter Power */
2449 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2450 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2452 /* Digital Interface */
2453 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2455 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2456 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2457 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2458 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2459 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2461 /* Audio Interface */
2462 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2463 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2465 /* DAC mixer before sound effect */
2466 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2467 ARRAY_SIZE(rt5663_adda_l_mix)),
2468 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2469 ARRAY_SIZE(rt5663_adda_r_mix)),
2470 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2471 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2474 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2475 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2476 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2477 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2478 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2479 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2482 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2483 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2484 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2485 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2486 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2487 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2490 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2491 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2492 SND_SOC_DAPM_POST_PMD),
2493 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2494 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2497 SND_SOC_DAPM_OUTPUT("HPOL"),
2498 SND_SOC_DAPM_OUTPUT("HPOR"),
2501 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2502 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2503 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2504 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2505 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2506 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2507 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2510 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2511 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2512 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2513 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2514 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2515 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2518 SND_SOC_DAPM_INPUT("IN2P"),
2519 SND_SOC_DAPM_INPUT("IN2N"),
2522 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2523 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2524 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2525 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2526 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2527 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2528 SND_SOC_DAPM_POST_PMU),
2531 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2532 ARRAY_SIZE(rt5663_recmix1l)),
2533 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2534 ARRAY_SIZE(rt5663_recmix1r)),
2535 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2536 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2539 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2540 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2541 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2544 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2545 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2546 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2547 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2548 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2549 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2550 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2551 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2553 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2554 &rt5663_sto1_adcl_mux),
2555 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2556 &rt5663_sto1_adcr_mux),
2559 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2560 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2562 /* Analog DAC Clock */
2563 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2564 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2567 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2568 &rt5663_hpo_switch),
2571 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2572 /* System Clock Pre Divider Gating */
2573 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2574 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2575 SND_SOC_DAPM_PRE_PMD),
2578 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2579 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2582 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2583 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2584 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2585 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2586 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2587 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 /* Analog DAC source */
2597 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2598 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2601 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2603 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2606 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2607 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2608 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2610 { "ADC L", NULL, "ADC L Power" },
2611 { "ADC L", NULL, "ADC Clock" },
2613 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2615 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2616 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2617 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2619 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2620 { "IF ADC", NULL, "IF1 ADC1" },
2621 { "AIFTX", NULL, "IF ADC" },
2622 { "AIFTX", NULL, "I2S" },
2624 { "AIFRX", NULL, "I2S" },
2625 { "IF DAC", NULL, "AIFRX" },
2626 { "IF1 DAC1 L", NULL, "IF DAC" },
2627 { "IF1 DAC1 R", NULL, "IF DAC" },
2629 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2630 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2631 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2632 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2633 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2634 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2635 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2637 { "DAC L1", NULL, "ADDA MIXL" },
2638 { "DAC R1", NULL, "ADDA MIXR" },
2640 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2641 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2642 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2643 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2644 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2645 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2647 { "HP Amp", NULL, "HP Charge Pump" },
2648 { "HP Amp", NULL, "DAC L" },
2649 { "HP Amp", NULL, "DAC R" },
2652 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2653 { "MICBIAS1", NULL, "LDO2" },
2654 { "MICBIAS2", NULL, "LDO2" },
2656 { "BST1 CBJ", NULL, "IN1P" },
2657 { "BST1 CBJ", NULL, "IN1N" },
2658 { "BST1 CBJ", NULL, "CBJ Power" },
2660 { "BST2", NULL, "IN2P" },
2661 { "BST2", NULL, "IN2N" },
2662 { "BST2", NULL, "BST2 Power" },
2664 { "RECMIX1L", "BST2 Switch", "BST2" },
2665 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2666 { "RECMIX1L", NULL, "RECMIX1L Power" },
2667 { "RECMIX1R", "BST2 Switch", "BST2" },
2668 { "RECMIX1R", NULL, "RECMIX1R Power" },
2670 { "ADC L", NULL, "RECMIX1L" },
2671 { "ADC R", NULL, "RECMIX1R" },
2672 { "ADC R", NULL, "ADC R Power" },
2673 { "ADC R", NULL, "ADC Clock" },
2675 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2676 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2677 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2679 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2680 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2681 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2682 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2684 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2685 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2686 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2688 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2690 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2692 { "DAC L", NULL, "STO1 DAC MIXL" },
2693 { "DAC L", NULL, "LDO DAC" },
2694 { "DAC L", NULL, "DAC Clock" },
2695 { "DAC R", NULL, "STO1 DAC MIXR" },
2696 { "DAC R", NULL, "LDO DAC" },
2697 { "DAC R", NULL, "DAC Clock" },
2699 { "HPO Playback", "Switch", "HP Amp" },
2700 { "HPOL", NULL, "HPO Playback" },
2701 { "HPOR", NULL, "HPO Playback" },
2704 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2705 { "I2S", NULL, "Pre Div Power" },
2707 { "BST1", NULL, "IN1P" },
2708 { "BST1", NULL, "IN1N" },
2709 { "BST1", NULL, "RECMIX1L Power" },
2711 { "ADC L", NULL, "BST1" },
2713 { "STO1 ADC L1", NULL, "ADC L" },
2715 { "DAC L Mux", "DAC L", "DAC L1" },
2716 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2717 { "DAC R Mux", "DAC R", "DAC R1"},
2718 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2720 { "DAC L", NULL, "DAC L Mux" },
2721 { "DAC R", NULL, "DAC R Mux" },
2723 { "HPOL", NULL, "HP Amp" },
2724 { "HPOR", NULL, "HP Amp" },
2727 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2728 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2730 struct snd_soc_codec *codec = dai->codec;
2731 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2732 unsigned int val_len = 0;
2735 rt5663->lrck = params_rate(params);
2737 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2738 rt5663->lrck, rt5663->sysclk);
2740 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2742 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2743 rt5663->lrck, dai->id);
2747 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2749 switch (params_width(params)) {
2751 val_len = RT5663_I2S_DL_8;
2754 val_len = RT5663_I2S_DL_16;
2757 val_len = RT5663_I2S_DL_20;
2760 val_len = RT5663_I2S_DL_24;
2766 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
2767 RT5663_I2S_DL_MASK, val_len);
2769 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
2770 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2775 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2777 struct snd_soc_codec *codec = dai->codec;
2778 unsigned int reg_val = 0;
2780 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2781 case SND_SOC_DAIFMT_CBM_CFM:
2783 case SND_SOC_DAIFMT_CBS_CFS:
2784 reg_val |= RT5663_I2S_MS_S;
2790 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2791 case SND_SOC_DAIFMT_NB_NF:
2793 case SND_SOC_DAIFMT_IB_NF:
2794 reg_val |= RT5663_I2S_BP_INV;
2800 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2801 case SND_SOC_DAIFMT_I2S:
2803 case SND_SOC_DAIFMT_LEFT_J:
2804 reg_val |= RT5663_I2S_DF_LEFT;
2806 case SND_SOC_DAIFMT_DSP_A:
2807 reg_val |= RT5663_I2S_DF_PCM_A;
2809 case SND_SOC_DAIFMT_DSP_B:
2810 reg_val |= RT5663_I2S_DF_PCM_B;
2816 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2817 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2822 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2823 unsigned int freq, int dir)
2825 struct snd_soc_codec *codec = dai->codec;
2826 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2827 unsigned int reg_val = 0;
2829 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2833 case RT5663_SCLK_S_MCLK:
2834 reg_val |= RT5663_SCLK_SRC_MCLK;
2836 case RT5663_SCLK_S_PLL1:
2837 reg_val |= RT5663_SCLK_SRC_PLL1;
2839 case RT5663_SCLK_S_RCCLK:
2840 reg_val |= RT5663_SCLK_SRC_RCCLK;
2843 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2846 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2848 rt5663->sysclk = freq;
2849 rt5663->sysclk_src = clk_id;
2851 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2857 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2858 unsigned int freq_in, unsigned int freq_out)
2860 struct snd_soc_codec *codec = dai->codec;
2861 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2862 struct rl6231_pll_code pll_code;
2864 int mask, shift, val;
2866 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2867 freq_out == rt5663->pll_out)
2870 if (!freq_in || !freq_out) {
2871 dev_dbg(codec->dev, "PLL disabled\n");
2874 rt5663->pll_out = 0;
2875 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2876 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2880 switch (rt5663->codec_ver) {
2882 mask = RT5663_V2_PLL1_SRC_MASK;
2883 shift = RT5663_V2_PLL1_SRC_SHIFT;
2886 mask = RT5663_PLL1_SRC_MASK;
2887 shift = RT5663_PLL1_SRC_SHIFT;
2890 dev_err(codec->dev, "Unknown CODEC Version\n");
2895 case RT5663_PLL1_S_MCLK:
2898 case RT5663_PLL1_S_BCLK1:
2902 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2905 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2907 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2909 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2913 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2914 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2917 snd_soc_write(codec, RT5663_PLL_1,
2918 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2919 snd_soc_write(codec, RT5663_PLL_2,
2920 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2921 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2923 rt5663->pll_in = freq_in;
2924 rt5663->pll_out = freq_out;
2925 rt5663->pll_src = source;
2930 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2931 unsigned int rx_mask, int slots, int slot_width)
2933 struct snd_soc_codec *codec = dai->codec;
2934 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2935 unsigned int val = 0, reg;
2937 if (rx_mask || tx_mask)
2938 val |= RT5663_TDM_MODE_TDM;
2942 val |= RT5663_TDM_IN_CH_4;
2943 val |= RT5663_TDM_OUT_CH_4;
2946 val |= RT5663_TDM_IN_CH_6;
2947 val |= RT5663_TDM_OUT_CH_6;
2950 val |= RT5663_TDM_IN_CH_8;
2951 val |= RT5663_TDM_OUT_CH_8;
2959 switch (slot_width) {
2961 val |= RT5663_TDM_IN_LEN_20;
2962 val |= RT5663_TDM_OUT_LEN_20;
2965 val |= RT5663_TDM_IN_LEN_24;
2966 val |= RT5663_TDM_OUT_LEN_24;
2969 val |= RT5663_TDM_IN_LEN_32;
2970 val |= RT5663_TDM_OUT_LEN_32;
2978 switch (rt5663->codec_ver) {
2986 dev_err(codec->dev, "Unknown CODEC Version\n");
2990 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2991 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2992 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
2997 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2999 struct snd_soc_codec *codec = dai->codec;
3000 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3003 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
3005 if (rt5663->codec_ver == CODEC_VER_1)
3012 snd_soc_update_bits(codec, reg,
3013 RT5663_TDM_LENGTN_MASK,
3014 RT5663_TDM_LENGTN_16);
3017 snd_soc_update_bits(codec, reg,
3018 RT5663_TDM_LENGTN_MASK,
3019 RT5663_TDM_LENGTN_20);
3022 snd_soc_update_bits(codec, reg,
3023 RT5663_TDM_LENGTN_MASK,
3024 RT5663_TDM_LENGTN_24);
3027 snd_soc_update_bits(codec, reg,
3028 RT5663_TDM_LENGTN_MASK,
3029 RT5663_TDM_LENGTN_32);
3032 dev_err(codec->dev, "Invalid ratio!\n");
3039 static int rt5663_set_bias_level(struct snd_soc_codec *codec,
3040 enum snd_soc_bias_level level)
3042 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3045 case SND_SOC_BIAS_ON:
3046 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
3047 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3048 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3051 case SND_SOC_BIAS_PREPARE:
3052 if (rt5663->codec_ver == CODEC_VER_1) {
3053 snd_soc_update_bits(codec, RT5663_DIG_MISC,
3054 RT5663_DIG_GATE_CTRL_MASK,
3055 RT5663_DIG_GATE_CTRL_EN);
3056 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
3057 RT5663_EN_ANA_CLK_DET_MASK |
3058 RT5663_PWR_CLK_DET_MASK,
3059 RT5663_EN_ANA_CLK_DET_AUTO |
3060 RT5663_PWR_CLK_DET_EN);
3064 case SND_SOC_BIAS_STANDBY:
3065 if (rt5663->codec_ver == CODEC_VER_1)
3066 snd_soc_update_bits(codec, RT5663_DIG_MISC,
3067 RT5663_DIG_GATE_CTRL_MASK,
3068 RT5663_DIG_GATE_CTRL_DIS);
3069 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
3070 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3071 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3072 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3073 RT5663_PWR_VREF2 | RT5663_PWR_MB);
3074 usleep_range(10000, 10005);
3075 if (rt5663->codec_ver == CODEC_VER_1) {
3076 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
3077 RT5663_EN_ANA_CLK_DET_MASK |
3078 RT5663_PWR_CLK_DET_MASK,
3079 RT5663_EN_ANA_CLK_DET_DIS |
3080 RT5663_PWR_CLK_DET_DIS);
3084 case SND_SOC_BIAS_OFF:
3085 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
3086 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3087 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
3097 static int rt5663_probe(struct snd_soc_codec *codec)
3099 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3100 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3102 rt5663->codec = codec;
3104 switch (rt5663->codec_ver) {
3106 snd_soc_dapm_new_controls(dapm,
3107 rt5663_v2_specific_dapm_widgets,
3108 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3109 snd_soc_dapm_add_routes(dapm,
3110 rt5663_v2_specific_dapm_routes,
3111 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3112 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
3113 ARRAY_SIZE(rt5663_v2_specific_controls));
3116 snd_soc_dapm_new_controls(dapm,
3117 rt5663_specific_dapm_widgets,
3118 ARRAY_SIZE(rt5663_specific_dapm_widgets));
3119 snd_soc_dapm_add_routes(dapm,
3120 rt5663_specific_dapm_routes,
3121 ARRAY_SIZE(rt5663_specific_dapm_routes));
3122 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
3123 ARRAY_SIZE(rt5663_specific_controls));
3125 if (!rt5663->imp_table)
3126 snd_soc_add_codec_controls(codec, rt5663_hpvol_controls,
3127 ARRAY_SIZE(rt5663_hpvol_controls));
3134 static int rt5663_remove(struct snd_soc_codec *codec)
3136 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3138 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3144 static int rt5663_suspend(struct snd_soc_codec *codec)
3146 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3148 regcache_cache_only(rt5663->regmap, true);
3149 regcache_mark_dirty(rt5663->regmap);
3154 static int rt5663_resume(struct snd_soc_codec *codec)
3156 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3158 regcache_cache_only(rt5663->regmap, false);
3159 regcache_sync(rt5663->regmap);
3161 rt5663_irq(0, rt5663);
3166 #define rt5663_suspend NULL
3167 #define rt5663_resume NULL
3170 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3171 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3172 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3174 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3175 .hw_params = rt5663_hw_params,
3176 .set_fmt = rt5663_set_dai_fmt,
3177 .set_sysclk = rt5663_set_dai_sysclk,
3178 .set_pll = rt5663_set_dai_pll,
3179 .set_tdm_slot = rt5663_set_tdm_slot,
3180 .set_bclk_ratio = rt5663_set_bclk_ratio,
3183 static struct snd_soc_dai_driver rt5663_dai[] = {
3185 .name = "rt5663-aif",
3188 .stream_name = "AIF Playback",
3191 .rates = RT5663_STEREO_RATES,
3192 .formats = RT5663_FORMATS,
3195 .stream_name = "AIF Capture",
3198 .rates = RT5663_STEREO_RATES,
3199 .formats = RT5663_FORMATS,
3201 .ops = &rt5663_aif_dai_ops,
3205 static const struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
3206 .probe = rt5663_probe,
3207 .remove = rt5663_remove,
3208 .suspend = rt5663_suspend,
3209 .resume = rt5663_resume,
3210 .set_bias_level = rt5663_set_bias_level,
3211 .idle_bias_off = true,
3212 .component_driver = {
3213 .controls = rt5663_snd_controls,
3214 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
3215 .dapm_widgets = rt5663_dapm_widgets,
3216 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3217 .dapm_routes = rt5663_dapm_routes,
3218 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3222 static const struct regmap_config rt5663_v2_regmap = {
3225 .use_single_rw = true,
3226 .max_register = 0x07fa,
3227 .volatile_reg = rt5663_v2_volatile_register,
3228 .readable_reg = rt5663_v2_readable_register,
3229 .cache_type = REGCACHE_RBTREE,
3230 .reg_defaults = rt5663_v2_reg,
3231 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3234 static const struct regmap_config rt5663_regmap = {
3237 .use_single_rw = true,
3238 .max_register = 0x03f3,
3239 .volatile_reg = rt5663_volatile_register,
3240 .readable_reg = rt5663_readable_register,
3241 .cache_type = REGCACHE_RBTREE,
3242 .reg_defaults = rt5663_reg,
3243 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3246 static const struct regmap_config temp_regmap = {
3250 .use_single_rw = true,
3251 .max_register = 0x03f3,
3252 .cache_type = REGCACHE_NONE,
3255 static const struct i2c_device_id rt5663_i2c_id[] = {
3259 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3261 #if defined(CONFIG_OF)
3262 static const struct of_device_id rt5663_of_match[] = {
3263 { .compatible = "realtek,rt5663", },
3266 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3270 static const struct acpi_device_id rt5663_acpi_match[] = {
3274 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3277 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3279 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3280 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3281 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3282 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3283 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3284 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3285 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3286 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3287 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3288 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3290 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3291 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3292 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3296 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3300 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3302 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3303 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3304 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3305 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3306 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3307 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3308 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3309 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3310 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3312 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3313 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3314 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3315 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3316 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3317 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3318 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3319 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3320 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3321 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3325 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3326 if (!(value & 0x80))
3327 usleep_range(10000, 10005);
3335 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3336 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3337 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3338 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3339 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3340 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3341 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3342 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3343 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3344 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3346 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3347 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3348 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3349 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3350 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3351 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3352 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3353 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3354 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3355 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3356 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3357 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3358 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3359 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3360 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3361 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3362 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3363 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3364 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3365 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3366 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3367 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3368 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3372 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3374 usleep_range(10000, 10005);
3383 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3384 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3385 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3389 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3391 usleep_range(10000, 10005);
3400 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3401 usleep_range(10000, 10005);
3402 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3403 usleep_range(10000, 10005);
3404 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3405 usleep_range(10000, 10005);
3406 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3407 usleep_range(10000, 10005);
3408 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3409 usleep_range(10000, 10005);
3410 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3411 usleep_range(10000, 10005);
3414 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3418 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3419 &rt5663->pdata.dc_offset_l_manual);
3420 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3421 &rt5663->pdata.dc_offset_r_manual);
3422 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3423 &rt5663->pdata.dc_offset_l_manual_mic);
3424 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3425 &rt5663->pdata.dc_offset_r_manual_mic);
3426 device_property_read_u32(dev, "realtek,impedance_sensing_num",
3427 &rt5663->pdata.impedance_sensing_num);
3429 if (rt5663->pdata.impedance_sensing_num) {
3430 table_size = sizeof(struct impedance_mapping_table) *
3431 rt5663->pdata.impedance_sensing_num;
3432 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3433 device_property_read_u32_array(dev,
3434 "realtek,impedance_sensing_table",
3435 (u32 *)rt5663->imp_table, table_size);
3441 static int rt5663_i2c_probe(struct i2c_client *i2c,
3442 const struct i2c_device_id *id)
3444 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3445 struct rt5663_priv *rt5663;
3448 struct regmap *regmap;
3450 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3456 i2c_set_clientdata(i2c, rt5663);
3459 rt5663->pdata = *pdata;
3461 rt5663_parse_dp(rt5663, &i2c->dev);
3463 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3464 if (IS_ERR(regmap)) {
3465 ret = PTR_ERR(regmap);
3466 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3471 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3472 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3474 "Device with ID register %#x is not rt5663, retry one time.\n",
3477 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3481 case RT5663_DEVICE_ID_2:
3482 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3483 rt5663->codec_ver = CODEC_VER_1;
3485 case RT5663_DEVICE_ID_1:
3486 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3487 rt5663->codec_ver = CODEC_VER_0;
3491 "Device with ID register %#x is not rt5663\n",
3496 if (IS_ERR(rt5663->regmap)) {
3497 ret = PTR_ERR(rt5663->regmap);
3498 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3503 /* reset and calibrate */
3504 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3505 regcache_cache_bypass(rt5663->regmap, true);
3506 switch (rt5663->codec_ver) {
3508 rt5663_v2_calibrate(rt5663);
3511 rt5663_calibrate(rt5663);
3514 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3516 regcache_cache_bypass(rt5663->regmap, false);
3517 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3518 dev_dbg(&i2c->dev, "calibrate done\n");
3520 switch (rt5663->codec_ver) {
3524 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3525 ARRAY_SIZE(rt5663_patch_list));
3528 "Failed to apply regmap patch: %d\n", ret);
3531 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3535 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3536 RT5663_GP1_PIN_IRQ);
3537 /* 4btn inline command debounce */
3538 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3539 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3541 switch (rt5663->codec_ver) {
3543 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3545 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3546 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3547 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3548 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3549 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3550 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3551 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3553 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3554 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3555 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3556 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3557 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3558 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3559 /* Set GPIO4 and GPIO8 as input for combo jack */
3560 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3561 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3562 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3563 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3564 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3565 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3566 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3569 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3570 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3571 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3572 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3573 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3574 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3575 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3576 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3577 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3578 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3580 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3581 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3582 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3583 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3584 /* DACREF LDO control */
3585 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3587 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3588 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3589 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3590 RT5663_DATA_SWAP_ADCDAT1_MASK,
3591 RT5663_DATA_SWAP_ADCDAT1_LL);
3594 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3597 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3598 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3601 ret = request_irq(i2c->irq, rt5663_irq,
3602 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3603 | IRQF_ONESHOT, "rt5663", rt5663);
3605 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3609 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3610 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3614 free_irq(i2c->irq, rt5663);
3620 static int rt5663_i2c_remove(struct i2c_client *i2c)
3622 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3625 free_irq(i2c->irq, rt5663);
3627 snd_soc_unregister_codec(&i2c->dev);
3632 static void rt5663_i2c_shutdown(struct i2c_client *client)
3634 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3636 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3639 static struct i2c_driver rt5663_i2c_driver = {
3642 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3643 .of_match_table = of_match_ptr(rt5663_of_match),
3645 .probe = rt5663_i2c_probe,
3646 .remove = rt5663_i2c_remove,
3647 .shutdown = rt5663_i2c_shutdown,
3648 .id_table = rt5663_i2c_id,
3650 module_i2c_driver(rt5663_i2c_driver);
3652 MODULE_DESCRIPTION("ASoC RT5663 driver");
3653 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3654 MODULE_LICENSE("GPL v2");
projects / linux.git / blob