1 // SPDX-License-Identifier: GPL-2.0
3 * rt715-sdw.c -- rt715 ALSA SoC audio driver
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
7 * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/soundwire/sdw.h>
14 #include <linux/soundwire/sdw_type.h>
15 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <sound/soc.h>
20 #include "rt715-sdw.h"
22 static bool rt715_readable_register(struct device *dev, unsigned int reg)
25 case 0x00e0 ... 0x00e5:
26 case 0x00ee ... 0x00ef:
27 case 0x00f0 ... 0x00f5:
28 case 0x00fe ... 0x00ff:
35 case 0x2000 ... 0x2016:
36 case 0x201a ... 0x2027:
37 case 0x2029 ... 0x202a:
38 case 0x202d ... 0x2034:
39 case 0x2200 ... 0x2204:
40 case 0x2206 ... 0x2212:
41 case 0x2220 ... 0x2223:
42 case 0x2230 ... 0x2239:
43 case 0x22f0 ... 0x22f3:
119 static bool rt715_volatile_register(struct device *dev, unsigned int reg)
134 case 0x200b ... 0x200e: /* i2c read */
135 case 0x2012 ... 0x2015: /* HD-A read */
136 case 0x202d ... 0x202f: /* BRA */
137 case 0x2201 ... 0x2212: /* i2c debug */
138 case 0x2220 ... 0x2223: /* decoded HD-A */
145 static int rt715_sdw_read(void *context, unsigned int reg, unsigned int *val)
147 struct device *dev = context;
148 struct rt715_priv *rt715 = dev_get_drvdata(dev);
149 unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
150 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
151 unsigned int is_hda_reg = 1, is_index_reg = 0;
159 if (is_index_reg) { /* index registers */
163 ret = regmap_write(rt715->sdw_regmap, reg, 0);
168 ret = regmap_write(rt715->sdw_regmap, reg2, val2);
172 reg3 = RT715_PRIV_DATA_R_H | nid;
173 ret = regmap_write(rt715->sdw_regmap, reg3,
174 ((*val >> 8) & 0xff));
177 reg4 = reg3 + 0x1000;
179 ret = regmap_write(rt715->sdw_regmap, reg4, (*val & 0xff));
182 } else if (mask == 0x3000) {
184 ret = regmap_write(rt715->sdw_regmap, reg, *val);
187 } else if (mask == 0x7000) {
190 ret = regmap_write(rt715->sdw_regmap, reg,
191 ((*val >> 8) & 0xff));
196 ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
199 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
202 ret = regmap_write(rt715->sdw_regmap, reg2,
203 ((*val >> 8) & 0xff));
206 ret = regmap_write(rt715->sdw_regmap, reg, (*val & 0xff));
209 } else if (mask == 0x9000) {
210 ret = regmap_write(rt715->sdw_regmap, reg,
211 ((*val >> 8) & 0xff));
216 ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff));
219 } else if (mask == 0xb000) {
220 ret = regmap_write(rt715->sdw_regmap, reg, *val);
224 ret = regmap_read(rt715->sdw_regmap, reg, val);
230 if (is_hda_reg || is_index_reg) {
235 ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_3,
239 ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_2,
243 ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_1,
247 ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_0,
251 *val = ((sdw_data_3 & 0xff) << 24) |
252 ((sdw_data_2 & 0xff) << 16) |
253 ((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
257 dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
258 else if (is_index_reg)
259 dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n", __func__,
260 reg, reg2, reg3, reg4, *val);
262 dev_dbg(dev, "[%s] %04x %04x => %08x\n",
263 __func__, reg, reg2, *val);
268 static int rt715_sdw_write(void *context, unsigned int reg, unsigned int val)
270 struct device *dev = context;
271 struct rt715_priv *rt715 = dev_get_drvdata(dev);
272 unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
273 unsigned int is_index_reg = 0;
281 if (is_index_reg) { /* index registers */
285 ret = regmap_write(rt715->sdw_regmap, reg, 0);
290 ret = regmap_write(rt715->sdw_regmap, reg2, val2);
294 reg3 = RT715_PRIV_DATA_W_H | nid;
295 ret = regmap_write(rt715->sdw_regmap, reg3,
296 ((val >> 8) & 0xff));
299 reg4 = reg3 + 0x1000;
301 ret = regmap_write(rt715->sdw_regmap, reg4, (val & 0xff));
305 } else if (reg < 0x4fff) {
306 ret = regmap_write(rt715->sdw_regmap, reg, val);
309 } else if (reg == RT715_FUNC_RESET) {
310 ret = regmap_write(rt715->sdw_regmap, reg, val);
313 } else if (mask == 0x7000) {
314 ret = regmap_write(rt715->sdw_regmap, reg,
315 ((val >> 8) & 0xff));
320 ret = regmap_write(rt715->sdw_regmap, reg2, (val & 0xff));
323 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
326 ret = regmap_write(rt715->sdw_regmap, reg2,
327 ((val >> 8) & 0xff));
330 ret = regmap_write(rt715->sdw_regmap, reg, (val & 0xff));
336 dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
337 else if (is_index_reg)
338 dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
339 __func__, reg, reg2, reg3, reg4, val2, val);
341 dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
342 __func__, reg, reg2, val);
347 static const struct regmap_config rt715_regmap = {
350 .readable_reg = rt715_readable_register, /* Readable registers */
351 .volatile_reg = rt715_volatile_register, /* volatile register */
352 .max_register = 0x752039, /* Maximum number of register */
353 .reg_defaults = rt715_reg_defaults, /* Defaults */
354 .num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults),
355 .cache_type = REGCACHE_RBTREE,
356 .use_single_read = true,
357 .use_single_write = true,
358 .reg_read = rt715_sdw_read,
359 .reg_write = rt715_sdw_write,
362 static const struct regmap_config rt715_sdw_regmap = {
364 .reg_bits = 32, /* Total register space for SDW */
365 .val_bits = 8, /* Total number of bits in register */
366 .max_register = 0xff01, /* Maximum number of register */
367 .cache_type = REGCACHE_NONE,
368 .use_single_read = true,
369 .use_single_write = true,
372 int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload,
373 unsigned int *sdw_addr_h, unsigned int *sdw_data_h,
374 unsigned int *sdw_addr_l, unsigned int *sdw_data_l)
376 unsigned int offset_h, offset_l, e_verb;
378 if (((verb & 0xff) != 0) || verb == 0xf00) { /* 12 bits command */
379 if (verb == 0x7ff) /* special case */
384 if (verb & 0x800) /* get command */
385 e_verb = (verb - 0xf00) | 0x80;
386 else /* set command */
387 e_verb = (verb - 0x700);
389 *sdw_data_h = payload; /* 7 bits payload */
390 *sdw_addr_l = *sdw_data_l = 0;
391 } else { /* 4 bits command */
392 if ((verb & 0x800) == 0x800) { /* read */
400 *sdw_data_h = (payload >> 8); /* 16 bits payload [15:8] */
401 *sdw_addr_l = (e_verb << 8) | nid | 0x80; /* 0x80: valid bit */
402 *sdw_addr_l += offset_l;
403 *sdw_data_l = payload & 0xff;
406 *sdw_addr_h = (e_verb << 8) | nid;
407 *sdw_addr_h += offset_h;
411 EXPORT_SYMBOL(hda_to_sdw);
413 static int rt715_update_status(struct sdw_slave *slave,
414 enum sdw_slave_status status)
416 struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
418 /* Update the status */
419 rt715->status = status;
421 * Perform initialization only if slave status is present and
422 * hw_init flag is false
424 if (rt715->hw_init || rt715->status != SDW_SLAVE_ATTACHED)
427 /* perform I/O transfers required for Slave initialization */
428 return rt715_io_init(&slave->dev, slave);
431 static int rt715_read_prop(struct sdw_slave *slave)
433 struct sdw_slave_prop *prop = &slave->prop;
434 int nval, i, num_of_ports = 1;
437 struct sdw_dpn_prop *dpn;
439 prop->paging_support = false;
441 /* first we need to allocate memory for set bits in port lists */
442 prop->source_ports = 0x50;/* BITMAP: 01010000 */
443 prop->sink_ports = 0x0; /* BITMAP: 00000000 */
445 nval = hweight32(prop->source_ports);
446 num_of_ports += nval;
447 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
448 sizeof(*prop->src_dpn_prop),
450 if (!prop->src_dpn_prop)
453 dpn = prop->src_dpn_prop;
455 addr = prop->source_ports;
456 for_each_set_bit(bit, &addr, 32) {
458 dpn[i].simple_ch_prep_sm = true;
459 dpn[i].ch_prep_timeout = 10;
463 /* do this again for sink now */
464 nval = hweight32(prop->sink_ports);
465 num_of_ports += nval;
466 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
467 sizeof(*prop->sink_dpn_prop),
469 if (!prop->sink_dpn_prop)
472 dpn = prop->sink_dpn_prop;
474 addr = prop->sink_ports;
475 for_each_set_bit(bit, &addr, 32) {
477 dpn[i].simple_ch_prep_sm = true;
478 dpn[i].ch_prep_timeout = 10;
482 /* Allocate port_ready based on num_of_ports */
483 slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports,
484 sizeof(*slave->port_ready),
486 if (!slave->port_ready)
489 /* Initialize completion */
490 for (i = 0; i < num_of_ports; i++)
491 init_completion(&slave->port_ready[i]);
493 /* set the timeout values */
494 prop->clk_stop_timeout = 20;
497 prop->wake_capable = 1;
502 static int rt715_bus_config(struct sdw_slave *slave,
503 struct sdw_bus_params *params)
505 struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev);
508 memcpy(&rt715->params, params, sizeof(*params));
510 ret = rt715_clock_config(&slave->dev);
512 dev_err(&slave->dev, "Invalid clk config");
517 static struct sdw_slave_ops rt715_slave_ops = {
518 .read_prop = rt715_read_prop,
519 .update_status = rt715_update_status,
520 .bus_config = rt715_bus_config,
523 static int rt715_sdw_probe(struct sdw_slave *slave,
524 const struct sdw_device_id *id)
526 struct regmap *sdw_regmap, *regmap;
529 slave->ops = &rt715_slave_ops;
531 /* Regmap Initialization */
532 sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap);
536 regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev,
539 return PTR_ERR(regmap);
541 rt715_init(&slave->dev, sdw_regmap, regmap, slave);
546 static const struct sdw_device_id rt715_id[] = {
547 SDW_SLAVE_ENTRY(0x025d, 0x715, 0),
550 MODULE_DEVICE_TABLE(sdw, rt715_id);
552 static int __maybe_unused rt715_dev_suspend(struct device *dev)
554 struct rt715_priv *rt715 = dev_get_drvdata(dev);
559 regcache_cache_only(rt715->regmap, true);
564 #define RT715_PROBE_TIMEOUT 2000
566 static int __maybe_unused rt715_dev_resume(struct device *dev)
568 struct sdw_slave *slave = dev_to_sdw_dev(dev);
569 struct rt715_priv *rt715 = dev_get_drvdata(dev);
575 if (!slave->unattach_request)
578 time = wait_for_completion_timeout(&slave->initialization_complete,
579 msecs_to_jiffies(RT715_PROBE_TIMEOUT));
581 dev_err(&slave->dev, "Initialization not complete, timed out\n");
586 slave->unattach_request = 0;
587 regcache_cache_only(rt715->regmap, false);
588 regcache_sync_region(rt715->regmap, 0x3000, 0x8fff);
589 regcache_sync_region(rt715->regmap, 0x752039, 0x752039);
594 static const struct dev_pm_ops rt715_pm = {
595 SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
596 SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
599 static struct sdw_driver rt715_sdw_driver = {
602 .owner = THIS_MODULE,
605 .probe = rt715_sdw_probe,
606 .ops = &rt715_slave_ops,
607 .id_table = rt715_id,
609 module_sdw_driver(rt715_sdw_driver);
611 MODULE_DESCRIPTION("ASoC RT715 driver SDW");
612 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
613 MODULE_LICENSE("GPL v2");