1 // SPDX-License-Identifier: GPL-2.0
3 // sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
5 // Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/module.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/slab.h>
13 #include <linux/i2c.h>
14 #include <linux/clk.h>
15 #include <linux/log2.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/of_device.h>
21 #include <sound/core.h>
22 #include <sound/tlv.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
31 #define SGTL5000_DAP_REG_OFFSET 0x0100
32 #define SGTL5000_MAX_REG_OFFSET 0x013A
34 /* default value of sgtl5000 registers */
35 static const struct reg_default sgtl5000_reg_defaults[] = {
36 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
37 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
38 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
39 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
40 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
41 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
42 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
43 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
44 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
45 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
46 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
47 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
48 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
49 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
50 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
51 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
52 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
53 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
54 { SGTL5000_DAP_CTRL, 0x0000 },
55 { SGTL5000_DAP_PEQ, 0x0000 },
56 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
57 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
58 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
59 { SGTL5000_DAP_SURROUND, 0x0040 },
60 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
61 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
62 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
63 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
64 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
65 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
66 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
67 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
68 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
69 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
70 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
73 /* AVC: Threshold dB -> register: pre-calculated values */
74 static const u16 avc_thr_db2reg[97] = {
75 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
76 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
77 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
78 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
79 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
80 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
81 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
82 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
83 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
84 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
85 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
87 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
88 enum sgtl5000_regulator_supplies {
95 /* vddd is optional supply */
96 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
102 #define LDO_VOLTAGE 1200000
103 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
105 enum sgtl5000_micbias_resistor {
106 SGTL5000_MICBIAS_OFF = 0,
107 SGTL5000_MICBIAS_2K = 2,
108 SGTL5000_MICBIAS_4K = 4,
109 SGTL5000_MICBIAS_8K = 8,
113 I2S_LRCLK_STRENGTH_DISABLE,
114 I2S_LRCLK_STRENGTH_LOW,
115 I2S_LRCLK_STRENGTH_MEDIUM,
116 I2S_LRCLK_STRENGTH_HIGH,
120 I2S_SCLK_STRENGTH_DISABLE,
121 I2S_SCLK_STRENGTH_LOW,
122 I2S_SCLK_STRENGTH_MEDIUM,
123 I2S_SCLK_STRENGTH_HIGH,
126 /* sgtl5000 private structure in codec */
127 struct sgtl5000_priv {
128 int sysclk; /* sysclk rate */
129 int master; /* i2s master or not */
130 int fmt; /* i2s data format */
131 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
133 struct regmap *regmap;
143 * mic_bias power on/off share the same register bits with
144 * output impedance of mic bias, when power on mic bias, we
145 * need reclaim it to impedance value.
151 static int mic_bias_event(struct snd_soc_dapm_widget *w,
152 struct snd_kcontrol *kcontrol, int event)
154 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
155 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
158 case SND_SOC_DAPM_POST_PMU:
159 /* change mic bias resistor */
160 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
161 SGTL5000_BIAS_R_MASK,
162 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
165 case SND_SOC_DAPM_PRE_PMD:
166 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
167 SGTL5000_BIAS_R_MASK, 0);
174 * As manual described, ADC/DAC only works when VAG powerup,
175 * So enabled VAG before ADC/DAC up.
176 * In power down case, we need wait 400ms when vag fully ramped down.
178 static int power_vag_event(struct snd_soc_dapm_widget *w,
179 struct snd_kcontrol *kcontrol, int event)
181 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
182 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
185 case SND_SOC_DAPM_POST_PMU:
186 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
187 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
191 case SND_SOC_DAPM_PRE_PMD:
193 * Don't clear VAG_POWERUP, when both DAC and ADC are
194 * operational to prevent inadvertently starving the
197 if ((snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER) &
199 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
200 SGTL5000_VAG_POWERUP, 0);
211 /* input sources for ADC */
212 static const char *adc_mux_text[] = {
216 static SOC_ENUM_SINGLE_DECL(adc_enum,
217 SGTL5000_CHIP_ANA_CTRL, 2,
220 static const struct snd_kcontrol_new adc_mux =
221 SOC_DAPM_ENUM("Capture Mux", adc_enum);
223 /* input sources for headphone */
224 static const char *hp_mux_text[] = {
228 static SOC_ENUM_SINGLE_DECL(hp_enum,
229 SGTL5000_CHIP_ANA_CTRL, 6,
232 static const struct snd_kcontrol_new hp_mux =
233 SOC_DAPM_ENUM("Headphone Mux", hp_enum);
235 /* input sources for DAC */
236 static const char *dac_mux_text[] = {
237 "ADC", "I2S", "Rsvrd", "DAP"
240 static SOC_ENUM_SINGLE_DECL(dac_enum,
241 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
244 static const struct snd_kcontrol_new dac_mux =
245 SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
247 /* input sources for DAP */
248 static const char *dap_mux_text[] = {
252 static SOC_ENUM_SINGLE_DECL(dap_enum,
253 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
256 static const struct snd_kcontrol_new dap_mux =
257 SOC_DAPM_ENUM("DAP Mux", dap_enum);
259 /* input sources for DAP mix */
260 static const char *dapmix_mux_text[] = {
264 static SOC_ENUM_SINGLE_DECL(dapmix_enum,
265 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
268 static const struct snd_kcontrol_new dapmix_mux =
269 SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
272 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
273 SND_SOC_DAPM_INPUT("LINE_IN"),
274 SND_SOC_DAPM_INPUT("MIC_IN"),
276 SND_SOC_DAPM_OUTPUT("HP_OUT"),
277 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
279 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
281 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
283 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
284 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
286 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
287 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
288 SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
289 SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
290 SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
291 SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
294 /* aif for i2s input */
295 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
296 0, SGTL5000_CHIP_DIG_POWER,
299 /* aif for i2s output */
300 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
301 0, SGTL5000_CHIP_DIG_POWER,
304 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
305 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
307 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
308 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
311 /* routes for sgtl5000 */
312 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
313 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
314 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
316 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
317 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
319 {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */
320 {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */
321 {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */
323 {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */
324 {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */
325 {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */
327 {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */
328 {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */
329 {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
330 {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
332 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
333 {"LO", NULL, "DAC"}, /* dac --> line_out */
335 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
336 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
338 {"LINE_OUT", NULL, "LO"},
339 {"HP_OUT", NULL, "HP"},
342 /* custom function to fetch info of PCM playback volume */
343 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
344 struct snd_ctl_elem_info *uinfo)
346 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
348 uinfo->value.integer.min = 0;
349 uinfo->value.integer.max = 0xfc - 0x3c;
354 * custom function to get of PCM playback volume
356 * dac volume register
357 * 15-------------8-7--------------0
358 * | R channel vol | L channel vol |
359 * -------------------------------
361 * PCM volume with 0.5017 dB steps from 0 to -90 dB
363 * register values map to dB
364 * 0x3B and less = Reserved
368 * 0xFC and greater = Muted
370 * register value map to userspace value
372 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
373 * ------------------------------
374 * userspace value 0xc0 0
376 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
377 struct snd_ctl_elem_value *ucontrol)
379 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
384 reg = snd_soc_component_read32(component, SGTL5000_CHIP_DAC_VOL);
386 /* get left channel volume */
387 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
389 /* get right channel volume */
390 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
392 /* make sure value fall in (0x3c,0xfc) */
393 l = clamp(l, 0x3c, 0xfc);
394 r = clamp(r, 0x3c, 0xfc);
396 /* invert it and map to userspace value */
400 ucontrol->value.integer.value[0] = l;
401 ucontrol->value.integer.value[1] = r;
407 * custom function to put of PCM playback volume
409 * dac volume register
410 * 15-------------8-7--------------0
411 * | R channel vol | L channel vol |
412 * -------------------------------
414 * PCM volume with 0.5017 dB steps from 0 to -90 dB
416 * register values map to dB
417 * 0x3B and less = Reserved
421 * 0xFC and greater = Muted
423 * userspace value map to register value
425 * userspace value 0xc0 0
426 * ------------------------------
427 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
429 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
430 struct snd_ctl_elem_value *ucontrol)
432 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
437 l = ucontrol->value.integer.value[0];
438 r = ucontrol->value.integer.value[1];
440 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
441 l = clamp(l, 0, 0xfc - 0x3c);
442 r = clamp(r, 0, 0xfc - 0x3c);
444 /* invert it, get the value can be set to register */
448 /* shift to get the register value */
449 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
450 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
452 snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
458 * custom function to get AVC threshold
460 * The threshold dB is calculated by rearranging the calculation from the
461 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
462 * dB = ( fls(register_value) - 14.347 ) * 6.02
464 * As this calculation is expensive and the threshold dB values may not exceed
465 * 0 to 96 we use pre-calculated values.
467 static int avc_get_threshold(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
470 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
472 u16 reg = snd_soc_component_read32(component, SGTL5000_DAP_AVC_THRESHOLD);
474 /* register value 0 => -96dB */
476 ucontrol->value.integer.value[0] = 96;
477 ucontrol->value.integer.value[1] = 96;
481 /* get dB from register value (rounded down) */
482 for (i = 0; avc_thr_db2reg[i] > reg; i++)
486 ucontrol->value.integer.value[0] = db;
487 ucontrol->value.integer.value[1] = db;
493 * custom function to put AVC threshold
495 * The register value is calculated by following formula:
496 * register_value = 10^(dB/20) * 0.636 * 2^15
497 * As this calculation is expensive and the threshold dB values may not exceed
498 * 0 to 96 we use pre-calculated values.
500 static int avc_put_threshold(struct snd_kcontrol *kcontrol,
501 struct snd_ctl_elem_value *ucontrol)
503 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
507 db = (int)ucontrol->value.integer.value[0];
508 if (db < 0 || db > 96)
510 reg = avc_thr_db2reg[db];
511 snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
516 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
518 /* tlv for mic gain, 0db 20db 30db 40db */
519 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
520 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
521 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
524 /* tlv for DAP channels, 0% - 100% - 200% */
525 static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
527 /* tlv for bass bands, -11.75db to 12.0db, step .25db */
528 static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
530 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
531 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
533 /* tlv for lineout volume, 31 steps of .5db each */
534 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
536 /* tlv for dap avc max gain, 0db, 6db, 12db */
537 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
539 /* tlv for dap avc threshold, */
540 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
542 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
543 /* SOC_DOUBLE_S8_TLV with invert */
545 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
546 .name = "PCM Playback Volume",
547 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
548 SNDRV_CTL_ELEM_ACCESS_READWRITE,
549 .info = dac_info_volsw,
550 .get = dac_get_volsw,
551 .put = dac_put_volsw,
554 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
555 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
556 SGTL5000_CHIP_ANA_ADC_CTRL,
557 8, 1, 0, capture_6db_attenuate),
558 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
560 SOC_DOUBLE_TLV("Headphone Playback Volume",
561 SGTL5000_CHIP_ANA_HP_CTRL,
565 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
567 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
570 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
571 0, 3, 0, mic_gain_tlv),
573 SOC_DOUBLE_TLV("Lineout Playback Volume",
574 SGTL5000_CHIP_LINE_OUT_VOL,
575 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
576 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
579 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
581 SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
582 0, 0xffff, 0, dap_volume),
584 SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
585 0, 0xffff, 0, dap_volume),
586 /* Automatic Volume Control (DAP AVC) */
587 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
588 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
589 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
591 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
592 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
593 0, 96, 0, avc_get_threshold, avc_put_threshold,
596 SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
597 0, 0x5F, 0, bass_band),
599 SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
600 0, 0x5F, 0, bass_band),
602 SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
603 0, 0x5F, 0, bass_band),
605 SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
606 0, 0x5F, 0, bass_band),
608 SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
609 0, 0x5F, 0, bass_band),
612 /* mute the codec used by alsa core */
613 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
615 struct snd_soc_component *component = codec_dai->component;
616 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
619 * During 'digital mute' do not mute DAC
620 * because LINE_IN would be muted aswell. We want to mute
621 * only I2S block - this can be done by powering it off
623 snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
624 i2s_pwr, mute ? 0 : i2s_pwr);
629 /* set codec format */
630 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
632 struct snd_soc_component *component = codec_dai->component;
633 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
636 sgtl5000->master = 0;
638 * i2s clock and frame master setting.
640 * - clock and frame slave,
641 * - clock and frame master
643 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
644 case SND_SOC_DAIFMT_CBS_CFS:
646 case SND_SOC_DAIFMT_CBM_CFM:
647 i2sctl |= SGTL5000_I2S_MASTER;
648 sgtl5000->master = 1;
654 /* setting i2s data format */
655 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
656 case SND_SOC_DAIFMT_DSP_A:
657 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
659 case SND_SOC_DAIFMT_DSP_B:
660 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
661 i2sctl |= SGTL5000_I2S_LRALIGN;
663 case SND_SOC_DAIFMT_I2S:
664 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
666 case SND_SOC_DAIFMT_RIGHT_J:
667 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
668 i2sctl |= SGTL5000_I2S_LRPOL;
670 case SND_SOC_DAIFMT_LEFT_J:
671 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
672 i2sctl |= SGTL5000_I2S_LRALIGN;
678 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
680 /* Clock inversion */
681 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
682 case SND_SOC_DAIFMT_NB_NF:
684 case SND_SOC_DAIFMT_IB_NF:
685 i2sctl |= SGTL5000_I2S_SCLK_INV;
691 snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
696 /* set codec sysclk */
697 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
698 int clk_id, unsigned int freq, int dir)
700 struct snd_soc_component *component = codec_dai->component;
701 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
704 case SGTL5000_SYSCLK:
705 sgtl5000->sysclk = freq;
715 * set clock according to i2s frame clock,
716 * sgtl5000 provides 2 clock sources:
717 * 1. sys_mclk: sample freq can only be configured to
718 * 1/256, 1/384, 1/512 of sys_mclk.
719 * 2. pll: can derive any audio clocks.
721 * clock setting rules:
722 * 1. in slave mode, only sys_mclk can be used
723 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
725 * 3. usage of sys_mclk is preferred over pll to save power.
727 static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
729 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
731 int sys_fs; /* sample freq */
734 * sample freq should be divided by frame clock,
735 * if frame clock is lower than 44.1 kHz, sample freq should be set to
736 * 32 kHz or 44.1 kHz.
738 switch (frame_rate) {
752 /* set divided factor of frame clock */
753 switch (sys_fs / frame_rate) {
755 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
758 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
761 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
767 /* set the sys_fs according to frame rate */
770 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
773 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
776 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
779 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
782 dev_err(component->dev, "frame rate %d not supported\n",
788 * calculate the divider of mclk/sample_freq,
789 * factor of freq = 96 kHz can only be 256, since mclk is in the range
792 switch (sgtl5000->sysclk / frame_rate) {
794 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
795 SGTL5000_MCLK_FREQ_SHIFT;
798 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
799 SGTL5000_MCLK_FREQ_SHIFT;
802 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
803 SGTL5000_MCLK_FREQ_SHIFT;
806 /* if mclk does not satisfy the divider, use pll */
807 if (sgtl5000->master) {
808 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
809 SGTL5000_MCLK_FREQ_SHIFT;
811 dev_err(component->dev,
812 "PLL not supported in slave mode\n");
813 dev_err(component->dev, "%d ratio is not supported. "
814 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
815 sgtl5000->sysclk / frame_rate);
820 /* if using pll, please check manual 6.4.2 for detail */
821 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
825 unsigned int in, int_div, frac_div;
827 if (sgtl5000->sysclk > 17000000) {
829 in = sgtl5000->sysclk / 2;
832 in = sgtl5000->sysclk;
843 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
844 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
846 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
848 snd_soc_component_update_bits(component,
849 SGTL5000_CHIP_CLK_TOP_CTRL,
850 SGTL5000_INPUT_FREQ_DIV2,
851 SGTL5000_INPUT_FREQ_DIV2);
853 snd_soc_component_update_bits(component,
854 SGTL5000_CHIP_CLK_TOP_CTRL,
855 SGTL5000_INPUT_FREQ_DIV2,
859 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
860 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
861 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
863 /* if using pll, clk_ctrl must be set after pll power up */
864 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
866 /* otherwise, clk_ctrl must be set before pll power down */
867 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
870 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
871 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
879 * Set PCM DAI bit size and sample rate.
880 * input: params_rate, params_fmt
882 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
883 struct snd_pcm_hw_params *params,
884 struct snd_soc_dai *dai)
886 struct snd_soc_component *component = dai->component;
887 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
888 int channels = params_channels(params);
893 /* sysclk should already set */
894 if (!sgtl5000->sysclk) {
895 dev_err(component->dev, "%s: set sysclk first!\n", __func__);
899 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
900 stereo = SGTL5000_DAC_STEREO;
902 stereo = SGTL5000_ADC_STEREO;
904 /* set mono to save power */
905 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
906 channels == 1 ? 0 : stereo);
908 /* set codec clock base on lrclk */
909 ret = sgtl5000_set_clock(component, params_rate(params));
913 /* set i2s data format */
914 switch (params_width(params)) {
916 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
918 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
919 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
920 SGTL5000_I2S_SCLKFREQ_SHIFT;
923 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
924 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
925 SGTL5000_I2S_SCLKFREQ_SHIFT;
928 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
929 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
930 SGTL5000_I2S_SCLKFREQ_SHIFT;
933 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
935 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
936 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
937 SGTL5000_I2S_SCLKFREQ_SHIFT;
943 snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
944 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
952 * common state changes:
954 * off --> standby --> prepare --> on
955 * standby --> prepare --> on
958 * on --> prepare --> standby
960 static int sgtl5000_set_bias_level(struct snd_soc_component *component,
961 enum snd_soc_bias_level level)
963 struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
967 case SND_SOC_BIAS_ON:
968 case SND_SOC_BIAS_PREPARE:
969 case SND_SOC_BIAS_STANDBY:
970 regcache_cache_only(sgtl->regmap, false);
971 ret = regcache_sync(sgtl->regmap);
973 regcache_cache_only(sgtl->regmap, true);
977 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
978 SGTL5000_REFTOP_POWERUP,
979 SGTL5000_REFTOP_POWERUP);
981 case SND_SOC_BIAS_OFF:
982 regcache_cache_only(sgtl->regmap, true);
983 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
984 SGTL5000_REFTOP_POWERUP, 0);
991 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
992 SNDRV_PCM_FMTBIT_S20_3LE |\
993 SNDRV_PCM_FMTBIT_S24_LE |\
994 SNDRV_PCM_FMTBIT_S32_LE)
996 static const struct snd_soc_dai_ops sgtl5000_ops = {
997 .hw_params = sgtl5000_pcm_hw_params,
998 .digital_mute = sgtl5000_digital_mute,
999 .set_fmt = sgtl5000_set_dai_fmt,
1000 .set_sysclk = sgtl5000_set_dai_sysclk,
1003 static struct snd_soc_dai_driver sgtl5000_dai = {
1006 .stream_name = "Playback",
1010 * only support 8~48K + 96K,
1011 * TODO modify hw_param to support more
1013 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1014 .formats = SGTL5000_FORMATS,
1017 .stream_name = "Capture",
1020 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1021 .formats = SGTL5000_FORMATS,
1023 .ops = &sgtl5000_ops,
1024 .symmetric_rates = 1,
1027 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1030 case SGTL5000_CHIP_ID:
1031 case SGTL5000_CHIP_ADCDAC_CTRL:
1032 case SGTL5000_CHIP_ANA_STATUS:
1039 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1042 case SGTL5000_CHIP_ID:
1043 case SGTL5000_CHIP_DIG_POWER:
1044 case SGTL5000_CHIP_CLK_CTRL:
1045 case SGTL5000_CHIP_I2S_CTRL:
1046 case SGTL5000_CHIP_SSS_CTRL:
1047 case SGTL5000_CHIP_ADCDAC_CTRL:
1048 case SGTL5000_CHIP_DAC_VOL:
1049 case SGTL5000_CHIP_PAD_STRENGTH:
1050 case SGTL5000_CHIP_ANA_ADC_CTRL:
1051 case SGTL5000_CHIP_ANA_HP_CTRL:
1052 case SGTL5000_CHIP_ANA_CTRL:
1053 case SGTL5000_CHIP_LINREG_CTRL:
1054 case SGTL5000_CHIP_REF_CTRL:
1055 case SGTL5000_CHIP_MIC_CTRL:
1056 case SGTL5000_CHIP_LINE_OUT_CTRL:
1057 case SGTL5000_CHIP_LINE_OUT_VOL:
1058 case SGTL5000_CHIP_ANA_POWER:
1059 case SGTL5000_CHIP_PLL_CTRL:
1060 case SGTL5000_CHIP_CLK_TOP_CTRL:
1061 case SGTL5000_CHIP_ANA_STATUS:
1062 case SGTL5000_CHIP_SHORT_CTRL:
1063 case SGTL5000_CHIP_ANA_TEST2:
1064 case SGTL5000_DAP_CTRL:
1065 case SGTL5000_DAP_PEQ:
1066 case SGTL5000_DAP_BASS_ENHANCE:
1067 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1068 case SGTL5000_DAP_AUDIO_EQ:
1069 case SGTL5000_DAP_SURROUND:
1070 case SGTL5000_DAP_FLT_COEF_ACCESS:
1071 case SGTL5000_DAP_COEF_WR_B0_MSB:
1072 case SGTL5000_DAP_COEF_WR_B0_LSB:
1073 case SGTL5000_DAP_EQ_BASS_BAND0:
1074 case SGTL5000_DAP_EQ_BASS_BAND1:
1075 case SGTL5000_DAP_EQ_BASS_BAND2:
1076 case SGTL5000_DAP_EQ_BASS_BAND3:
1077 case SGTL5000_DAP_EQ_BASS_BAND4:
1078 case SGTL5000_DAP_MAIN_CHAN:
1079 case SGTL5000_DAP_MIX_CHAN:
1080 case SGTL5000_DAP_AVC_CTRL:
1081 case SGTL5000_DAP_AVC_THRESHOLD:
1082 case SGTL5000_DAP_AVC_ATTACK:
1083 case SGTL5000_DAP_AVC_DECAY:
1084 case SGTL5000_DAP_COEF_WR_B1_MSB:
1085 case SGTL5000_DAP_COEF_WR_B1_LSB:
1086 case SGTL5000_DAP_COEF_WR_B2_MSB:
1087 case SGTL5000_DAP_COEF_WR_B2_LSB:
1088 case SGTL5000_DAP_COEF_WR_A1_MSB:
1089 case SGTL5000_DAP_COEF_WR_A1_LSB:
1090 case SGTL5000_DAP_COEF_WR_A2_MSB:
1091 case SGTL5000_DAP_COEF_WR_A2_LSB:
1100 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1101 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1102 * The calculatation was done for all possible register values which
1103 * is the array index and the following formula: 10^((idx−15)/40) * 100
1105 static const u8 vol_quot_table[] = {
1106 42, 45, 47, 50, 53, 56, 60, 63,
1107 67, 71, 75, 79, 84, 89, 94, 100,
1108 106, 112, 119, 126, 133, 141, 150, 158,
1109 168, 178, 188, 200, 211, 224, 237, 251
1113 * sgtl5000 has 3 internal power supplies:
1114 * 1. VAG, normally set to vdda/2
1115 * 2. charge pump, set to different value
1116 * according to voltage of vdda and vddio
1117 * 3. line out VAG, normally set to vddio/2
1119 * and should be set according to:
1120 * 1. vddd provided by external or not
1121 * 2. vdda and vddio voltage value. > 3.1v or not
1123 static int sgtl5000_set_power_regs(struct snd_soc_component *component)
1135 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1137 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1138 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1139 vddd = (sgtl5000->num_supplies > VDDD)
1140 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1144 vddio = vddio / 1000;
1147 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1148 dev_err(component->dev, "regulator voltage not set correctly\n");
1153 /* according to datasheet, maximum voltage of supplies */
1154 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1155 dev_err(component->dev,
1156 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1163 ana_pwr = snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER);
1164 ana_pwr |= SGTL5000_DAC_STEREO |
1165 SGTL5000_ADC_STEREO |
1166 SGTL5000_REFTOP_POWERUP;
1167 lreg_ctrl = snd_soc_component_read32(component, SGTL5000_CHIP_LINREG_CTRL);
1169 if (vddio < 3100 && vdda < 3100) {
1170 /* enable internal oscillator used for charge pump */
1171 snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
1172 SGTL5000_INT_OSC_EN,
1173 SGTL5000_INT_OSC_EN);
1174 /* Enable VDDC charge pump */
1175 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1176 } else if (vddio >= 3100 && vdda >= 3100) {
1177 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1178 /* VDDC use VDDIO rail */
1179 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1180 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1181 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1184 snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1186 snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1189 * set ADC/DAC VAG to vdda / 2,
1190 * should stay in range (0.8v, 1.575v)
1193 if (vag <= SGTL5000_ANA_GND_BASE)
1195 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1196 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1197 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1199 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1201 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1202 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1204 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1206 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1208 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1209 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1210 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1212 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1213 SGTL5000_LINE_OUT_GND_STP;
1215 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
1216 SGTL5000_LINE_OUT_CURRENT_MASK |
1217 SGTL5000_LINE_OUT_GND_MASK,
1218 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1219 SGTL5000_LINE_OUT_CURRENT_360u <<
1220 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1223 * Set lineout output level in range (0..31)
1224 * the same value is used for right and left channel
1226 * Searching for a suitable index solving this formula:
1227 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1229 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1231 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1232 if (vol_quot >= vol_quot_table[i])
1238 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
1239 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1240 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1241 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1242 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1247 static int sgtl5000_enable_regulators(struct i2c_client *client)
1251 int external_vddd = 0;
1252 struct regulator *vddd;
1253 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1255 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1256 sgtl5000->supplies[i].supply = supply_names[i];
1258 vddd = regulator_get_optional(&client->dev, "VDDD");
1260 /* See if it's just not registered yet */
1261 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1262 return -EPROBE_DEFER;
1265 regulator_put(vddd);
1268 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1269 - 1 + external_vddd;
1270 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1271 sgtl5000->supplies);
1275 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1276 sgtl5000->supplies);
1278 usleep_range(10, 20);
1280 regulator_bulk_free(sgtl5000->num_supplies,
1281 sgtl5000->supplies);
1286 static int sgtl5000_probe(struct snd_soc_component *component)
1290 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1292 /* power up sgtl5000 */
1293 ret = sgtl5000_set_power_regs(component);
1297 /* enable small pop, introduce 400ms delay in turning off */
1298 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1299 SGTL5000_SMALL_POP, 1);
1301 /* disable short cut detector */
1302 snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
1304 snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
1305 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1307 /* enable dac volume ramp by default */
1308 snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
1309 SGTL5000_DAC_VOL_RAMP_EN |
1310 SGTL5000_DAC_MUTE_RIGHT |
1311 SGTL5000_DAC_MUTE_LEFT);
1313 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT |
1314 (sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT |
1316 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
1318 snd_soc_component_write(component, SGTL5000_CHIP_ANA_CTRL,
1319 SGTL5000_HP_ZCD_EN |
1320 SGTL5000_ADC_ZCD_EN);
1322 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1323 SGTL5000_BIAS_R_MASK,
1324 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1326 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1327 SGTL5000_BIAS_VOLT_MASK,
1328 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1330 * enable DAP Graphic EQ
1332 * Add control for changing between PEQ/Tone Control/GEQ
1334 snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
1336 /* Unmute DAC after start */
1337 snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
1338 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
1346 static const struct snd_soc_component_driver sgtl5000_driver = {
1347 .probe = sgtl5000_probe,
1348 .set_bias_level = sgtl5000_set_bias_level,
1349 .controls = sgtl5000_snd_controls,
1350 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1351 .dapm_widgets = sgtl5000_dapm_widgets,
1352 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1353 .dapm_routes = sgtl5000_dapm_routes,
1354 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1355 .suspend_bias_off = 1,
1357 .use_pmdown_time = 1,
1359 .non_legacy_dai_naming = 1,
1362 static const struct regmap_config sgtl5000_regmap = {
1367 .max_register = SGTL5000_MAX_REG_OFFSET,
1368 .volatile_reg = sgtl5000_volatile,
1369 .readable_reg = sgtl5000_readable,
1371 .cache_type = REGCACHE_RBTREE,
1372 .reg_defaults = sgtl5000_reg_defaults,
1373 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1377 * Write all the default values from sgtl5000_reg_defaults[] array into the
1378 * sgtl5000 registers, to make sure we always start with the sane registers
1379 * values as stated in the datasheet.
1381 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1382 * we follow this approach to guarantee we always start from the default values
1383 * and avoid problems like, not being able to probe after an audio playback
1384 * followed by a system reset or a 'reboot' command in Linux
1386 static void sgtl5000_fill_defaults(struct i2c_client *client)
1388 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1389 int i, ret, val, index;
1391 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1392 val = sgtl5000_reg_defaults[i].def;
1393 index = sgtl5000_reg_defaults[i].reg;
1394 ret = regmap_write(sgtl5000->regmap, index, val);
1396 dev_err(&client->dev,
1397 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1398 __func__, ret, index, val);
1402 static int sgtl5000_i2c_probe(struct i2c_client *client,
1403 const struct i2c_device_id *id)
1405 struct sgtl5000_priv *sgtl5000;
1407 struct device_node *np = client->dev.of_node;
1411 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1415 i2c_set_clientdata(client, sgtl5000);
1417 ret = sgtl5000_enable_regulators(client);
1421 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1422 if (IS_ERR(sgtl5000->regmap)) {
1423 ret = PTR_ERR(sgtl5000->regmap);
1424 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1428 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1429 if (IS_ERR(sgtl5000->mclk)) {
1430 ret = PTR_ERR(sgtl5000->mclk);
1431 /* Defer the probe to see if the clk will be provided later */
1433 ret = -EPROBE_DEFER;
1435 if (ret != -EPROBE_DEFER)
1436 dev_err(&client->dev, "Failed to get mclock: %d\n",
1441 ret = clk_prepare_enable(sgtl5000->mclk);
1443 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1447 /* Need 8 clocks before I2C accesses */
1450 /* read chip information */
1451 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1453 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1457 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1458 SGTL5000_PARTID_PART_ID) {
1459 dev_err(&client->dev,
1460 "Device with ID register %x is not a sgtl5000\n", reg);
1465 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1466 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1467 sgtl5000->revision = rev;
1469 /* reconfigure the clocks in case we're using the PLL */
1470 ret = regmap_write(sgtl5000->regmap,
1471 SGTL5000_CHIP_CLK_CTRL,
1472 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1474 dev_err(&client->dev,
1475 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1477 /* Follow section 2.2.1.1 of AN3663 */
1478 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1479 if (sgtl5000->num_supplies <= VDDD) {
1480 /* internal VDDD at 1.2V */
1481 ret = regmap_update_bits(sgtl5000->regmap,
1482 SGTL5000_CHIP_LINREG_CTRL,
1483 SGTL5000_LINREG_VDDD_MASK,
1486 dev_err(&client->dev,
1487 "Error %d setting LINREG_VDDD\n", ret);
1489 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1490 dev_info(&client->dev,
1491 "Using internal LDO instead of VDDD: check ER1 erratum\n");
1493 /* using external LDO for VDDD
1494 * Clear startup powerup and simple powerup
1495 * bits to save power
1497 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1498 | SGTL5000_LINREG_SIMPLE_POWERUP);
1499 dev_dbg(&client->dev, "Using external VDDD\n");
1501 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1503 dev_err(&client->dev,
1504 "Error %d setting CHIP_ANA_POWER to %04x\n",
1508 if (!of_property_read_u32(np,
1509 "micbias-resistor-k-ohms", &value)) {
1511 case SGTL5000_MICBIAS_OFF:
1512 sgtl5000->micbias_resistor = 0;
1514 case SGTL5000_MICBIAS_2K:
1515 sgtl5000->micbias_resistor = 1;
1517 case SGTL5000_MICBIAS_4K:
1518 sgtl5000->micbias_resistor = 2;
1520 case SGTL5000_MICBIAS_8K:
1521 sgtl5000->micbias_resistor = 3;
1524 sgtl5000->micbias_resistor = 2;
1525 dev_err(&client->dev,
1526 "Unsuitable MicBias resistor\n");
1529 /* default is 4Kohms */
1530 sgtl5000->micbias_resistor = 2;
1532 if (!of_property_read_u32(np,
1533 "micbias-voltage-m-volts", &value)) {
1535 /* steps of 250mV */
1536 if ((value >= 1250) && (value <= 3000))
1537 sgtl5000->micbias_voltage = (value / 250) - 5;
1539 sgtl5000->micbias_voltage = 0;
1540 dev_err(&client->dev,
1541 "Unsuitable MicBias voltage\n");
1544 sgtl5000->micbias_voltage = 0;
1548 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1549 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1550 if (value > I2S_LRCLK_STRENGTH_HIGH)
1551 value = I2S_LRCLK_STRENGTH_LOW;
1552 sgtl5000->lrclk_strength = value;
1555 sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW;
1556 if (!of_property_read_u32(np, "sclk-strength", &value)) {
1557 if (value > I2S_SCLK_STRENGTH_HIGH)
1558 value = I2S_SCLK_STRENGTH_LOW;
1559 sgtl5000->sclk_strength = value;
1562 /* Ensure sgtl5000 will start with sane register values */
1563 sgtl5000_fill_defaults(client);
1565 ret = devm_snd_soc_register_component(&client->dev,
1566 &sgtl5000_driver, &sgtl5000_dai, 1);
1573 clk_disable_unprepare(sgtl5000->mclk);
1576 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1577 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1582 static int sgtl5000_i2c_remove(struct i2c_client *client)
1584 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1586 clk_disable_unprepare(sgtl5000->mclk);
1587 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1588 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1593 static const struct i2c_device_id sgtl5000_id[] = {
1598 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1600 static const struct of_device_id sgtl5000_dt_ids[] = {
1601 { .compatible = "fsl,sgtl5000", },
1604 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1606 static struct i2c_driver sgtl5000_i2c_driver = {
1609 .of_match_table = sgtl5000_dt_ids,
1611 .probe = sgtl5000_i2c_probe,
1612 .remove = sgtl5000_i2c_remove,
1613 .id_table = sgtl5000_id,
1616 module_i2c_driver(sgtl5000_i2c_driver);
1618 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1619 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1620 MODULE_LICENSE("GPL");