sound/soc/codecs/wcd9335.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   3 // Copyright (c) 2017-2018, Linaro Limited
   4
   5 #include <linux/module.h>
   6 #include <linux/init.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/device.h>
   9 #include <linux/wait.h>
  10 #include <linux/bitops.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slimbus.h>
  16 #include <sound/soc.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc-dapm.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <sound/tlv.h>
  23 #include <sound/info.h>
  24 #include "wcd9335.h"
  25 #include "wcd-clsh-v2.h"
  26
  27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  28                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  29                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  30 /* Fractional Rates */
  31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
  32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  33                                   SNDRV_PCM_FMTBIT_S24_LE)
  34
  35 /* slave port water mark level
  36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  37  */
  38 #define SLAVE_PORT_WATER_MARK_6BYTES  0
  39 #define SLAVE_PORT_WATER_MARK_9BYTES  1
  40 #define SLAVE_PORT_WATER_MARK_12BYTES 2
  41 #define SLAVE_PORT_WATER_MARK_15BYTES 3
  42 #define SLAVE_PORT_WATER_MARK_SHIFT 1
  43 #define SLAVE_PORT_ENABLE           1
  44 #define SLAVE_PORT_DISABLE          0
  45 #define WCD9335_SLIM_WATER_MARK_VAL \
  46         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  47          (SLAVE_PORT_ENABLE))
  48
  49 #define WCD9335_SLIM_NUM_PORT_REG 3
  50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
  51
  52 #define WCD9335_MCLK_CLK_12P288MHZ      12288000
  53 #define WCD9335_MCLK_CLK_9P6MHZ         9600000
  54
  55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
  56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
  57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
  58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
  59
  60 #define WCD9335_NUM_INTERPOLATORS 9
  61 #define WCD9335_RX_START        16
  62 #define WCD9335_SLIM_CH_START 128
  63 #define WCD9335_MAX_MICBIAS 4
  64 #define WCD9335_MAX_VALID_ADC_MUX  13
  65 #define WCD9335_INVALID_ADC_MUX 9
  66
  67 #define  TX_HPF_CUT_OFF_FREQ_MASK       0x60
  68 #define  CF_MIN_3DB_4HZ                 0x0
  69 #define  CF_MIN_3DB_75HZ                0x1
  70 #define  CF_MIN_3DB_150HZ               0x2
  71 #define WCD9335_DMIC_CLK_DIV_2  0x0
  72 #define WCD9335_DMIC_CLK_DIV_3  0x1
  73 #define WCD9335_DMIC_CLK_DIV_4  0x2
  74 #define WCD9335_DMIC_CLK_DIV_6  0x3
  75 #define WCD9335_DMIC_CLK_DIV_8  0x4
  76 #define WCD9335_DMIC_CLK_DIV_16  0x5
  77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
  78 #define WCD9335_AMIC_PWR_LEVEL_LP 0
  79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
  80 #define WCD9335_AMIC_PWR_LEVEL_HP 2
  81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
  82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
  83
  84 #define WCD9335_DEC_PWR_LVL_MASK 0x06
  85 #define WCD9335_DEC_PWR_LVL_LP 0x02
  86 #define WCD9335_DEC_PWR_LVL_HP 0x04
  87 #define WCD9335_DEC_PWR_LVL_DF 0x00
  88
  89 #define WCD9335_SLIM_RX_CH(p) \
  90         {.port = p + WCD9335_RX_START, .shift = p,}
  91
  92 #define WCD9335_SLIM_TX_CH(p) \
  93         {.port = p, .shift = p,}
  94
  95 /* vout step value */
  96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
  97
  98 #define WCD9335_INTERPOLATOR_PATH(id)                   \
  99         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 100         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 101         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 102         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 103         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 104         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 105         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 106         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 107         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 108         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 109         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 110         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 111         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 112         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 113         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 114         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 115         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 116         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 117         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 118         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 119         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 120         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 121         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 122         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 123         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 124         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 125         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 126         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 127         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 128         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 129         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 130         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 131         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"},    \
 132         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"},    \
 133         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"},    \
 134         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"},         \
 135         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"},        \
 136         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"},          \
 137         {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
 138
 139 #define WCD9335_ADC_MUX_PATH(id)                        \
 140         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 141         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 142         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 143         {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
 144         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id},        \
 145         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id},        \
 146         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 147         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 148         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 149         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 150         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 151         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 152         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 153         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 154         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 155         {"AMIC MUX" #id, "ADC4", "ADC4"},               \
 156         {"AMIC MUX" #id, "ADC5", "ADC5"},               \
 157         {"AMIC MUX" #id, "ADC6", "ADC6"}
 158
 159 enum {
 160         WCD9335_RX0 = 0,
 161         WCD9335_RX1,
 162         WCD9335_RX2,
 163         WCD9335_RX3,
 164         WCD9335_RX4,
 165         WCD9335_RX5,
 166         WCD9335_RX6,
 167         WCD9335_RX7,
 168         WCD9335_RX8,
 169         WCD9335_RX9,
 170         WCD9335_RX10,
 171         WCD9335_RX11,
 172         WCD9335_RX12,
 173         WCD9335_RX_MAX,
 174 };
 175
 176 enum {
 177         WCD9335_TX0 = 0,
 178         WCD9335_TX1,
 179         WCD9335_TX2,
 180         WCD9335_TX3,
 181         WCD9335_TX4,
 182         WCD9335_TX5,
 183         WCD9335_TX6,
 184         WCD9335_TX7,
 185         WCD9335_TX8,
 186         WCD9335_TX9,
 187         WCD9335_TX10,
 188         WCD9335_TX11,
 189         WCD9335_TX12,
 190         WCD9335_TX13,
 191         WCD9335_TX14,
 192         WCD9335_TX15,
 193         WCD9335_TX_MAX,
 194 };
 195
 196 enum {
 197         SIDO_SOURCE_INTERNAL = 0,
 198         SIDO_SOURCE_RCO_BG,
 199 };
 200
 201 enum wcd9335_sido_voltage {
 202         SIDO_VOLTAGE_SVS_MV = 950,
 203         SIDO_VOLTAGE_NOMINAL_MV = 1100,
 204 };
 205
 206 enum {
 207         AIF1_PB = 0,
 208         AIF1_CAP,
 209         AIF2_PB,
 210         AIF2_CAP,
 211         AIF3_PB,
 212         AIF3_CAP,
 213         AIF4_PB,
 214         NUM_CODEC_DAIS,
 215 };
 216
 217 enum {
 218         COMPANDER_1, /* HPH_L */
 219         COMPANDER_2, /* HPH_R */
 220         COMPANDER_3, /* LO1_DIFF */
 221         COMPANDER_4, /* LO2_DIFF */
 222         COMPANDER_5, /* LO3_SE */
 223         COMPANDER_6, /* LO4_SE */
 224         COMPANDER_7, /* SWR SPK CH1 */
 225         COMPANDER_8, /* SWR SPK CH2 */
 226         COMPANDER_MAX,
 227 };
 228
 229 enum {
 230         INTn_2_INP_SEL_ZERO = 0,
 231         INTn_2_INP_SEL_RX0,
 232         INTn_2_INP_SEL_RX1,
 233         INTn_2_INP_SEL_RX2,
 234         INTn_2_INP_SEL_RX3,
 235         INTn_2_INP_SEL_RX4,
 236         INTn_2_INP_SEL_RX5,
 237         INTn_2_INP_SEL_RX6,
 238         INTn_2_INP_SEL_RX7,
 239         INTn_2_INP_SEL_PROXIMITY,
 240 };
 241
 242 enum {
 243         INTn_1_MIX_INP_SEL_ZERO = 0,
 244         INTn_1_MIX_INP_SEL_DEC0,
 245         INTn_1_MIX_INP_SEL_DEC1,
 246         INTn_1_MIX_INP_SEL_IIR0,
 247         INTn_1_MIX_INP_SEL_IIR1,
 248         INTn_1_MIX_INP_SEL_RX0,
 249         INTn_1_MIX_INP_SEL_RX1,
 250         INTn_1_MIX_INP_SEL_RX2,
 251         INTn_1_MIX_INP_SEL_RX3,
 252         INTn_1_MIX_INP_SEL_RX4,
 253         INTn_1_MIX_INP_SEL_RX5,
 254         INTn_1_MIX_INP_SEL_RX6,
 255         INTn_1_MIX_INP_SEL_RX7,
 256
 257 };
 258
 259 enum {
 260         INTERP_EAR = 0,
 261         INTERP_HPHL,
 262         INTERP_HPHR,
 263         INTERP_LO1,
 264         INTERP_LO2,
 265         INTERP_LO3,
 266         INTERP_LO4,
 267         INTERP_SPKR1,
 268         INTERP_SPKR2,
 269 };
 270
 271 enum wcd_clock_type {
 272         WCD_CLK_OFF,
 273         WCD_CLK_RCO,
 274         WCD_CLK_MCLK,
 275 };
 276
 277 enum {
 278         MIC_BIAS_1 = 1,
 279         MIC_BIAS_2,
 280         MIC_BIAS_3,
 281         MIC_BIAS_4
 282 };
 283
 284 enum {
 285         MICB_PULLUP_ENABLE,
 286         MICB_PULLUP_DISABLE,
 287         MICB_ENABLE,
 288         MICB_DISABLE,
 289 };
 290
 291 struct wcd9335_slim_ch {
 292         u32 ch_num;
 293         u16 port;
 294         u16 shift;
 295         struct list_head list;
 296 };
 297
 298 struct wcd_slim_codec_dai_data {
 299         struct list_head slim_ch_list;
 300         struct slim_stream_config sconfig;
 301         struct slim_stream_runtime *sruntime;
 302 };
 303
 304 struct wcd9335_codec {
 305         struct device *dev;
 306         struct clk *mclk;
 307         struct clk *native_clk;
 308         u32 mclk_rate;
 309         u8 version;
 310
 311         struct slim_device *slim;
 312         struct slim_device *slim_ifc_dev;
 313         struct regmap *regmap;
 314         struct regmap *if_regmap;
 315         struct regmap_irq_chip_data *irq_data;
 316
 317         struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
 318         struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
 319         u32 num_rx_port;
 320         u32 num_tx_port;
 321
 322         int sido_input_src;
 323         enum wcd9335_sido_voltage sido_voltage;
 324
 325         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 326         struct snd_soc_component *component;
 327
 328         int master_bias_users;
 329         int clk_mclk_users;
 330         int clk_rco_users;
 331         int sido_ccl_cnt;
 332         enum wcd_clock_type clk_type;
 333
 334         struct wcd_clsh_ctrl *clsh_ctrl;
 335         u32 hph_mode;
 336         int prim_int_users[WCD9335_NUM_INTERPOLATORS];
 337
 338         int comp_enabled[COMPANDER_MAX];
 339
 340         int intr1;
 341         int reset_gpio;
 342         struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
 343
 344         unsigned int rx_port_value;
 345         unsigned int tx_port_value;
 346         int hph_l_gain;
 347         int hph_r_gain;
 348         u32 rx_bias_count;
 349
 350         /*TX*/
 351         int micb_ref[WCD9335_MAX_MICBIAS];
 352         int pullup_ref[WCD9335_MAX_MICBIAS];
 353
 354         int dmic_0_1_clk_cnt;
 355         int dmic_2_3_clk_cnt;
 356         int dmic_4_5_clk_cnt;
 357         int dmic_sample_rate;
 358         int mad_dmic_sample_rate;
 359
 360         int native_clk_users;
 361 };
 362
 363 struct wcd9335_irq {
 364         int irq;
 365         irqreturn_t (*handler)(int irq, void *data);
 366         char *name;
 367 };
 368
 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
 370         WCD9335_SLIM_TX_CH(0),
 371         WCD9335_SLIM_TX_CH(1),
 372         WCD9335_SLIM_TX_CH(2),
 373         WCD9335_SLIM_TX_CH(3),
 374         WCD9335_SLIM_TX_CH(4),
 375         WCD9335_SLIM_TX_CH(5),
 376         WCD9335_SLIM_TX_CH(6),
 377         WCD9335_SLIM_TX_CH(7),
 378         WCD9335_SLIM_TX_CH(8),
 379         WCD9335_SLIM_TX_CH(9),
 380         WCD9335_SLIM_TX_CH(10),
 381         WCD9335_SLIM_TX_CH(11),
 382         WCD9335_SLIM_TX_CH(12),
 383         WCD9335_SLIM_TX_CH(13),
 384         WCD9335_SLIM_TX_CH(14),
 385         WCD9335_SLIM_TX_CH(15),
 386 };
 387
 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
 389         WCD9335_SLIM_RX_CH(0),   /* 16 */
 390         WCD9335_SLIM_RX_CH(1),   /* 17 */
 391         WCD9335_SLIM_RX_CH(2),
 392         WCD9335_SLIM_RX_CH(3),
 393         WCD9335_SLIM_RX_CH(4),
 394         WCD9335_SLIM_RX_CH(5),
 395         WCD9335_SLIM_RX_CH(6),
 396         WCD9335_SLIM_RX_CH(7),
 397         WCD9335_SLIM_RX_CH(8),
 398         WCD9335_SLIM_RX_CH(9),
 399         WCD9335_SLIM_RX_CH(10),
 400         WCD9335_SLIM_RX_CH(11),
 401         WCD9335_SLIM_RX_CH(12),
 402 };
 403
 404 struct interp_sample_rate {
 405         int rate;
 406         int rate_val;
 407 };
 408
 409 static struct interp_sample_rate int_mix_rate_val[] = {
 410         {48000, 0x4},   /* 48K */
 411         {96000, 0x5},   /* 96K */
 412         {192000, 0x6},  /* 192K */
 413 };
 414
 415 static struct interp_sample_rate int_prim_rate_val[] = {
 416         {8000, 0x0},    /* 8K */
 417         {16000, 0x1},   /* 16K */
 418         {24000, -EINVAL},/* 24K */
 419         {32000, 0x3},   /* 32K */
 420         {48000, 0x4},   /* 48K */
 421         {96000, 0x5},   /* 96K */
 422         {192000, 0x6},  /* 192K */
 423         {384000, 0x7},  /* 384K */
 424         {44100, 0x8}, /* 44.1K */
 425 };
 426
 427 struct wcd9335_reg_mask_val {
 428         u16 reg;
 429         u8 mask;
 430         u8 val;
 431 };
 432
 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
 434         /* Rbuckfly/R_EAR(32) */
 435         {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
 436         {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
 437         {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
 438         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
 439         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
 440         {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
 441         {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
 442         {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
 443         {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
 444         {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
 445         {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
 446         {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
 447         {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
 448         {WCD9335_EAR_CMBUFF, 0x08, 0x00},
 449         {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 450         {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 451         {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 452         {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 453         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
 454         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
 455         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
 456         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
 457         {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
 458         {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
 459         {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
 460         {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
 461         {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
 462         {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
 463         {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
 464         {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
 465         {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
 466         {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
 467         {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
 468         {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
 469         {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
 470         {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
 471         {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
 472         {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
 473         {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
 474         {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
 475         {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
 476         {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
 477         {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
 478         {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
 479         {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
 480         {WCD9335_HPH_L_TEST, 0x01, 0x01},
 481         {WCD9335_HPH_R_TEST, 0x01, 0x01},
 482         {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
 483         {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
 484         {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
 485         {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
 486         {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
 487         {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
 488         {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
 489         {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
 490         {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
 491         {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
 492 };
 493
 494 /* Cutoff frequency for high pass filter */
 495 static const char * const cf_text[] = {
 496         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 497 };
 498
 499 static const char * const rx_cf_text[] = {
 500         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 501         "CF_NEG_3DB_0P48HZ"
 502 };
 503
 504 static const char * const rx_int0_7_mix_mux_text[] = {
 505         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 506         "RX6", "RX7", "PROXIMITY"
 507 };
 508
 509 static const char * const rx_int_mix_mux_text[] = {
 510         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 511         "RX6", "RX7"
 512 };
 513
 514 static const char * const rx_prim_mix_text[] = {
 515         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 516         "RX3", "RX4", "RX5", "RX6", "RX7"
 517 };
 518
 519 static const char * const rx_int_dem_inp_mux_text[] = {
 520         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 521 };
 522
 523 static const char * const rx_int0_interp_mux_text[] = {
 524         "ZERO", "RX INT0 MIX2",
 525 };
 526
 527 static const char * const rx_int1_interp_mux_text[] = {
 528         "ZERO", "RX INT1 MIX2",
 529 };
 530
 531 static const char * const rx_int2_interp_mux_text[] = {
 532         "ZERO", "RX INT2 MIX2",
 533 };
 534
 535 static const char * const rx_int3_interp_mux_text[] = {
 536         "ZERO", "RX INT3 MIX2",
 537 };
 538
 539 static const char * const rx_int4_interp_mux_text[] = {
 540         "ZERO", "RX INT4 MIX2",
 541 };
 542
 543 static const char * const rx_int5_interp_mux_text[] = {
 544         "ZERO", "RX INT5 MIX2",
 545 };
 546
 547 static const char * const rx_int6_interp_mux_text[] = {
 548         "ZERO", "RX INT6 MIX2",
 549 };
 550
 551 static const char * const rx_int7_interp_mux_text[] = {
 552         "ZERO", "RX INT7 MIX2",
 553 };
 554
 555 static const char * const rx_int8_interp_mux_text[] = {
 556         "ZERO", "RX INT8 SEC MIX"
 557 };
 558
 559 static const char * const rx_hph_mode_mux_text[] = {
 560         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 561         "Class-H Hi-Fi Low Power"
 562 };
 563
 564 static const char *const slim_rx_mux_text[] = {
 565         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 566 };
 567
 568 static const char * const adc_mux_text[] = {
 569         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 570 };
 571
 572 static const char * const dmic_mux_text[] = {
 573         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 574         "SMIC0", "SMIC1", "SMIC2", "SMIC3"
 575 };
 576
 577 static const char * const dmic_mux_alt_text[] = {
 578         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 579 };
 580
 581 static const char * const amic_mux_text[] = {
 582         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
 583 };
 584
 585 static const char * const sb_tx0_mux_text[] = {
 586         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 587 };
 588
 589 static const char * const sb_tx1_mux_text[] = {
 590         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 591 };
 592
 593 static const char * const sb_tx2_mux_text[] = {
 594         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 595 };
 596
 597 static const char * const sb_tx3_mux_text[] = {
 598         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 599 };
 600
 601 static const char * const sb_tx4_mux_text[] = {
 602         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 603 };
 604
 605 static const char * const sb_tx5_mux_text[] = {
 606         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 607 };
 608
 609 static const char * const sb_tx6_mux_text[] = {
 610         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 611 };
 612
 613 static const char * const sb_tx7_mux_text[] = {
 614         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 615 };
 616
 617 static const char * const sb_tx8_mux_text[] = {
 618         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 619 };
 620
 621 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 625
 626 static const struct soc_enum cf_dec0_enum =
 627         SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 628
 629 static const struct soc_enum cf_dec1_enum =
 630         SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 631
 632 static const struct soc_enum cf_dec2_enum =
 633         SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 634
 635 static const struct soc_enum cf_dec3_enum =
 636         SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 637
 638 static const struct soc_enum cf_dec4_enum =
 639         SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 640
 641 static const struct soc_enum cf_dec5_enum =
 642         SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 643
 644 static const struct soc_enum cf_dec6_enum =
 645         SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 646
 647 static const struct soc_enum cf_dec7_enum =
 648         SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 649
 650 static const struct soc_enum cf_dec8_enum =
 651         SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 652
 653 static const struct soc_enum cf_int0_1_enum =
 654         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 655
 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
 657                      rx_cf_text);
 658
 659 static const struct soc_enum cf_int1_1_enum =
 660         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 661
 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
 663                      rx_cf_text);
 664
 665 static const struct soc_enum cf_int2_1_enum =
 666         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 667
 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
 669                      rx_cf_text);
 670
 671 static const struct soc_enum cf_int3_1_enum =
 672         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 673
 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
 675                      rx_cf_text);
 676
 677 static const struct soc_enum cf_int4_1_enum =
 678         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 679
 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
 681                      rx_cf_text);
 682
 683 static const struct soc_enum cf_int5_1_enum =
 684         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
 685
 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
 687                      rx_cf_text);
 688
 689 static const struct soc_enum cf_int6_1_enum =
 690         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
 691
 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
 693                      rx_cf_text);
 694
 695 static const struct soc_enum cf_int7_1_enum =
 696         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 697
 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
 699                      rx_cf_text);
 700
 701 static const struct soc_enum cf_int8_1_enum =
 702         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 703
 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
 705                      rx_cf_text);
 706
 707 static const struct soc_enum rx_hph_mode_mux_enum =
 708         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 709                             rx_hph_mode_mux_text);
 710
 711 static const struct soc_enum slim_rx_mux_enum =
 712         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 713
 714 static const struct soc_enum rx_int0_2_mux_chain_enum =
 715         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 716                         rx_int0_7_mix_mux_text);
 717
 718 static const struct soc_enum rx_int1_2_mux_chain_enum =
 719         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 720                         rx_int_mix_mux_text);
 721
 722 static const struct soc_enum rx_int2_2_mux_chain_enum =
 723         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 724                         rx_int_mix_mux_text);
 725
 726 static const struct soc_enum rx_int3_2_mux_chain_enum =
 727         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 728                         rx_int_mix_mux_text);
 729
 730 static const struct soc_enum rx_int4_2_mux_chain_enum =
 731         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 732                         rx_int_mix_mux_text);
 733
 734 static const struct soc_enum rx_int5_2_mux_chain_enum =
 735         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
 736                         rx_int_mix_mux_text);
 737
 738 static const struct soc_enum rx_int6_2_mux_chain_enum =
 739         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
 740                         rx_int_mix_mux_text);
 741
 742 static const struct soc_enum rx_int7_2_mux_chain_enum =
 743         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 744                         rx_int0_7_mix_mux_text);
 745
 746 static const struct soc_enum rx_int8_2_mux_chain_enum =
 747         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 748                         rx_int_mix_mux_text);
 749
 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 751         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 752                         rx_prim_mix_text);
 753
 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 755         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 756                         rx_prim_mix_text);
 757
 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 759         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 760                         rx_prim_mix_text);
 761
 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 763         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 764                         rx_prim_mix_text);
 765
 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 767         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 768                         rx_prim_mix_text);
 769
 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 771         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 772                         rx_prim_mix_text);
 773
 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 775         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 776                         rx_prim_mix_text);
 777
 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 779         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 780                         rx_prim_mix_text);
 781
 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 783         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 784                         rx_prim_mix_text);
 785
 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 787         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 788                         rx_prim_mix_text);
 789
 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 791         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 792                         rx_prim_mix_text);
 793
 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 795         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 796                         rx_prim_mix_text);
 797
 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 799         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 800                         rx_prim_mix_text);
 801
 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 803         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 804                         rx_prim_mix_text);
 805
 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 807         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 808                         rx_prim_mix_text);
 809
 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
 811         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
 812                         rx_prim_mix_text);
 813
 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
 815         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
 816                         rx_prim_mix_text);
 817
 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
 819         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
 820                         rx_prim_mix_text);
 821
 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
 823         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
 824                         rx_prim_mix_text);
 825
 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
 827         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
 828                         rx_prim_mix_text);
 829
 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
 831         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
 832                         rx_prim_mix_text);
 833
 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 835         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 836                         rx_prim_mix_text);
 837
 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 839         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 840                         rx_prim_mix_text);
 841
 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 843         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 844                         rx_prim_mix_text);
 845
 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 847         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 848                         rx_prim_mix_text);
 849
 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 851         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 852                         rx_prim_mix_text);
 853
 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 855         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 856                         rx_prim_mix_text);
 857
 858 static const struct soc_enum rx_int0_dem_inp_mux_enum =
 859         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
 860                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 861                         rx_int_dem_inp_mux_text);
 862
 863 static const struct soc_enum rx_int1_dem_inp_mux_enum =
 864         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
 865                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 866                         rx_int_dem_inp_mux_text);
 867
 868 static const struct soc_enum rx_int2_dem_inp_mux_enum =
 869         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
 870                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 871                         rx_int_dem_inp_mux_text);
 872
 873 static const struct soc_enum rx_int0_interp_mux_enum =
 874         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
 875                         rx_int0_interp_mux_text);
 876
 877 static const struct soc_enum rx_int1_interp_mux_enum =
 878         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
 879                         rx_int1_interp_mux_text);
 880
 881 static const struct soc_enum rx_int2_interp_mux_enum =
 882         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
 883                         rx_int2_interp_mux_text);
 884
 885 static const struct soc_enum rx_int3_interp_mux_enum =
 886         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
 887                         rx_int3_interp_mux_text);
 888
 889 static const struct soc_enum rx_int4_interp_mux_enum =
 890         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
 891                         rx_int4_interp_mux_text);
 892
 893 static const struct soc_enum rx_int5_interp_mux_enum =
 894         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
 895                         rx_int5_interp_mux_text);
 896
 897 static const struct soc_enum rx_int6_interp_mux_enum =
 898         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
 899                         rx_int6_interp_mux_text);
 900
 901 static const struct soc_enum rx_int7_interp_mux_enum =
 902         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
 903                         rx_int7_interp_mux_text);
 904
 905 static const struct soc_enum rx_int8_interp_mux_enum =
 906         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
 907                         rx_int8_interp_mux_text);
 908
 909 static const struct soc_enum tx_adc_mux0_chain_enum =
 910         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
 911                         adc_mux_text);
 912
 913 static const struct soc_enum tx_adc_mux1_chain_enum =
 914         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
 915                         adc_mux_text);
 916
 917 static const struct soc_enum tx_adc_mux2_chain_enum =
 918         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
 919                         adc_mux_text);
 920
 921 static const struct soc_enum tx_adc_mux3_chain_enum =
 922         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
 923                         adc_mux_text);
 924
 925 static const struct soc_enum tx_adc_mux4_chain_enum =
 926         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
 927                         adc_mux_text);
 928
 929 static const struct soc_enum tx_adc_mux5_chain_enum =
 930         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
 931                         adc_mux_text);
 932
 933 static const struct soc_enum tx_adc_mux6_chain_enum =
 934         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
 935                         adc_mux_text);
 936
 937 static const struct soc_enum tx_adc_mux7_chain_enum =
 938         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
 939                         adc_mux_text);
 940
 941 static const struct soc_enum tx_adc_mux8_chain_enum =
 942         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
 943                         adc_mux_text);
 944
 945 static const struct soc_enum tx_dmic_mux0_enum =
 946         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
 947                         dmic_mux_text);
 948
 949 static const struct soc_enum tx_dmic_mux1_enum =
 950         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
 951                         dmic_mux_text);
 952
 953 static const struct soc_enum tx_dmic_mux2_enum =
 954         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
 955                         dmic_mux_text);
 956
 957 static const struct soc_enum tx_dmic_mux3_enum =
 958         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
 959                         dmic_mux_text);
 960
 961 static const struct soc_enum tx_dmic_mux4_enum =
 962         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
 963                         dmic_mux_alt_text);
 964
 965 static const struct soc_enum tx_dmic_mux5_enum =
 966         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
 967                         dmic_mux_alt_text);
 968
 969 static const struct soc_enum tx_dmic_mux6_enum =
 970         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
 971                         dmic_mux_alt_text);
 972
 973 static const struct soc_enum tx_dmic_mux7_enum =
 974         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
 975                         dmic_mux_alt_text);
 976
 977 static const struct soc_enum tx_dmic_mux8_enum =
 978         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
 979                         dmic_mux_alt_text);
 980
 981 static const struct soc_enum tx_amic_mux0_enum =
 982         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
 983                         amic_mux_text);
 984
 985 static const struct soc_enum tx_amic_mux1_enum =
 986         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
 987                         amic_mux_text);
 988
 989 static const struct soc_enum tx_amic_mux2_enum =
 990         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
 991                         amic_mux_text);
 992
 993 static const struct soc_enum tx_amic_mux3_enum =
 994         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
 995                         amic_mux_text);
 996
 997 static const struct soc_enum tx_amic_mux4_enum =
 998         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
 999                         amic_mux_text);
1000
1001 static const struct soc_enum tx_amic_mux5_enum =
1002         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
1003                         amic_mux_text);
1004
1005 static const struct soc_enum tx_amic_mux6_enum =
1006         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
1007                         amic_mux_text);
1008
1009 static const struct soc_enum tx_amic_mux7_enum =
1010         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1011                         amic_mux_text);
1012
1013 static const struct soc_enum tx_amic_mux8_enum =
1014         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1015                         amic_mux_text);
1016
1017 static const struct soc_enum sb_tx0_mux_enum =
1018         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1019                         sb_tx0_mux_text);
1020
1021 static const struct soc_enum sb_tx1_mux_enum =
1022         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1023                         sb_tx1_mux_text);
1024
1025 static const struct soc_enum sb_tx2_mux_enum =
1026         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1027                         sb_tx2_mux_text);
1028
1029 static const struct soc_enum sb_tx3_mux_enum =
1030         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1031                         sb_tx3_mux_text);
1032
1033 static const struct soc_enum sb_tx4_mux_enum =
1034         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1035                         sb_tx4_mux_text);
1036
1037 static const struct soc_enum sb_tx5_mux_enum =
1038         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1039                         sb_tx5_mux_text);
1040
1041 static const struct soc_enum sb_tx6_mux_enum =
1042         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1043                         sb_tx6_mux_text);
1044
1045 static const struct soc_enum sb_tx7_mux_enum =
1046         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1047                         sb_tx7_mux_text);
1048
1049 static const struct soc_enum sb_tx8_mux_enum =
1050         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1051                         sb_tx8_mux_text);
1052
1053 static const struct snd_kcontrol_new rx_int0_2_mux =
1054         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int1_2_mux =
1057         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int2_2_mux =
1060         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int3_2_mux =
1063         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int4_2_mux =
1066         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int5_2_mux =
1069         SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int6_2_mux =
1072         SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int7_2_mux =
1075         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int8_2_mux =
1078         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1081         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1084         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1087         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1090         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1093         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1096         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1099         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1102         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1105         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1108         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1111         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1114         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1117         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1120         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1123         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1126         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1129         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1132         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1135         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1138         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1141         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1144         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1147         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1150         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1153         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1154
1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1156         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1157
1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1159         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1160
1161 static const struct snd_kcontrol_new rx_int0_interp_mux =
1162         SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int1_interp_mux =
1165         SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int2_interp_mux =
1168         SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int3_interp_mux =
1171         SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int4_interp_mux =
1174         SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int5_interp_mux =
1177         SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new rx_int6_interp_mux =
1180         SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1181
1182 static const struct snd_kcontrol_new rx_int7_interp_mux =
1183         SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1184
1185 static const struct snd_kcontrol_new rx_int8_interp_mux =
1186         SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux0 =
1189         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux1 =
1192         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux2 =
1195         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux3 =
1198         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux4 =
1201         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux5 =
1204         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1205
1206 static const struct snd_kcontrol_new tx_dmic_mux6 =
1207         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1208
1209 static const struct snd_kcontrol_new tx_dmic_mux7 =
1210         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1211
1212 static const struct snd_kcontrol_new tx_dmic_mux8 =
1213         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux0 =
1216         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux1 =
1219         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux2 =
1222         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux3 =
1225         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux4 =
1228         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux5 =
1231         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1232
1233 static const struct snd_kcontrol_new tx_amic_mux6 =
1234         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1235
1236 static const struct snd_kcontrol_new tx_amic_mux7 =
1237         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1238
1239 static const struct snd_kcontrol_new tx_amic_mux8 =
1240         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx0_mux =
1243         SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx1_mux =
1246         SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx2_mux =
1249         SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx3_mux =
1252         SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx4_mux =
1255         SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx5_mux =
1258         SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1259
1260 static const struct snd_kcontrol_new sb_tx6_mux =
1261         SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1262
1263 static const struct snd_kcontrol_new sb_tx7_mux =
1264         SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1265
1266 static const struct snd_kcontrol_new sb_tx8_mux =
1267         SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1268
1269 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1270                            struct snd_ctl_elem_value *ucontrol)
1271 {
1272         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1273         struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1274
1275         ucontrol->value.enumerated.item[0] = wcd->rx_port_value;
1276
1277         return 0;
1278 }
1279
1280 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1281                            struct snd_ctl_elem_value *ucontrol)
1282 {
1283         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1284         struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1285         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1286         struct snd_soc_dapm_update *update = NULL;
1287         u32 port_id = w->shift;
1288
1289         wcd->rx_port_value = ucontrol->value.enumerated.item[0];
1290
1291         switch (wcd->rx_port_value) {
1292         case 0:
1293                 list_del_init(&wcd->rx_chs[port_id].list);
1294                 break;
1295         case 1:
1296                 list_add_tail(&wcd->rx_chs[port_id].list,
1297                               &wcd->dai[AIF1_PB].slim_ch_list);
1298                 break;
1299         case 2:
1300                 list_add_tail(&wcd->rx_chs[port_id].list,
1301                               &wcd->dai[AIF2_PB].slim_ch_list);
1302                 break;
1303         case 3:
1304                 list_add_tail(&wcd->rx_chs[port_id].list,
1305                               &wcd->dai[AIF3_PB].slim_ch_list);
1306                 break;
1307         case 4:
1308                 list_add_tail(&wcd->rx_chs[port_id].list,
1309                               &wcd->dai[AIF4_PB].slim_ch_list);
1310                 break;
1311         default:
1312                 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value);
1313                 goto err;
1314         }
1315
1316         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value,
1317                                       e, update);
1318
1319         return 0;
1320 err:
1321         return -EINVAL;
1322 }
1323
1324 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1325                              struct snd_ctl_elem_value *ucontrol)
1326 {
1327
1328         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1329         struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1330
1331         ucontrol->value.integer.value[0] = wcd->tx_port_value;
1332
1333         return 0;
1334 }
1335
1336 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1337                              struct snd_ctl_elem_value *ucontrol)
1338 {
1339
1340         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1341         struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1342         struct snd_soc_dapm_update *update = NULL;
1343         struct soc_mixer_control *mixer =
1344                         (struct soc_mixer_control *)kc->private_value;
1345         int enable = ucontrol->value.integer.value[0];
1346         int dai_id = widget->shift;
1347         int port_id = mixer->shift;
1348
1349         switch (dai_id) {
1350         case AIF1_CAP:
1351         case AIF2_CAP:
1352         case AIF3_CAP:
1353                 /* only add to the list if value not set */
1354                 if (enable && !(wcd->tx_port_value & BIT(port_id))) {
1355                         wcd->tx_port_value |= BIT(port_id);
1356                         list_add_tail(&wcd->tx_chs[port_id].list,
1357                                         &wcd->dai[dai_id].slim_ch_list);
1358                 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) {
1359                         wcd->tx_port_value &= ~BIT(port_id);
1360                         list_del_init(&wcd->tx_chs[port_id].list);
1361                 }
1362                 break;
1363         default:
1364                 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1365                 return -EINVAL;
1366         }
1367
1368         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1369
1370         return 0;
1371 }
1372
1373 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1374         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1375                           slim_rx_mux_get, slim_rx_mux_put),
1376         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1377                           slim_rx_mux_get, slim_rx_mux_put),
1378         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1379                           slim_rx_mux_get, slim_rx_mux_put),
1380         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1381                           slim_rx_mux_get, slim_rx_mux_put),
1382         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1383                           slim_rx_mux_get, slim_rx_mux_put),
1384         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1385                           slim_rx_mux_get, slim_rx_mux_put),
1386         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1387                           slim_rx_mux_get, slim_rx_mux_put),
1388         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1389                           slim_rx_mux_get, slim_rx_mux_put),
1390 };
1391
1392 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1393         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1394                         slim_tx_mixer_get, slim_tx_mixer_put),
1395         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1396                         slim_tx_mixer_get, slim_tx_mixer_put),
1397         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1398                         slim_tx_mixer_get, slim_tx_mixer_put),
1399         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1400                         slim_tx_mixer_get, slim_tx_mixer_put),
1401         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1402                         slim_tx_mixer_get, slim_tx_mixer_put),
1403         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1404                         slim_tx_mixer_get, slim_tx_mixer_put),
1405         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1406                         slim_tx_mixer_get, slim_tx_mixer_put),
1407         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1408                         slim_tx_mixer_get, slim_tx_mixer_put),
1409         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1410                         slim_tx_mixer_get, slim_tx_mixer_put),
1411         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1412                         slim_tx_mixer_get, slim_tx_mixer_put),
1413         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1414                         slim_tx_mixer_get, slim_tx_mixer_put),
1415         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1416                         slim_tx_mixer_get, slim_tx_mixer_put),
1417         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1418                         slim_tx_mixer_get, slim_tx_mixer_put),
1419 };
1420
1421 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1422         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1423                         slim_tx_mixer_get, slim_tx_mixer_put),
1424         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1425                         slim_tx_mixer_get, slim_tx_mixer_put),
1426         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1427                         slim_tx_mixer_get, slim_tx_mixer_put),
1428         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1429                         slim_tx_mixer_get, slim_tx_mixer_put),
1430         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1431                         slim_tx_mixer_get, slim_tx_mixer_put),
1432         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1433                         slim_tx_mixer_get, slim_tx_mixer_put),
1434         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1435                         slim_tx_mixer_get, slim_tx_mixer_put),
1436         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1437                         slim_tx_mixer_get, slim_tx_mixer_put),
1438         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1439                         slim_tx_mixer_get, slim_tx_mixer_put),
1440         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1441                         slim_tx_mixer_get, slim_tx_mixer_put),
1442         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1443                         slim_tx_mixer_get, slim_tx_mixer_put),
1444         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1445                         slim_tx_mixer_get, slim_tx_mixer_put),
1446         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1447                         slim_tx_mixer_get, slim_tx_mixer_put),
1448 };
1449
1450 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1451         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1452                         slim_tx_mixer_get, slim_tx_mixer_put),
1453         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1454                         slim_tx_mixer_get, slim_tx_mixer_put),
1455         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1456                         slim_tx_mixer_get, slim_tx_mixer_put),
1457         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1458                         slim_tx_mixer_get, slim_tx_mixer_put),
1459         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1460                         slim_tx_mixer_get, slim_tx_mixer_put),
1461         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1462                         slim_tx_mixer_get, slim_tx_mixer_put),
1463         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1464                         slim_tx_mixer_get, slim_tx_mixer_put),
1465         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1466                         slim_tx_mixer_get, slim_tx_mixer_put),
1467         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1468                         slim_tx_mixer_get, slim_tx_mixer_put),
1469 };
1470
1471 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1472                                 struct snd_ctl_elem_value *ucontrol)
1473 {
1474         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1475         struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1476         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1477         unsigned int val, reg, sel;
1478
1479         val = ucontrol->value.enumerated.item[0];
1480
1481         switch (e->reg) {
1482         case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1483                 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1484                 break;
1485         case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1486                 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1487                 break;
1488         case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1489                 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1490                 break;
1491         case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1492                 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1493                 break;
1494         case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1495                 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1496                 break;
1497         case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1498                 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1499                 break;
1500         case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1501                 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1502                 break;
1503         case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1504                 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1505                 break;
1506         case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1507                 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1508                 break;
1509         default:
1510                 return -EINVAL;
1511         }
1512
1513         /* AMIC: 0, DMIC: 1 */
1514         sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1515         snd_soc_component_update_bits(component, reg,
1516                                       WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1517                                       sel);
1518
1519         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1520 }
1521
1522 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1523                                  struct snd_ctl_elem_value *ucontrol)
1524 {
1525         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1526         struct snd_soc_component *component;
1527         int reg, val;
1528
1529         component = snd_soc_dapm_kcontrol_component(kc);
1530         val = ucontrol->value.enumerated.item[0];
1531
1532         if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1533                 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1534         else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1535                 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1536         else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1537                 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1538         else
1539                 return -EINVAL;
1540
1541         /* Set Look Ahead Delay */
1542         snd_soc_component_update_bits(component, reg,
1543                                 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1544                                 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1545         /* Set DEM INP Select */
1546         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1547 }
1548
1549 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1550         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1551                           snd_soc_dapm_get_enum_double,
1552                           wcd9335_int_dem_inp_mux_put);
1553
1554 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1555         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1556                           snd_soc_dapm_get_enum_double,
1557                           wcd9335_int_dem_inp_mux_put);
1558
1559 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1560         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1561                           snd_soc_dapm_get_enum_double,
1562                           wcd9335_int_dem_inp_mux_put);
1563
1564 static const struct snd_kcontrol_new tx_adc_mux0 =
1565         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1566                           snd_soc_dapm_get_enum_double,
1567                           wcd9335_put_dec_enum);
1568
1569 static const struct snd_kcontrol_new tx_adc_mux1 =
1570         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1571                           snd_soc_dapm_get_enum_double,
1572                           wcd9335_put_dec_enum);
1573
1574 static const struct snd_kcontrol_new tx_adc_mux2 =
1575         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1576                           snd_soc_dapm_get_enum_double,
1577                           wcd9335_put_dec_enum);
1578
1579 static const struct snd_kcontrol_new tx_adc_mux3 =
1580         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1581                           snd_soc_dapm_get_enum_double,
1582                           wcd9335_put_dec_enum);
1583
1584 static const struct snd_kcontrol_new tx_adc_mux4 =
1585         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1586                           snd_soc_dapm_get_enum_double,
1587                           wcd9335_put_dec_enum);
1588
1589 static const struct snd_kcontrol_new tx_adc_mux5 =
1590         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1591                           snd_soc_dapm_get_enum_double,
1592                           wcd9335_put_dec_enum);
1593
1594 static const struct snd_kcontrol_new tx_adc_mux6 =
1595         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1596                           snd_soc_dapm_get_enum_double,
1597                           wcd9335_put_dec_enum);
1598
1599 static const struct snd_kcontrol_new tx_adc_mux7 =
1600         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1601                           snd_soc_dapm_get_enum_double,
1602                           wcd9335_put_dec_enum);
1603
1604 static const struct snd_kcontrol_new tx_adc_mux8 =
1605         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1606                           snd_soc_dapm_get_enum_double,
1607                           wcd9335_put_dec_enum);
1608
1609 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1610                                              int rate_val,
1611                                              u32 rate)
1612 {
1613         struct snd_soc_component *component = dai->component;
1614         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1615         struct wcd9335_slim_ch *ch;
1616         int val, j;
1617
1618         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1619                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1620                         val = snd_soc_component_read32(component,
1621                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1622                                         WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1623
1624                         if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1625                                 snd_soc_component_update_bits(component,
1626                                                 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1627                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1628                                                 rate_val);
1629                 }
1630         }
1631
1632         return 0;
1633 }
1634
1635 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1636                                               u8 rate_val,
1637                                               u32 rate)
1638 {
1639         struct snd_soc_component *comp = dai->component;
1640         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1641         struct wcd9335_slim_ch *ch;
1642         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1643         int inp, j;
1644
1645         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1646                 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1647                 /*
1648                  * Loop through all interpolator MUX inputs and find out
1649                  * to which interpolator input, the slim rx port
1650                  * is connected
1651                  */
1652                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1653                         cfg0 = snd_soc_component_read32(comp,
1654                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1655                         cfg1 = snd_soc_component_read32(comp,
1656                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1657
1658                         inp0_sel = cfg0 &
1659                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1660                         inp1_sel = (cfg0 >> 4) &
1661                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1662                         inp2_sel = (cfg1 >> 4) &
1663                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1664
1665                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1666                             (inp2_sel == inp)) {
1667                                 /* rate is in Hz */
1668                                 if ((j == 0) && (rate == 44100))
1669                                         dev_info(wcd->dev,
1670                                                 "Cannot set 44.1KHz on INT0\n");
1671                                 else
1672                                         snd_soc_component_update_bits(comp,
1673                                                 WCD9335_CDC_RX_PATH_CTL(j),
1674                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1675                                                 rate_val);
1676                         }
1677                 }
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1684 {
1685         int i;
1686
1687         /* set mixing path rate */
1688         for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1689                 if (rate == int_mix_rate_val[i].rate) {
1690                         wcd9335_set_mix_interpolator_rate(dai,
1691                                         int_mix_rate_val[i].rate_val, rate);
1692                         break;
1693                 }
1694         }
1695
1696         /* set primary path sample rate */
1697         for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1698                 if (rate == int_prim_rate_val[i].rate) {
1699                         wcd9335_set_prim_interpolator_rate(dai,
1700                                         int_prim_rate_val[i].rate_val, rate);
1701                         break;
1702                 }
1703         }
1704
1705         return 0;
1706 }
1707
1708 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1709                                  struct wcd_slim_codec_dai_data *dai_data,
1710                                  int direction)
1711 {
1712         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1713         struct slim_stream_config *cfg = &dai_data->sconfig;
1714         struct wcd9335_slim_ch *ch;
1715         u16 payload = 0;
1716         int ret, i;
1717
1718         cfg->ch_count = 0;
1719         cfg->direction = direction;
1720         cfg->port_mask = 0;
1721
1722         /* Configure slave interface device */
1723         list_for_each_entry(ch, slim_ch_list, list) {
1724                 cfg->ch_count++;
1725                 payload |= 1 << ch->shift;
1726                 cfg->port_mask |= BIT(ch->port);
1727         }
1728
1729         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1730         if (!cfg->chs)
1731                 return -ENOMEM;
1732
1733         i = 0;
1734         list_for_each_entry(ch, slim_ch_list, list) {
1735                 cfg->chs[i++] = ch->ch_num;
1736                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1737                         /* write to interface device */
1738                         ret = regmap_write(wcd->if_regmap,
1739                                 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1740                                 payload);
1741
1742                         if (ret < 0)
1743                                 goto err;
1744
1745                         /* configure the slave port for water mark and enable*/
1746                         ret = regmap_write(wcd->if_regmap,
1747                                         WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1748                                         WCD9335_SLIM_WATER_MARK_VAL);
1749                         if (ret < 0)
1750                                 goto err;
1751                 } else {
1752                         ret = regmap_write(wcd->if_regmap,
1753                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1754                                 payload & 0x00FF);
1755                         if (ret < 0)
1756                                 goto err;
1757
1758                         /* ports 8,9 */
1759                         ret = regmap_write(wcd->if_regmap,
1760                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1761                                 (payload & 0xFF00)>>8);
1762                         if (ret < 0)
1763                                 goto err;
1764
1765                         /* configure the slave port for water mark and enable*/
1766                         ret = regmap_write(wcd->if_regmap,
1767                                         WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1768                                         WCD9335_SLIM_WATER_MARK_VAL);
1769
1770                         if (ret < 0)
1771                                 goto err;
1772                 }
1773         }
1774
1775         dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1776
1777         return 0;
1778
1779 err:
1780         dev_err(wcd->dev, "Error Setting slim hw params\n");
1781         kfree(cfg->chs);
1782         cfg->chs = NULL;
1783
1784         return ret;
1785 }
1786
1787 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1788                                       u8 rate_val, u32 rate)
1789 {
1790         struct snd_soc_component *comp = dai->component;
1791         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1792         u8 shift = 0, shift_val = 0, tx_mux_sel;
1793         struct wcd9335_slim_ch *ch;
1794         int tx_port, tx_port_reg;
1795         int decimator = -1;
1796
1797         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1798                 tx_port = ch->port;
1799                 if ((tx_port == 12) || (tx_port >= 14)) {
1800                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1801                                 tx_port, dai->id);
1802                         return -EINVAL;
1803                 }
1804                 /* Find the SB TX MUX input - which decimator is connected */
1805                 if (tx_port < 4) {
1806                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1807                         shift = (tx_port << 1);
1808                         shift_val = 0x03;
1809                 } else if ((tx_port >= 4) && (tx_port < 8)) {
1810                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1811                         shift = ((tx_port - 4) << 1);
1812                         shift_val = 0x03;
1813                 } else if ((tx_port >= 8) && (tx_port < 11)) {
1814                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1815                         shift = ((tx_port - 8) << 1);
1816                         shift_val = 0x03;
1817                 } else if (tx_port == 11) {
1818                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1819                         shift = 0;
1820                         shift_val = 0x0F;
1821                 } else if (tx_port == 13) {
1822                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1823                         shift = 4;
1824                         shift_val = 0x03;
1825                 } else {
1826                         return -EINVAL;
1827                 }
1828
1829                 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
1830                                                       (shift_val << shift);
1831
1832                 tx_mux_sel = tx_mux_sel >> shift;
1833                 if (tx_port <= 8) {
1834                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1835                                 decimator = tx_port;
1836                 } else if (tx_port <= 10) {
1837                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1838                                 decimator = ((tx_port == 9) ? 7 : 6);
1839                 } else if (tx_port == 11) {
1840                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1841                                 decimator = tx_mux_sel - 1;
1842                 } else if (tx_port == 13) {
1843                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1844                                 decimator = 5;
1845                 }
1846
1847                 if (decimator >= 0) {
1848                         snd_soc_component_update_bits(comp,
1849                                         WCD9335_CDC_TX_PATH_CTL(decimator),
1850                                         WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1851                                         rate_val);
1852                 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1853                         /* Check if the TX Mux input is RX MIX TXn */
1854                         dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1855                                 tx_port, tx_port);
1856                 } else {
1857                         dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1858                                 decimator);
1859                         return -EINVAL;
1860                 }
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1867                            struct snd_pcm_hw_params *params,
1868                            struct snd_soc_dai *dai)
1869 {
1870         struct wcd9335_codec *wcd;
1871         int ret, tx_fs_rate = 0;
1872
1873         wcd = snd_soc_component_get_drvdata(dai->component);
1874
1875         switch (substream->stream) {
1876         case SNDRV_PCM_STREAM_PLAYBACK:
1877                 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1878                 if (ret) {
1879                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1880                                 params_rate(params));
1881                         return ret;
1882                 }
1883                 switch (params_width(params)) {
1884                 case 16 ... 24:
1885                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1886                         break;
1887                 default:
1888                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1889                                 __func__, params_width(params));
1890                         return -EINVAL;
1891                 }
1892                 break;
1893
1894         case SNDRV_PCM_STREAM_CAPTURE:
1895                 switch (params_rate(params)) {
1896                 case 8000:
1897                         tx_fs_rate = 0;
1898                         break;
1899                 case 16000:
1900                         tx_fs_rate = 1;
1901                         break;
1902                 case 32000:
1903                         tx_fs_rate = 3;
1904                         break;
1905                 case 48000:
1906                         tx_fs_rate = 4;
1907                         break;
1908                 case 96000:
1909                         tx_fs_rate = 5;
1910                         break;
1911                 case 192000:
1912                         tx_fs_rate = 6;
1913                         break;
1914                 case 384000:
1915                         tx_fs_rate = 7;
1916                         break;
1917                 default:
1918                         dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1919                                 __func__, params_rate(params));
1920                         return -EINVAL;
1921
1922                 };
1923
1924                 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1925                                                 params_rate(params));
1926                 if (ret < 0) {
1927                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1928                         return ret;
1929                 }
1930                 switch (params_width(params)) {
1931                 case 16 ... 32:
1932                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1933                         break;
1934                 default:
1935                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1936                                 __func__, params_width(params));
1937                         return -EINVAL;
1938                 };
1939                 break;
1940         default:
1941                 dev_err(wcd->dev, "Invalid stream type %d\n",
1942                         substream->stream);
1943                 return -EINVAL;
1944         };
1945
1946         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1947         wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1948
1949         return 0;
1950 }
1951
1952 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1953                            struct snd_soc_dai *dai)
1954 {
1955         struct wcd_slim_codec_dai_data *dai_data;
1956         struct wcd9335_codec *wcd;
1957         struct slim_stream_config *cfg;
1958
1959         wcd = snd_soc_component_get_drvdata(dai->component);
1960
1961         dai_data = &wcd->dai[dai->id];
1962
1963         switch (cmd) {
1964         case SNDRV_PCM_TRIGGER_START:
1965         case SNDRV_PCM_TRIGGER_RESUME:
1966         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967                 cfg = &dai_data->sconfig;
1968                 slim_stream_prepare(dai_data->sruntime, cfg);
1969                 slim_stream_enable(dai_data->sruntime);
1970                 break;
1971         case SNDRV_PCM_TRIGGER_STOP:
1972         case SNDRV_PCM_TRIGGER_SUSPEND:
1973         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1974                 slim_stream_unprepare(dai_data->sruntime);
1975                 slim_stream_disable(dai_data->sruntime);
1976                 break;
1977         default:
1978                 break;
1979         }
1980
1981         return 0;
1982 }
1983
1984 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1985                                    unsigned int tx_num, unsigned int *tx_slot,
1986                                    unsigned int rx_num, unsigned int *rx_slot)
1987 {
1988         struct wcd9335_codec *wcd;
1989         int i;
1990
1991         wcd = snd_soc_component_get_drvdata(dai->component);
1992
1993         if (!tx_slot || !rx_slot) {
1994                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1995                         tx_slot, rx_slot);
1996                 return -EINVAL;
1997         }
1998
1999         wcd->num_rx_port = rx_num;
2000         for (i = 0; i < rx_num; i++) {
2001                 wcd->rx_chs[i].ch_num = rx_slot[i];
2002                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2003         }
2004
2005         wcd->num_tx_port = tx_num;
2006         for (i = 0; i < tx_num; i++) {
2007                 wcd->tx_chs[i].ch_num = tx_slot[i];
2008                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2009         }
2010
2011         return 0;
2012 }
2013
2014 static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
2015                                    unsigned int *tx_num, unsigned int *tx_slot,
2016                                    unsigned int *rx_num, unsigned int *rx_slot)
2017 {
2018         struct wcd9335_slim_ch *ch;
2019         struct wcd9335_codec *wcd;
2020         int i = 0;
2021
2022         wcd = snd_soc_component_get_drvdata(dai->component);
2023
2024         switch (dai->id) {
2025         case AIF1_PB:
2026         case AIF2_PB:
2027         case AIF3_PB:
2028         case AIF4_PB:
2029                 if (!rx_slot || !rx_num) {
2030                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2031                                 rx_slot, rx_num);
2032                         return -EINVAL;
2033                 }
2034
2035                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2036                         rx_slot[i++] = ch->ch_num;
2037
2038                 *rx_num = i;
2039                 break;
2040         case AIF1_CAP:
2041         case AIF2_CAP:
2042         case AIF3_CAP:
2043                 if (!tx_slot || !tx_num) {
2044                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2045                                 tx_slot, tx_num);
2046                         return -EINVAL;
2047                 }
2048                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2049                         tx_slot[i++] = ch->ch_num;
2050
2051                 *tx_num = i;
2052                 break;
2053         default:
2054                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2055                 break;
2056         }
2057
2058         return 0;
2059 }
2060
2061 static struct snd_soc_dai_ops wcd9335_dai_ops = {
2062         .hw_params = wcd9335_hw_params,
2063         .trigger = wcd9335_trigger,
2064         .set_channel_map = wcd9335_set_channel_map,
2065         .get_channel_map = wcd9335_get_channel_map,
2066 };
2067
2068 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2069         [0] = {
2070                 .name = "wcd9335_rx1",
2071                 .id = AIF1_PB,
2072                 .playback = {
2073                         .stream_name = "AIF1 Playback",
2074                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
2075                         .formats = WCD9335_FORMATS_S16_S24_LE,
2076                         .rate_max = 192000,
2077                         .rate_min = 8000,
2078                         .channels_min = 1,
2079                         .channels_max = 2,
2080                 },
2081                 .ops = &wcd9335_dai_ops,
2082         },
2083         [1] = {
2084                 .name = "wcd9335_tx1",
2085                 .id = AIF1_CAP,
2086                 .capture = {
2087                         .stream_name = "AIF1 Capture",
2088                         .rates = WCD9335_RATES_MASK,
2089                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2090                         .rate_min = 8000,
2091                         .rate_max = 192000,
2092                         .channels_min = 1,
2093                         .channels_max = 4,
2094                 },
2095                 .ops = &wcd9335_dai_ops,
2096         },
2097         [2] = {
2098                 .name = "wcd9335_rx2",
2099                 .id = AIF2_PB,
2100                 .playback = {
2101                         .stream_name = "AIF2 Playback",
2102                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
2103                         .formats = WCD9335_FORMATS_S16_S24_LE,
2104                         .rate_min = 8000,
2105                         .rate_max = 192000,
2106                         .channels_min = 1,
2107                         .channels_max = 2,
2108                 },
2109                 .ops = &wcd9335_dai_ops,
2110         },
2111         [3] = {
2112                 .name = "wcd9335_tx2",
2113                 .id = AIF2_CAP,
2114                 .capture = {
2115                         .stream_name = "AIF2 Capture",
2116                         .rates = WCD9335_RATES_MASK,
2117                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2118                         .rate_min = 8000,
2119                         .rate_max = 192000,
2120                         .channels_min = 1,
2121                         .channels_max = 4,
2122                 },
2123                 .ops = &wcd9335_dai_ops,
2124         },
2125         [4] = {
2126                 .name = "wcd9335_rx3",
2127                 .id = AIF3_PB,
2128                 .playback = {
2129                         .stream_name = "AIF3 Playback",
2130                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
2131                         .formats = WCD9335_FORMATS_S16_S24_LE,
2132                         .rate_min = 8000,
2133                         .rate_max = 192000,
2134                         .channels_min = 1,
2135                         .channels_max = 2,
2136                 },
2137                 .ops = &wcd9335_dai_ops,
2138         },
2139         [5] = {
2140                 .name = "wcd9335_tx3",
2141                 .id = AIF3_CAP,
2142                 .capture = {
2143                         .stream_name = "AIF3 Capture",
2144                         .rates = WCD9335_RATES_MASK,
2145                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2146                         .rate_min = 8000,
2147                         .rate_max = 192000,
2148                         .channels_min = 1,
2149                         .channels_max = 4,
2150                 },
2151                 .ops = &wcd9335_dai_ops,
2152         },
2153         [6] = {
2154                 .name = "wcd9335_rx4",
2155                 .id = AIF4_PB,
2156                 .playback = {
2157                         .stream_name = "AIF4 Playback",
2158                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK,
2159                         .formats = WCD9335_FORMATS_S16_S24_LE,
2160                         .rate_min = 8000,
2161                         .rate_max = 192000,
2162                         .channels_min = 1,
2163                         .channels_max = 2,
2164                 },
2165                 .ops = &wcd9335_dai_ops,
2166         },
2167 };
2168
2169 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2170                                struct snd_ctl_elem_value *ucontrol)
2171 {
2172
2173         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2174         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2175         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2176
2177         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2178         return 0;
2179 }
2180
2181 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2182                                  struct snd_ctl_elem_value *ucontrol)
2183 {
2184         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2185         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2186         int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2187         int value = ucontrol->value.integer.value[0];
2188         int sel;
2189
2190         wcd->comp_enabled[comp] = value;
2191         sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2192                 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2193
2194         /* Any specific register configuration for compander */
2195         switch (comp) {
2196         case COMPANDER_1:
2197                 /* Set Gain Source Select based on compander enable/disable */
2198                 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2199                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2200                 break;
2201         case COMPANDER_2:
2202                 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2203                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2204                 break;
2205         case COMPANDER_5:
2206                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2207                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2208                 break;
2209         case COMPANDER_6:
2210                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2211                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2212                 break;
2213         default:
2214                 break;
2215         };
2216
2217         return 0;
2218 }
2219
2220 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2221                                  struct snd_ctl_elem_value *ucontrol)
2222 {
2223         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2224         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2225
2226         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2227
2228         return 0;
2229 }
2230
2231 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2232                                  struct snd_ctl_elem_value *ucontrol)
2233 {
2234         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2235         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2236         u32 mode_val;
2237
2238         mode_val = ucontrol->value.enumerated.item[0];
2239
2240         if (mode_val == 0) {
2241                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2242                 mode_val = CLS_H_HIFI;
2243         }
2244         wcd->hph_mode = mode_val;
2245
2246         return 0;
2247 }
2248
2249 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2250         /* -84dB min - 40dB max */
2251         SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2252                 0, -84, 40, digital_gain),
2253         SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2254                 0, -84, 40, digital_gain),
2255         SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2256                 0, -84, 40, digital_gain),
2257         SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2258                 0, -84, 40, digital_gain),
2259         SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2260                 0, -84, 40, digital_gain),
2261         SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2262                 0, -84, 40, digital_gain),
2263         SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2264                 0, -84, 40, digital_gain),
2265         SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2266                 0, -84, 40, digital_gain),
2267         SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2268                 0, -84, 40, digital_gain),
2269         SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume",
2270                           WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2271                           0, -84, 40, digital_gain),
2272         SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume",
2273                           WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2274                           0, -84, 40, digital_gain),
2275         SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume",
2276                           WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2277                           0, -84, 40, digital_gain),
2278         SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume",
2279                           WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2280                           0, -84, 40, digital_gain),
2281         SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume",
2282                           WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2283                           0, -84, 40, digital_gain),
2284         SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume",
2285                           WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2286                           0, -84, 40, digital_gain),
2287         SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume",
2288                           WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2289                           0, -84, 40, digital_gain),
2290         SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume",
2291                           WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2292                           0, -84, 40, digital_gain),
2293         SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume",
2294                           WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2295                           0, -84, 40, digital_gain),
2296         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2297         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2298         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2299         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2300         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2301         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2302         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2303         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2304         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2305         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2306         SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2307         SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2308         SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2309         SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2310         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2311         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2312         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2313         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2314         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2315                        wcd9335_get_compander, wcd9335_set_compander),
2316         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2317                        wcd9335_get_compander, wcd9335_set_compander),
2318         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2319                        wcd9335_get_compander, wcd9335_set_compander),
2320         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2321                        wcd9335_get_compander, wcd9335_set_compander),
2322         SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2323                        wcd9335_get_compander, wcd9335_set_compander),
2324         SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2325                        wcd9335_get_compander, wcd9335_set_compander),
2326         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2327                        wcd9335_get_compander, wcd9335_set_compander),
2328         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2329                        wcd9335_get_compander, wcd9335_set_compander),
2330         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2331                        wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2332
2333         /* Gain Controls */
2334         SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2335                 ear_pa_gain),
2336         SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2337                 line_gain),
2338         SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2339                 line_gain),
2340         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2341                         3, 16, 1, line_gain),
2342         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2343                         3, 16, 1, line_gain),
2344         SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2345                         line_gain),
2346         SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2347                         line_gain),
2348
2349         SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2350                         analog_gain),
2351         SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2352                         analog_gain),
2353         SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2354                         analog_gain),
2355         SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2356                         analog_gain),
2357         SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2358                         analog_gain),
2359         SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2360                         analog_gain),
2361
2362         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2363         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2364         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2365         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2366         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2367         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2368         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2369         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2370         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2371 };
2372
2373 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2374         {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2375         {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2376         {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2377         {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2378         {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2379         {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2380         {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2381         {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2382
2383         {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2384         {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2385         {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2386         {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2387         {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2388         {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2389         {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2390         {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2391
2392         {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2393         {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2394         {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2395         {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2396         {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2397         {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2398         {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2399         {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2400
2401         {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2402         {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2403         {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2404         {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2405         {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2406         {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2407         {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2408         {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2409
2410         {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2411         {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2412         {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2413         {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2414         {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2415         {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2416         {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2417         {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2418
2419         WCD9335_INTERPOLATOR_PATH(0),
2420         WCD9335_INTERPOLATOR_PATH(1),
2421         WCD9335_INTERPOLATOR_PATH(2),
2422         WCD9335_INTERPOLATOR_PATH(3),
2423         WCD9335_INTERPOLATOR_PATH(4),
2424         WCD9335_INTERPOLATOR_PATH(5),
2425         WCD9335_INTERPOLATOR_PATH(6),
2426         WCD9335_INTERPOLATOR_PATH(7),
2427         WCD9335_INTERPOLATOR_PATH(8),
2428
2429         /* EAR PA */
2430         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2431         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2432         {"RX INT0 DAC", NULL, "RX_BIAS"},
2433         {"EAR PA", NULL, "RX INT0 DAC"},
2434         {"EAR", NULL, "EAR PA"},
2435
2436         /* HPHL */
2437         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2438         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2439         {"RX INT1 DAC", NULL, "RX_BIAS"},
2440         {"HPHL PA", NULL, "RX INT1 DAC"},
2441         {"HPHL", NULL, "HPHL PA"},
2442
2443         /* HPHR */
2444         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2445         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2446         {"RX INT2 DAC", NULL, "RX_BIAS"},
2447         {"HPHR PA", NULL, "RX INT2 DAC"},
2448         {"HPHR", NULL, "HPHR PA"},
2449
2450         /* LINEOUT1 */
2451         {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2452         {"RX INT3 DAC", NULL, "RX_BIAS"},
2453         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2454         {"LINEOUT1", NULL, "LINEOUT1 PA"},
2455
2456         /* LINEOUT2 */
2457         {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2458         {"RX INT4 DAC", NULL, "RX_BIAS"},
2459         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2460         {"LINEOUT2", NULL, "LINEOUT2 PA"},
2461
2462         /* LINEOUT3 */
2463         {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2464         {"RX INT5 DAC", NULL, "RX_BIAS"},
2465         {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2466         {"LINEOUT3", NULL, "LINEOUT3 PA"},
2467
2468         /* LINEOUT4 */
2469         {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2470         {"RX INT6 DAC", NULL, "RX_BIAS"},
2471         {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2472         {"LINEOUT4", NULL, "LINEOUT4 PA"},
2473
2474         /* SLIMBUS Connections */
2475         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2476         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2477         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2478
2479         /* ADC Mux */
2480         WCD9335_ADC_MUX_PATH(0),
2481         WCD9335_ADC_MUX_PATH(1),
2482         WCD9335_ADC_MUX_PATH(2),
2483         WCD9335_ADC_MUX_PATH(3),
2484         WCD9335_ADC_MUX_PATH(4),
2485         WCD9335_ADC_MUX_PATH(5),
2486         WCD9335_ADC_MUX_PATH(6),
2487         WCD9335_ADC_MUX_PATH(7),
2488         WCD9335_ADC_MUX_PATH(8),
2489
2490         /* ADC Connections */
2491         {"ADC1", NULL, "AMIC1"},
2492         {"ADC2", NULL, "AMIC2"},
2493         {"ADC3", NULL, "AMIC3"},
2494         {"ADC4", NULL, "AMIC4"},
2495         {"ADC5", NULL, "AMIC5"},
2496         {"ADC6", NULL, "AMIC6"},
2497 };
2498
2499 static int wcd9335_micbias_control(struct snd_soc_component *component,
2500                                    int micb_num, int req, bool is_dapm)
2501 {
2502         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2503         int micb_index = micb_num - 1;
2504         u16 micb_reg;
2505
2506         if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2507                 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2508                         micb_index);
2509                 return -EINVAL;
2510         }
2511
2512         switch (micb_num) {
2513         case MIC_BIAS_1:
2514                 micb_reg = WCD9335_ANA_MICB1;
2515                 break;
2516         case MIC_BIAS_2:
2517                 micb_reg = WCD9335_ANA_MICB2;
2518                 break;
2519         case MIC_BIAS_3:
2520                 micb_reg = WCD9335_ANA_MICB3;
2521                 break;
2522         case MIC_BIAS_4:
2523                 micb_reg = WCD9335_ANA_MICB4;
2524                 break;
2525         default:
2526                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2527                         __func__, micb_num);
2528                 return -EINVAL;
2529         }
2530
2531         switch (req) {
2532         case MICB_PULLUP_ENABLE:
2533                 wcd->pullup_ref[micb_index]++;
2534                 if ((wcd->pullup_ref[micb_index] == 1) &&
2535                     (wcd->micb_ref[micb_index] == 0))
2536                         snd_soc_component_update_bits(component, micb_reg,
2537                                                         0xC0, 0x80);
2538                 break;
2539         case MICB_PULLUP_DISABLE:
2540                 wcd->pullup_ref[micb_index]--;
2541                 if ((wcd->pullup_ref[micb_index] == 0) &&
2542                     (wcd->micb_ref[micb_index] == 0))
2543                         snd_soc_component_update_bits(component, micb_reg,
2544                                                         0xC0, 0x00);
2545                 break;
2546         case MICB_ENABLE:
2547                 wcd->micb_ref[micb_index]++;
2548                 if (wcd->micb_ref[micb_index] == 1)
2549                         snd_soc_component_update_bits(component, micb_reg,
2550                                                         0xC0, 0x40);
2551                 break;
2552         case MICB_DISABLE:
2553                 wcd->micb_ref[micb_index]--;
2554                 if ((wcd->micb_ref[micb_index] == 0) &&
2555                     (wcd->pullup_ref[micb_index] > 0))
2556                         snd_soc_component_update_bits(component, micb_reg,
2557                                                         0xC0, 0x80);
2558                 else if ((wcd->micb_ref[micb_index] == 0) &&
2559                          (wcd->pullup_ref[micb_index] == 0)) {
2560                         snd_soc_component_update_bits(component, micb_reg,
2561                                                         0xC0, 0x00);
2562                 }
2563                 break;
2564         };
2565
2566         return 0;
2567 }
2568
2569 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2570                                         int event)
2571 {
2572         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2573         int micb_num;
2574
2575         if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2576                 micb_num = MIC_BIAS_1;
2577         else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2578                 micb_num = MIC_BIAS_2;
2579         else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2580                 micb_num = MIC_BIAS_3;
2581         else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2582                 micb_num = MIC_BIAS_4;
2583         else
2584                 return -EINVAL;
2585
2586         switch (event) {
2587         case SND_SOC_DAPM_PRE_PMU:
2588                 /*
2589                  * MIC BIAS can also be requested by MBHC,
2590                  * so use ref count to handle micbias pullup
2591                  * and enable requests
2592                  */
2593                 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2594                 break;
2595         case SND_SOC_DAPM_POST_PMU:
2596                 /* wait for cnp time */
2597                 usleep_range(1000, 1100);
2598                 break;
2599         case SND_SOC_DAPM_POST_PMD:
2600                 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2601                 break;
2602         };
2603
2604         return 0;
2605 }
2606
2607 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2608                 struct snd_kcontrol *kc, int event)
2609 {
2610         return __wcd9335_codec_enable_micbias(w, event);
2611 }
2612
2613 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2614                                       u16 amic_reg, bool set)
2615 {
2616         u8 mask = 0x20;
2617         u8 val;
2618
2619         if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2620             amic_reg == WCD9335_ANA_AMIC5)
2621                 mask = 0x40;
2622
2623         val = set ? mask : 0x00;
2624
2625         switch (amic_reg) {
2626         case WCD9335_ANA_AMIC1:
2627         case WCD9335_ANA_AMIC2:
2628                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2629                                                 val);
2630                 break;
2631         case WCD9335_ANA_AMIC3:
2632         case WCD9335_ANA_AMIC4:
2633                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2634                                                 val);
2635                 break;
2636         case WCD9335_ANA_AMIC5:
2637         case WCD9335_ANA_AMIC6:
2638                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2639                                                 val);
2640                 break;
2641         default:
2642                 dev_err(comp->dev, "%s: invalid amic: %d\n",
2643                         __func__, amic_reg);
2644                 break;
2645         }
2646 }
2647
2648 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2649                 struct snd_kcontrol *kc, int event)
2650 {
2651         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2652
2653         switch (event) {
2654         case SND_SOC_DAPM_PRE_PMU:
2655                 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2656                 break;
2657         default:
2658                 break;
2659         }
2660
2661         return 0;
2662 }
2663
2664 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2665                                          int adc_mux_n)
2666 {
2667         int mux_sel, reg, mreg;
2668
2669         if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2670             adc_mux_n == WCD9335_INVALID_ADC_MUX)
2671                 return 0;
2672
2673         /* Check whether adc mux input is AMIC or DMIC */
2674         if (adc_mux_n < 4) {
2675                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2676                 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2677                 mux_sel = snd_soc_component_read32(comp, reg) & 0x3;
2678         } else {
2679                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2680                 mreg = reg;
2681                 mux_sel = snd_soc_component_read32(comp, reg) >> 6;
2682         }
2683
2684         if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2685                 return 0;
2686
2687         return snd_soc_component_read32(comp, mreg) & 0x07;
2688 }
2689
2690 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2691                                             int amic)
2692 {
2693         u16 pwr_level_reg = 0;
2694
2695         switch (amic) {
2696         case 1:
2697         case 2:
2698                 pwr_level_reg = WCD9335_ANA_AMIC1;
2699                 break;
2700
2701         case 3:
2702         case 4:
2703                 pwr_level_reg = WCD9335_ANA_AMIC3;
2704                 break;
2705
2706         case 5:
2707         case 6:
2708                 pwr_level_reg = WCD9335_ANA_AMIC5;
2709                 break;
2710         default:
2711                 dev_err(comp->dev, "invalid amic: %d\n", amic);
2712                 break;
2713         }
2714
2715         return pwr_level_reg;
2716 }
2717
2718 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2719         struct snd_kcontrol *kc, int event)
2720 {
2721         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2722         unsigned int decimator;
2723         char *dec_adc_mux_name = NULL;
2724         char *widget_name = NULL;
2725         char *wname;
2726         int ret = 0, amic_n;
2727         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2728         u16 tx_gain_ctl_reg;
2729         char *dec;
2730         u8 hpf_coff_freq;
2731
2732         widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
2733         if (!widget_name)
2734                 return -ENOMEM;
2735
2736         wname = widget_name;
2737         dec_adc_mux_name = strsep(&widget_name, " ");
2738         if (!dec_adc_mux_name) {
2739                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2740                         __func__, w->name);
2741                 ret =  -EINVAL;
2742                 goto out;
2743         }
2744         dec_adc_mux_name = widget_name;
2745
2746         dec = strpbrk(dec_adc_mux_name, "012345678");
2747         if (!dec) {
2748                 dev_err(comp->dev, "%s: decimator index not found\n",
2749                         __func__);
2750                 ret =  -EINVAL;
2751                 goto out;
2752         }
2753
2754         ret = kstrtouint(dec, 10, &decimator);
2755         if (ret < 0) {
2756                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2757                         __func__, wname);
2758                 ret =  -EINVAL;
2759                 goto out;
2760         }
2761
2762         tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2763         hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2764         dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2765         tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2766
2767         switch (event) {
2768         case SND_SOC_DAPM_PRE_PMU:
2769                 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2770                 if (amic_n)
2771                         pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2772                                                                        amic_n);
2773
2774                 if (pwr_level_reg) {
2775                         switch ((snd_soc_component_read32(comp, pwr_level_reg) &
2776                                               WCD9335_AMIC_PWR_LVL_MASK) >>
2777                                               WCD9335_AMIC_PWR_LVL_SHIFT) {
2778                         case WCD9335_AMIC_PWR_LEVEL_LP:
2779                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2780                                                     WCD9335_DEC_PWR_LVL_MASK,
2781                                                     WCD9335_DEC_PWR_LVL_LP);
2782                                 break;
2783
2784                         case WCD9335_AMIC_PWR_LEVEL_HP:
2785                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2786                                                     WCD9335_DEC_PWR_LVL_MASK,
2787                                                     WCD9335_DEC_PWR_LVL_HP);
2788                                 break;
2789                         case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2790                         default:
2791                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2792                                                     WCD9335_DEC_PWR_LVL_MASK,
2793                                                     WCD9335_DEC_PWR_LVL_DF);
2794                                 break;
2795                         }
2796                 }
2797                 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
2798                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2799
2800                 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2801                         snd_soc_component_update_bits(comp, dec_cfg_reg,
2802                                             TX_HPF_CUT_OFF_FREQ_MASK,
2803                                             CF_MIN_3DB_150HZ << 5);
2804                 /* Enable TX PGA Mute */
2805                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2806                                                 0x10, 0x10);
2807                 /* Enable APC */
2808                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2809                 break;
2810         case SND_SOC_DAPM_POST_PMU:
2811                 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2812
2813                 if (decimator == 0) {
2814                         snd_soc_component_write(comp,
2815                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2816                         snd_soc_component_write(comp,
2817                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2818                         snd_soc_component_write(comp,
2819                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2820                         snd_soc_component_write(comp,
2821                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2822                 }
2823
2824                 snd_soc_component_update_bits(comp, hpf_gate_reg,
2825                                                 0x01, 0x01);
2826                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2827                                                 0x10, 0x00);
2828                 snd_soc_component_write(comp, tx_gain_ctl_reg,
2829                               snd_soc_component_read32(comp, tx_gain_ctl_reg));
2830                 break;
2831         case SND_SOC_DAPM_PRE_PMD:
2832                 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
2833                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2834                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2835                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2836                         if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2837                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2838                                                     TX_HPF_CUT_OFF_FREQ_MASK,
2839                                                     hpf_coff_freq << 5);
2840                         }
2841                 break;
2842         case SND_SOC_DAPM_POST_PMD:
2843                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2844                 break;
2845         };
2846 out:
2847         kfree(wname);
2848         return ret;
2849 }
2850
2851 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2852                                  u32 mclk_rate, u32 dmic_clk_rate)
2853 {
2854         u32 div_factor;
2855         u8 dmic_ctl_val;
2856
2857         dev_err(component->dev,
2858                 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
2859                 __func__, mclk_rate, dmic_clk_rate);
2860
2861         /* Default value to return in case of error */
2862         if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2863                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2864         else
2865                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2866
2867         if (dmic_clk_rate == 0) {
2868                 dev_err(component->dev,
2869                         "%s: dmic_sample_rate cannot be 0\n",
2870                         __func__);
2871                 goto done;
2872         }
2873
2874         div_factor = mclk_rate / dmic_clk_rate;
2875         switch (div_factor) {
2876         case 2:
2877                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2878                 break;
2879         case 3:
2880                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2881                 break;
2882         case 4:
2883                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
2884                 break;
2885         case 6:
2886                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
2887                 break;
2888         case 8:
2889                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
2890                 break;
2891         case 16:
2892                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
2893                 break;
2894         default:
2895                 dev_err(component->dev,
2896                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
2897                         __func__, div_factor, mclk_rate, dmic_clk_rate);
2898                 break;
2899         }
2900
2901 done:
2902         return dmic_ctl_val;
2903 }
2904
2905 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2906                 struct snd_kcontrol *kc, int event)
2907 {
2908         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2909         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2910         u8  dmic_clk_en = 0x01;
2911         u16 dmic_clk_reg;
2912         s32 *dmic_clk_cnt;
2913         u8 dmic_rate_val, dmic_rate_shift = 1;
2914         unsigned int dmic;
2915         int ret;
2916         char *wname;
2917
2918         wname = strpbrk(w->name, "012345");
2919         if (!wname) {
2920                 dev_err(comp->dev, "%s: widget not found\n", __func__);
2921                 return -EINVAL;
2922         }
2923
2924         ret = kstrtouint(wname, 10, &dmic);
2925         if (ret < 0) {
2926                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2927                         __func__);
2928                 return -EINVAL;
2929         }
2930
2931         switch (dmic) {
2932         case 0:
2933         case 1:
2934                 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2935                 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2936                 break;
2937         case 2:
2938         case 3:
2939                 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2940                 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2941                 break;
2942         case 4:
2943         case 5:
2944                 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2945                 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2946                 break;
2947         default:
2948                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2949                         __func__);
2950                 return -EINVAL;
2951         };
2952
2953         switch (event) {
2954         case SND_SOC_DAPM_PRE_PMU:
2955                 dmic_rate_val =
2956                         wcd9335_get_dmic_clk_val(comp,
2957                                         wcd->mclk_rate,
2958                                         wcd->dmic_sample_rate);
2959
2960                 (*dmic_clk_cnt)++;
2961                 if (*dmic_clk_cnt == 1) {
2962                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2963                                 0x07 << dmic_rate_shift,
2964                                 dmic_rate_val << dmic_rate_shift);
2965                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2966                                         dmic_clk_en, dmic_clk_en);
2967                 }
2968
2969                 break;
2970         case SND_SOC_DAPM_POST_PMD:
2971                 dmic_rate_val =
2972                         wcd9335_get_dmic_clk_val(comp,
2973                                         wcd->mclk_rate,
2974                                         wcd->mad_dmic_sample_rate);
2975                 (*dmic_clk_cnt)--;
2976                 if (*dmic_clk_cnt  == 0) {
2977                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2978                                         dmic_clk_en, 0);
2979                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2980                                 0x07 << dmic_rate_shift,
2981                                 dmic_rate_val << dmic_rate_shift);
2982                 }
2983                 break;
2984         };
2985
2986         return 0;
2987 }
2988
2989 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2990                                         struct snd_soc_component *component)
2991 {
2992         int port_num = 0;
2993         unsigned short reg = 0;
2994         unsigned int val = 0;
2995         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2996         struct wcd9335_slim_ch *ch;
2997
2998         list_for_each_entry(ch, &dai->slim_ch_list, list) {
2999                 if (ch->port >= WCD9335_RX_START) {
3000                         port_num = ch->port - WCD9335_RX_START;
3001                         reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3002                 } else {
3003                         port_num = ch->port;
3004                         reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3005                 }
3006
3007                 regmap_read(wcd->if_regmap, reg, &val);
3008                 if (!(val & BIT(port_num % 8)))
3009                         regmap_write(wcd->if_regmap, reg,
3010                                         val | BIT(port_num % 8));
3011         }
3012 }
3013
3014 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
3015                                        struct snd_kcontrol *kc,
3016                                        int event)
3017 {
3018         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3019         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
3020         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3021         int ret = 0;
3022
3023         switch (event) {
3024         case SND_SOC_DAPM_POST_PMU:
3025                 wcd9335_codec_enable_int_port(dai, comp);
3026                 break;
3027         case SND_SOC_DAPM_POST_PMD:
3028                 kfree(dai->sconfig.chs);
3029
3030                 break;
3031         }
3032
3033         return ret;
3034 }
3035
3036 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3037                 struct snd_kcontrol *kc, int event)
3038 {
3039         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3040         u16 gain_reg;
3041         int offset_val = 0;
3042         int val = 0;
3043
3044         switch (w->reg) {
3045         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3046                 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
3047                 break;
3048         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3049                 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
3050                 break;
3051         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3052                 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
3053                 break;
3054         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3055                 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3056                 break;
3057         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3058                 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3059                 break;
3060         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3061                 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3062                 break;
3063         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3064                 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3065                 break;
3066         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3067                 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3068                 break;
3069         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3070                 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3071                 break;
3072         default:
3073                 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3074                         __func__, w->name);
3075                 return 0;
3076         };
3077
3078         switch (event) {
3079         case SND_SOC_DAPM_POST_PMU:
3080                 val = snd_soc_component_read32(comp, gain_reg);
3081                 val += offset_val;
3082                 snd_soc_component_write(comp, gain_reg, val);
3083                 break;
3084         case SND_SOC_DAPM_POST_PMD:
3085                 break;
3086         };
3087
3088         return 0;
3089 }
3090
3091 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3092 {
3093         u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3094
3095         switch (reg) {
3096         case WCD9335_CDC_RX0_RX_PATH_CTL:
3097         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3098                 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3099                 *ind = 0;
3100                 break;
3101         case WCD9335_CDC_RX1_RX_PATH_CTL:
3102         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3103                 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3104                 *ind = 1;
3105                 break;
3106         case WCD9335_CDC_RX2_RX_PATH_CTL:
3107         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3108                 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3109                 *ind = 2;
3110                 break;
3111         case WCD9335_CDC_RX3_RX_PATH_CTL:
3112         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3113                 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3114                 *ind = 3;
3115                 break;
3116         case WCD9335_CDC_RX4_RX_PATH_CTL:
3117         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3118                 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3119                 *ind = 4;
3120                 break;
3121         case WCD9335_CDC_RX5_RX_PATH_CTL:
3122         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3123                 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3124                 *ind = 5;
3125                 break;
3126         case WCD9335_CDC_RX6_RX_PATH_CTL:
3127         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3128                 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3129                 *ind = 6;
3130                 break;
3131         case WCD9335_CDC_RX7_RX_PATH_CTL:
3132         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3133                 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3134                 *ind = 7;
3135                 break;
3136         case WCD9335_CDC_RX8_RX_PATH_CTL:
3137         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3138                 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3139                 *ind = 8;
3140                 break;
3141         };
3142
3143         return prim_int_reg;
3144 }
3145
3146 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3147                                     u16 prim_int_reg, int event)
3148 {
3149         u16 hd2_scale_reg;
3150         u16 hd2_enable_reg = 0;
3151
3152         if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3153                 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3154                 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3155         }
3156         if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3157                 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3158                 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3159         }
3160
3161         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3162                 snd_soc_component_update_bits(component, hd2_scale_reg,
3163                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3164                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3165                 snd_soc_component_update_bits(component, hd2_scale_reg,
3166                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3167                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3168                 snd_soc_component_update_bits(component, hd2_enable_reg,
3169                                 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3170                                 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3171         }
3172
3173         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3174                 snd_soc_component_update_bits(component, hd2_enable_reg,
3175                                         WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3176                                         WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3177                 snd_soc_component_update_bits(component, hd2_scale_reg,
3178                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3179                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3180                 snd_soc_component_update_bits(component, hd2_scale_reg,
3181                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3182                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3183         }
3184 }
3185
3186 static int wcd9335_codec_enable_prim_interpolator(
3187                                                 struct snd_soc_component *comp,
3188                                                 u16 reg, int event)
3189 {
3190         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3191         u16 ind = 0;
3192         int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3193
3194         switch (event) {
3195         case SND_SOC_DAPM_PRE_PMU:
3196                 wcd->prim_int_users[ind]++;
3197                 if (wcd->prim_int_users[ind] == 1) {
3198                         snd_soc_component_update_bits(comp, prim_int_reg,
3199                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3200                                         WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3201                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3202                         snd_soc_component_update_bits(comp, prim_int_reg,
3203                                         WCD9335_CDC_RX_CLK_EN_MASK,
3204                                         WCD9335_CDC_RX_CLK_ENABLE);
3205                 }
3206
3207                 if ((reg != prim_int_reg) &&
3208                         ((snd_soc_component_read32(comp, prim_int_reg)) &
3209                          WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3210                         snd_soc_component_update_bits(comp, reg,
3211                                                 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3212                                                 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3213                 break;
3214         case SND_SOC_DAPM_POST_PMD:
3215                 wcd->prim_int_users[ind]--;
3216                 if (wcd->prim_int_users[ind] == 0) {
3217                         snd_soc_component_update_bits(comp, prim_int_reg,
3218                                         WCD9335_CDC_RX_CLK_EN_MASK,
3219                                         WCD9335_CDC_RX_CLK_DISABLE);
3220                         snd_soc_component_update_bits(comp, prim_int_reg,
3221                                         WCD9335_CDC_RX_RESET_MASK,
3222                                         WCD9335_CDC_RX_RESET_ENABLE);
3223                         snd_soc_component_update_bits(comp, prim_int_reg,
3224                                         WCD9335_CDC_RX_RESET_MASK,
3225                                         WCD9335_CDC_RX_RESET_DISABLE);
3226                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3227                 }
3228                 break;
3229         };
3230
3231         return 0;
3232 }
3233
3234 static int wcd9335_config_compander(struct snd_soc_component *component,
3235                                     int interp_n, int event)
3236 {
3237         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3238         int comp;
3239         u16 comp_ctl0_reg, rx_path_cfg0_reg;
3240
3241         /* EAR does not have compander */
3242         if (!interp_n)
3243                 return 0;
3244
3245         comp = interp_n - 1;
3246         if (!wcd->comp_enabled[comp])
3247                 return 0;
3248
3249         comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3250         rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3251
3252         if (SND_SOC_DAPM_EVENT_ON(event)) {
3253                 /* Enable Compander Clock */
3254                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3255                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3256                                         WCD9335_CDC_COMPANDER_CLK_ENABLE);
3257                 /* Reset comander */
3258                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3259                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3260                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3261                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3262                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3263                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3264                 /* Enables DRE in this path */
3265                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3266                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3267                                         WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3268         }
3269
3270         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3271                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3272                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3273                                         WCD9335_CDC_COMPANDER_HALT);
3274                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3275                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3276                                         WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3277
3278                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3279                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3280                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3281                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3282                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3283                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3284                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3285                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3286                                         WCD9335_CDC_COMPANDER_CLK_DISABLE);
3287                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3288                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3289                                         WCD9335_CDC_COMPANDER_NOHALT);
3290         }
3291
3292         return 0;
3293 }
3294
3295 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3296                 struct snd_kcontrol *kc, int event)
3297 {
3298         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3299         u16 gain_reg;
3300         u16 reg;
3301         int val;
3302         int offset_val = 0;
3303
3304         if (!(strcmp(w->name, "RX INT0 INTERP"))) {
3305                 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3306                 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3307         } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
3308                 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3309                 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3310         } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
3311                 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3312                 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3313         } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
3314                 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3315                 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3316         } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
3317                 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3318                 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3319         } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
3320                 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3321                 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3322         } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
3323                 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3324                 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3325         } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
3326                 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3327                 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3328         } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
3329                 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3330                 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3331         } else {
3332                 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3333                         __func__);
3334                 return -EINVAL;
3335         }
3336
3337         switch (event) {
3338         case SND_SOC_DAPM_PRE_PMU:
3339                 /* Reset if needed */
3340                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3341                 break;
3342         case SND_SOC_DAPM_POST_PMU:
3343                 wcd9335_config_compander(comp, w->shift, event);
3344                 val = snd_soc_component_read32(comp, gain_reg);
3345                 val += offset_val;
3346                 snd_soc_component_write(comp, gain_reg, val);
3347                 break;
3348         case SND_SOC_DAPM_POST_PMD:
3349                 wcd9335_config_compander(comp, w->shift, event);
3350                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3351                 break;
3352         };
3353
3354         return 0;
3355 }
3356
3357 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3358                                             u8 gain)
3359 {
3360         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3361         u8 hph_l_en, hph_r_en;
3362         u8 l_val, r_val;
3363         u8 hph_pa_status;
3364         bool is_hphl_pa, is_hphr_pa;
3365
3366         hph_pa_status = snd_soc_component_read32(component, WCD9335_ANA_HPH);
3367         is_hphl_pa = hph_pa_status >> 7;
3368         is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3369
3370         hph_l_en = snd_soc_component_read32(component, WCD9335_HPH_L_EN);
3371         hph_r_en = snd_soc_component_read32(component, WCD9335_HPH_R_EN);
3372
3373         l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3374         r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3375
3376         /*
3377          * Set HPH_L & HPH_R gain source selection to REGISTER
3378          * for better click and pop only if corresponding PAs are
3379          * not enabled. Also cache the values of the HPHL/R
3380          * PA gains to be applied after PAs are enabled
3381          */
3382         if ((l_val != hph_l_en) && !is_hphl_pa) {
3383                 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3384                 wcd->hph_l_gain = hph_l_en & 0x1F;
3385         }
3386
3387         if ((r_val != hph_r_en) && !is_hphr_pa) {
3388                 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3389                 wcd->hph_r_gain = hph_r_en & 0x1F;
3390         }
3391 }
3392
3393 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3394                                           int event)
3395 {
3396         if (SND_SOC_DAPM_EVENT_ON(event)) {
3397                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3398                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3399                                         0x06);
3400                 snd_soc_component_update_bits(comp,
3401                                         WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3402                                         0xF0, 0x40);
3403                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3404                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3405                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3406                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3407                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3408                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3409                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3410                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3411                                 0x0C);
3412                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3413         }
3414
3415         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3416                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3417                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3418                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3419                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3420                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3421                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3422                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3423                                         0x8A);
3424                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3425                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3426                                         0x0A);
3427         }
3428 }
3429
3430 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3431                                       int event)
3432 {
3433         if (SND_SOC_DAPM_EVENT_ON(event)) {
3434                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3435                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3436                                 0x0C);
3437                 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3438                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3439                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3440                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3441                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3442                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3443                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3444                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3445                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3446                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3447                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3448                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3449                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3450                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3451                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3452                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3453                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3454                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3455                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3456                 snd_soc_component_update_bits(comp,
3457                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3458                 snd_soc_component_update_bits(comp,
3459                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3460         }
3461
3462         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3463                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3464                                         0x88);
3465                 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3466                                         0x33);
3467                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3468                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3469                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3470                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3471                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3472                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3473                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3474                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3475                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3476                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3477                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3478                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3479                 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3480                                 WCD9335_HPH_CONST_SEL_L_MASK,
3481                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3482                 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3483                                 WCD9335_HPH_CONST_SEL_L_MASK,
3484                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3485         }
3486 }
3487
3488 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3489                                         int event)
3490 {
3491         if (SND_SOC_DAPM_EVENT_ON(event)) {
3492                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3493                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3494                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3495                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3496                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3497                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3498                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3499                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3500                                 0x0C);
3501                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3502         }
3503
3504         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3505                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3506                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3507                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3508                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3509                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3510                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3511         }
3512 }
3513
3514 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3515                                           int event, int mode)
3516 {
3517         switch (mode) {
3518         case CLS_H_LP:
3519                 wcd9335_codec_hph_lp_config(component, event);
3520                 break;
3521         case CLS_H_LOHIFI:
3522                 wcd9335_codec_hph_lohifi_config(component, event);
3523                 break;
3524         case CLS_H_HIFI:
3525                 wcd9335_codec_hph_hifi_config(component, event);
3526                 break;
3527         }
3528 }
3529
3530 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3531                                         struct snd_kcontrol *kc,
3532                                         int event)
3533 {
3534         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3535         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3536         int hph_mode = wcd->hph_mode;
3537         u8 dem_inp;
3538         int ret = 0;
3539
3540         switch (event) {
3541         case SND_SOC_DAPM_PRE_PMU:
3542                 /* Read DEM INP Select */
3543                 dem_inp = snd_soc_component_read32(comp,
3544                                 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3545                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3546                                 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3547                         dev_err(comp->dev, "Incorrect DEM Input\n");
3548                         return -EINVAL;
3549                 }
3550                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3551                                         WCD_CLSH_STATE_HPHL,
3552                                         ((hph_mode == CLS_H_LOHIFI) ?
3553                                          CLS_H_HIFI : hph_mode));
3554
3555                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3556
3557                 break;
3558         case SND_SOC_DAPM_POST_PMU:
3559                 usleep_range(1000, 1100);
3560                 break;
3561         case SND_SOC_DAPM_PRE_PMD:
3562                 break;
3563         case SND_SOC_DAPM_POST_PMD:
3564                 /* 1000us required as per HW requirement */
3565                 usleep_range(1000, 1100);
3566
3567                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3568                                 WCD_CLSH_STATE_HPHR))
3569                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3570
3571                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3572                                 WCD_CLSH_STATE_HPHL,
3573                                 ((hph_mode == CLS_H_LOHIFI) ?
3574                                  CLS_H_HIFI : hph_mode));
3575                 break;
3576         };
3577
3578         return ret;
3579 }
3580
3581 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3582                                            struct snd_kcontrol *kc, int event)
3583 {
3584         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3585         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3586
3587         switch (event) {
3588         case SND_SOC_DAPM_PRE_PMU:
3589                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3590                                         WCD_CLSH_STATE_LO, CLS_AB);
3591                 break;
3592         case SND_SOC_DAPM_POST_PMD:
3593                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3594                                         WCD_CLSH_STATE_LO, CLS_AB);
3595                 break;
3596         }
3597
3598         return 0;
3599 }
3600
3601 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3602                                        struct snd_kcontrol *kc, int event)
3603 {
3604         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3605         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3606         int ret = 0;
3607
3608         switch (event) {
3609         case SND_SOC_DAPM_PRE_PMU:
3610                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3611                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3612
3613                 break;
3614         case SND_SOC_DAPM_POST_PMD:
3615                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3616                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3617                 break;
3618         };
3619
3620         return ret;
3621 }
3622
3623 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3624                                              int mode, int event)
3625 {
3626         u8 scale_val = 0;
3627
3628         switch (event) {
3629         case SND_SOC_DAPM_POST_PMU:
3630                 switch (mode) {
3631                 case CLS_H_HIFI:
3632                         scale_val = 0x3;
3633                         break;
3634                 case CLS_H_LOHIFI:
3635                         scale_val = 0x1;
3636                         break;
3637                 }
3638                 break;
3639         case SND_SOC_DAPM_PRE_PMD:
3640                 scale_val = 0x6;
3641                 break;
3642         }
3643
3644         if (scale_val)
3645                 snd_soc_component_update_bits(wcd->component,
3646                                         WCD9335_HPH_PA_CTL1,
3647                                         WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3648                                         scale_val << 1);
3649         if (SND_SOC_DAPM_EVENT_ON(event)) {
3650                 if (wcd->comp_enabled[COMPANDER_1] ||
3651                     wcd->comp_enabled[COMPANDER_2]) {
3652                         /* GAIN Source Selection */
3653                         snd_soc_component_update_bits(wcd->component,
3654                                         WCD9335_HPH_L_EN,
3655                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3656                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3657                         snd_soc_component_update_bits(wcd->component,
3658                                         WCD9335_HPH_R_EN,
3659                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3660                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3661                         snd_soc_component_update_bits(wcd->component,
3662                                         WCD9335_HPH_AUTO_CHOP,
3663                                         WCD9335_HPH_AUTO_CHOP_MASK,
3664                                         WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3665                 }
3666                 snd_soc_component_update_bits(wcd->component,
3667                                                 WCD9335_HPH_L_EN,
3668                                                 WCD9335_HPH_PA_GAIN_MASK,
3669                                                 wcd->hph_l_gain);
3670                 snd_soc_component_update_bits(wcd->component,
3671                                                 WCD9335_HPH_R_EN,
3672                                                 WCD9335_HPH_PA_GAIN_MASK,
3673                                                 wcd->hph_r_gain);
3674         }
3675
3676         if (SND_SOC_DAPM_EVENT_OFF(event))
3677                 snd_soc_component_update_bits(wcd->component,
3678                                 WCD9335_HPH_AUTO_CHOP,
3679                                 WCD9335_HPH_AUTO_CHOP_MASK,
3680                                 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3681 }
3682
3683 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3684                                       struct snd_kcontrol *kc,
3685                                       int event)
3686 {
3687         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3688         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3689         int hph_mode = wcd->hph_mode;
3690         u8 dem_inp;
3691         int ret = 0;
3692
3693         switch (event) {
3694         case SND_SOC_DAPM_PRE_PMU:
3695
3696                 /* Read DEM INP Select */
3697                 dem_inp = snd_soc_component_read32(comp,
3698                                 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3699                                 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3700                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3701                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3702                         dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3703                                 hph_mode);
3704                         return -EINVAL;
3705                 }
3706
3707                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3708                              WCD_CLSH_EVENT_PRE_DAC,
3709                              WCD_CLSH_STATE_HPHR,
3710                              ((hph_mode == CLS_H_LOHIFI) ?
3711                                CLS_H_HIFI : hph_mode));
3712
3713                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3714
3715                 break;
3716         case SND_SOC_DAPM_POST_PMD:
3717                 /* 1000us required as per HW requirement */
3718                 usleep_range(1000, 1100);
3719
3720                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3721                                         WCD_CLSH_STATE_HPHL))
3722                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3723
3724                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3725                              WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3726                                                 CLS_H_HIFI : hph_mode));
3727                 break;
3728         };
3729
3730         return ret;
3731 }
3732
3733 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3734                                       struct snd_kcontrol *kc,
3735                                       int event)
3736 {
3737         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3738         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3739         int hph_mode = wcd->hph_mode;
3740         int ret = 0;
3741
3742         switch (event) {
3743         case SND_SOC_DAPM_PRE_PMU:
3744                 break;
3745         case SND_SOC_DAPM_POST_PMU:
3746                 /*
3747                  * 7ms sleep is required after PA is enabled as per
3748                  * HW requirement
3749                  */
3750                 usleep_range(7000, 7100);
3751
3752                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3753                 snd_soc_component_update_bits(comp,
3754                                         WCD9335_CDC_RX1_RX_PATH_CTL,
3755                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3756                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3757
3758                 /* Remove mix path mute if it is enabled */
3759                 if ((snd_soc_component_read32(comp,
3760                                         WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3761                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3762                         snd_soc_component_update_bits(comp,
3763                                             WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3764                                             WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3765                                             WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3766
3767                 break;
3768         case SND_SOC_DAPM_PRE_PMD:
3769                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3770                 break;
3771         case SND_SOC_DAPM_POST_PMD:
3772                 /* 5ms sleep is required after PA is disabled as per
3773                  * HW requirement
3774                  */
3775                 usleep_range(5000, 5500);
3776                 break;
3777         };
3778
3779         return ret;
3780 }
3781
3782 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3783                                          struct snd_kcontrol *kc,
3784                                          int event)
3785 {
3786         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3787         int vol_reg = 0, mix_vol_reg = 0;
3788         int ret = 0;
3789
3790         if (w->reg == WCD9335_ANA_LO_1_2) {
3791                 if (w->shift == 7) {
3792                         vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3793                         mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3794                 } else if (w->shift == 6) {
3795                         vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3796                         mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3797                 }
3798         } else if (w->reg == WCD9335_ANA_LO_3_4) {
3799                 if (w->shift == 7) {
3800                         vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3801                         mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3802                 } else if (w->shift == 6) {
3803                         vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3804                         mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3805                 }
3806         } else {
3807                 dev_err(comp->dev, "Error enabling lineout PA\n");
3808                 return -EINVAL;
3809         }
3810
3811         switch (event) {
3812         case SND_SOC_DAPM_POST_PMU:
3813                 /* 5ms sleep is required after PA is enabled as per
3814                  * HW requirement
3815                  */
3816                 usleep_range(5000, 5500);
3817                 snd_soc_component_update_bits(comp, vol_reg,
3818                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3819                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3820
3821                 /* Remove mix path mute if it is enabled */
3822                 if ((snd_soc_component_read32(comp, mix_vol_reg)) &
3823                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3824                         snd_soc_component_update_bits(comp,  mix_vol_reg,
3825                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3826                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3827                 break;
3828         case SND_SOC_DAPM_POST_PMD:
3829                 /* 5ms sleep is required after PA is disabled as per
3830                  * HW requirement
3831                  */
3832                 usleep_range(5000, 5500);
3833                 break;
3834         };
3835
3836         return ret;
3837 }
3838
3839 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3840 {
3841         snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3842                                         WCD9335_HPH_CONST_SEL_L_MASK,
3843                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3844         snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3845                                         WCD9335_HPH_CONST_SEL_L_MASK,
3846                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3847         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3848                                         WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3849                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3850         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3851                                         WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3852                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3853 }
3854
3855 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3856                 struct snd_kcontrol *kc, int event)
3857 {
3858         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3859         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3860
3861         switch (event) {
3862         case SND_SOC_DAPM_PRE_PMU:
3863                 wcd->rx_bias_count++;
3864                 if (wcd->rx_bias_count == 1) {
3865                         wcd9335_codec_init_flyback(comp);
3866                         snd_soc_component_update_bits(comp,
3867                                                 WCD9335_ANA_RX_SUPPLIES,
3868                                                 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3869                                                 WCD9335_ANA_RX_BIAS_ENABLE);
3870                 }
3871                 break;
3872         case SND_SOC_DAPM_POST_PMD:
3873                 wcd->rx_bias_count--;
3874                 if (!wcd->rx_bias_count)
3875                         snd_soc_component_update_bits(comp,
3876                                         WCD9335_ANA_RX_SUPPLIES,
3877                                         WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3878                                         WCD9335_ANA_RX_BIAS_DISABLE);
3879                 break;
3880         };
3881
3882         return 0;
3883 }
3884
3885 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3886                                         struct snd_kcontrol *kc, int event)
3887 {
3888         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3889         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3890         int hph_mode = wcd->hph_mode;
3891         int ret = 0;
3892
3893         switch (event) {
3894         case SND_SOC_DAPM_PRE_PMU:
3895                 break;
3896         case SND_SOC_DAPM_POST_PMU:
3897                 /*
3898                  * 7ms sleep is required after PA is enabled as per
3899                  * HW requirement
3900                  */
3901                 usleep_range(7000, 7100);
3902                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3903                 snd_soc_component_update_bits(comp,
3904                                         WCD9335_CDC_RX2_RX_PATH_CTL,
3905                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3906                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3907                 /* Remove mix path mute if it is enabled */
3908                 if ((snd_soc_component_read32(comp,
3909                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3910                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3911                         snd_soc_component_update_bits(comp,
3912                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3913                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3914                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3915
3916                 break;
3917
3918         case SND_SOC_DAPM_PRE_PMD:
3919                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3920                 break;
3921         case SND_SOC_DAPM_POST_PMD:
3922                 /* 5ms sleep is required after PA is disabled as per
3923                  * HW requirement
3924                  */
3925                 usleep_range(5000, 5500);
3926                 break;
3927         };
3928
3929         return ret;
3930 }
3931
3932 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3933                                        struct snd_kcontrol *kc, int event)
3934 {
3935         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3936         int ret = 0;
3937
3938         switch (event) {
3939         case SND_SOC_DAPM_POST_PMU:
3940                 /* 5ms sleep is required after PA is enabled as per
3941                  * HW requirement
3942                  */
3943                 usleep_range(5000, 5500);
3944                 snd_soc_component_update_bits(comp,
3945                                         WCD9335_CDC_RX0_RX_PATH_CTL,
3946                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3947                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3948                 /* Remove mix path mute if it is enabled */
3949                 if ((snd_soc_component_read32(comp,
3950                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3951                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3952                         snd_soc_component_update_bits(comp,
3953                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3954                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3955                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3956                 break;
3957         case SND_SOC_DAPM_POST_PMD:
3958                 /* 5ms sleep is required after PA is disabled as per
3959                  * HW requirement
3960                  */
3961                 usleep_range(5000, 5500);
3962
3963                 break;
3964         };
3965
3966         return ret;
3967 }
3968
3969 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3970 {
3971         struct wcd9335_codec *wcd = data;
3972         unsigned long status = 0;
3973         int i, j, port_id;
3974         unsigned int val, int_val = 0;
3975         irqreturn_t ret = IRQ_NONE;
3976         bool tx;
3977         unsigned short reg = 0;
3978
3979         for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3980              i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3981                 regmap_read(wcd->if_regmap, i, &val);
3982                 status |= ((u32)val << (8 * j));
3983         }
3984
3985         for_each_set_bit(j, &status, 32) {
3986                 tx = (j >= 16 ? true : false);
3987                 port_id = (tx ? j - 16 : j);
3988                 regmap_read(wcd->if_regmap,
3989                                 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3990                 if (val) {
3991                         if (!tx)
3992                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3993                                         (port_id / 8);
3994                         else
3995                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3996                                         (port_id / 8);
3997                         regmap_read(
3998                                 wcd->if_regmap, reg, &int_val);
3999                         /*
4000                          * Ignore interrupts for ports for which the
4001                          * interrupts are not specifically enabled.
4002                          */
4003                         if (!(int_val & (1 << (port_id % 8))))
4004                                 continue;
4005                 }
4006
4007                 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
4008                         dev_err_ratelimited(wcd->dev,
4009                            "%s: overflow error on %s port %d, value %x\n",
4010                            __func__, (tx ? "TX" : "RX"), port_id, val);
4011
4012                 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
4013                         dev_err_ratelimited(wcd->dev,
4014                            "%s: underflow error on %s port %d, value %x\n",
4015                            __func__, (tx ? "TX" : "RX"), port_id, val);
4016
4017                 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
4018                         (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
4019                         if (!tx)
4020                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
4021                                         (port_id / 8);
4022                         else
4023                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
4024                                         (port_id / 8);
4025                         regmap_read(
4026                                 wcd->if_regmap, reg, &int_val);
4027                         if (int_val & (1 << (port_id % 8))) {
4028                                 int_val = int_val ^ (1 << (port_id % 8));
4029                                 regmap_write(wcd->if_regmap,
4030                                         reg, int_val);
4031                         }
4032                 }
4033
4034                 regmap_write(wcd->if_regmap,
4035                                 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
4036                                 BIT(j % 8));
4037                 ret = IRQ_HANDLED;
4038         }
4039
4040         return ret;
4041 }
4042
4043 static struct wcd9335_irq wcd9335_irqs[] = {
4044         {
4045                 .irq = WCD9335_IRQ_SLIMBUS,
4046                 .handler = wcd9335_slimbus_irq,
4047                 .name = "SLIM Slave",
4048         },
4049 };
4050
4051 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
4052 {
4053         int irq, ret, i;
4054
4055         for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
4056                 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
4057                 if (irq < 0) {
4058                         dev_err(wcd->dev, "Failed to get %s\n",
4059                                         wcd9335_irqs[i].name);
4060                         return irq;
4061                 }
4062
4063                 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
4064                                                 wcd9335_irqs[i].handler,
4065                                                 IRQF_TRIGGER_RISING,
4066                                                 wcd9335_irqs[i].name, wcd);
4067                 if (ret) {
4068                         dev_err(wcd->dev, "Failed to request %s\n",
4069                                         wcd9335_irqs[i].name);
4070                         return ret;
4071                 }
4072         }
4073
4074         /* enable interrupts on all slave ports */
4075         for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4076                 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4077                              0xFF);
4078
4079         return ret;
4080 }
4081
4082 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4083                                         bool ccl_flag)
4084 {
4085         struct snd_soc_component *comp = wcd->component;
4086
4087         if (ccl_flag) {
4088                 if (++wcd->sido_ccl_cnt == 1)
4089                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4090                                         WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4091         } else {
4092                 if (wcd->sido_ccl_cnt == 0) {
4093                         dev_err(wcd->dev, "sido_ccl already disabled\n");
4094                         return;
4095                 }
4096                 if (--wcd->sido_ccl_cnt == 0)
4097                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4098                                 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4099         }
4100 }
4101
4102 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4103 {
4104         wcd->master_bias_users++;
4105         if (wcd->master_bias_users == 1) {
4106                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4107                                         WCD9335_ANA_BIAS_EN_MASK,
4108                                         WCD9335_ANA_BIAS_ENABLE);
4109                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4110                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4111                                         WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4112                 /*
4113                  * 1ms delay is required after pre-charge is enabled
4114                  * as per HW requirement
4115                  */
4116                 usleep_range(1000, 1100);
4117                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4118                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4119                                         WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4120                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4121                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4122                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4123         }
4124
4125         return 0;
4126 }
4127
4128 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4129 {
4130         /* Enable mclk requires master bias to be enabled first */
4131         if (wcd->master_bias_users <= 0)
4132                 return -EINVAL;
4133
4134         if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4135             ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4136                 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4137                         wcd->clk_type);
4138                 return -EINVAL;
4139         }
4140
4141         if (++wcd->clk_mclk_users == 1) {
4142                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4143                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4144                                         WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4145                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4146                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4147                                         WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4148                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4149                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4150                                         WCD9335_ANA_CLK_MCLK_ENABLE);
4151                 regmap_update_bits(wcd->regmap,
4152                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4153                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4154                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4155                 regmap_update_bits(wcd->regmap,
4156                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4157                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4158                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4159                 /*
4160                  * 10us sleep is required after clock is enabled
4161                  * as per HW requirement
4162                  */
4163                 usleep_range(10, 15);
4164         }
4165
4166         wcd->clk_type = WCD_CLK_MCLK;
4167
4168         return 0;
4169 }
4170
4171 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4172 {
4173         if (wcd->clk_mclk_users <= 0)
4174                 return -EINVAL;
4175
4176         if (--wcd->clk_mclk_users == 0) {
4177                 if (wcd->clk_rco_users > 0) {
4178                         /* MCLK to RCO switch */
4179                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4180                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4181                                         WCD9335_ANA_CLK_MCLK_SRC_RCO);
4182                         wcd->clk_type = WCD_CLK_RCO;
4183                 } else {
4184                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4185                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4186                                         WCD9335_ANA_CLK_MCLK_DISABLE);
4187                         wcd->clk_type = WCD_CLK_OFF;
4188                 }
4189
4190                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4191                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4192                                         WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4193         }
4194
4195         return 0;
4196 }
4197
4198 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4199 {
4200         if (wcd->master_bias_users <= 0)
4201                 return -EINVAL;
4202
4203         wcd->master_bias_users--;
4204         if (wcd->master_bias_users == 0) {
4205                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4206                                 WCD9335_ANA_BIAS_EN_MASK,
4207                                 WCD9335_ANA_BIAS_DISABLE);
4208                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4209                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4210                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4211         }
4212         return 0;
4213 }
4214
4215 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4216                                      bool enable)
4217 {
4218         int ret = 0;
4219
4220         if (enable) {
4221                 wcd9335_cdc_sido_ccl_enable(wcd, true);
4222                 ret = clk_prepare_enable(wcd->mclk);
4223                 if (ret) {
4224                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
4225                                 __func__);
4226                         goto err;
4227                 }
4228                 /* get BG */
4229                 wcd9335_enable_master_bias(wcd);
4230                 /* get MCLK */
4231                 wcd9335_enable_mclk(wcd);
4232
4233         } else {
4234                 /* put MCLK */
4235                 wcd9335_disable_mclk(wcd);
4236                 /* put BG */
4237                 wcd9335_disable_master_bias(wcd);
4238                 clk_disable_unprepare(wcd->mclk);
4239                 wcd9335_cdc_sido_ccl_enable(wcd, false);
4240         }
4241 err:
4242         return ret;
4243 }
4244
4245 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4246                                              enum wcd9335_sido_voltage req_mv)
4247 {
4248         struct snd_soc_component *comp = wcd->component;
4249         int vout_d_val;
4250
4251         if (req_mv == wcd->sido_voltage)
4252                 return;
4253
4254         /* compute the vout_d step value */
4255         vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4256                         WCD9335_ANA_BUCK_VOUT_MASK;
4257         snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4258         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4259                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4260                                 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4261
4262         /* 1 msec sleep required after SIDO Vout_D voltage change */
4263         usleep_range(1000, 1100);
4264         wcd->sido_voltage = req_mv;
4265         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4266                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4267                                 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4268 }
4269
4270 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4271                                              enum wcd9335_sido_voltage req_mv)
4272 {
4273         int ret = 0;
4274
4275         /* enable mclk before setting SIDO voltage */
4276         ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4277         if (ret) {
4278                 dev_err(wcd->dev, "Ext clk enable failed\n");
4279                 goto err;
4280         }
4281
4282         wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4283         wcd9335_cdc_req_mclk_enable(wcd, false);
4284
4285 err:
4286         return ret;
4287 }
4288
4289 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4290                                       int enable)
4291 {
4292         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4293         int ret;
4294
4295         if (enable) {
4296                 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4297                 if (ret)
4298                         return ret;
4299
4300                 wcd9335_codec_apply_sido_voltage(wcd,
4301                                 SIDO_VOLTAGE_NOMINAL_MV);
4302         } else {
4303                 wcd9335_codec_update_sido_voltage(wcd,
4304                                         wcd->sido_voltage);
4305                 wcd9335_cdc_req_mclk_enable(wcd, false);
4306         }
4307
4308         return 0;
4309 }
4310
4311 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4312                                      struct snd_kcontrol *kc, int event)
4313 {
4314         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4315
4316         switch (event) {
4317         case SND_SOC_DAPM_PRE_PMU:
4318                 return _wcd9335_codec_enable_mclk(comp, true);
4319         case SND_SOC_DAPM_POST_PMD:
4320                 return _wcd9335_codec_enable_mclk(comp, false);
4321         }
4322
4323         return 0;
4324 }
4325
4326 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4327         /* TODO SPK1 & SPK2 OUT*/
4328         SND_SOC_DAPM_OUTPUT("EAR"),
4329         SND_SOC_DAPM_OUTPUT("HPHL"),
4330         SND_SOC_DAPM_OUTPUT("HPHR"),
4331         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4332         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4333         SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4334         SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4335         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4336                                 AIF1_PB, 0, wcd9335_codec_enable_slim,
4337                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4338         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4339                                 AIF2_PB, 0, wcd9335_codec_enable_slim,
4340                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4341         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4342                                 AIF3_PB, 0, wcd9335_codec_enable_slim,
4343                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4344         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4345                                 AIF4_PB, 0, wcd9335_codec_enable_slim,
4346                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4347         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4348                                 &slim_rx_mux[WCD9335_RX0]),
4349         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4350                                 &slim_rx_mux[WCD9335_RX1]),
4351         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4352                                 &slim_rx_mux[WCD9335_RX2]),
4353         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4354                                 &slim_rx_mux[WCD9335_RX3]),
4355         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4356                                 &slim_rx_mux[WCD9335_RX4]),
4357         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4358                                 &slim_rx_mux[WCD9335_RX5]),
4359         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4360                                 &slim_rx_mux[WCD9335_RX6]),
4361         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4362                                 &slim_rx_mux[WCD9335_RX7]),
4363         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4364         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4365         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4366         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4367         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4368         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4369         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4370         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4371         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4372                         5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4373                         SND_SOC_DAPM_POST_PMU),
4374         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4375                         5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4376                         SND_SOC_DAPM_POST_PMU),
4377         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4378                         5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4379                         SND_SOC_DAPM_POST_PMU),
4380         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4381                         5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4382                         SND_SOC_DAPM_POST_PMU),
4383         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4384                         5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4385                         SND_SOC_DAPM_POST_PMU),
4386         SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4387                         5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4388                         SND_SOC_DAPM_POST_PMU),
4389         SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4390                         5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4391                         SND_SOC_DAPM_POST_PMU),
4392         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4393                         5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4394                         SND_SOC_DAPM_POST_PMU),
4395         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4396                         5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4397                         SND_SOC_DAPM_POST_PMU),
4398         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4399                 &rx_int0_1_mix_inp0_mux),
4400         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4401                 &rx_int0_1_mix_inp1_mux),
4402         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4403                 &rx_int0_1_mix_inp2_mux),
4404         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4405                 &rx_int1_1_mix_inp0_mux),
4406         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4407                 &rx_int1_1_mix_inp1_mux),
4408         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4409                 &rx_int1_1_mix_inp2_mux),
4410         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4411                 &rx_int2_1_mix_inp0_mux),
4412         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4413                 &rx_int2_1_mix_inp1_mux),
4414         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4415                 &rx_int2_1_mix_inp2_mux),
4416         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4417                 &rx_int3_1_mix_inp0_mux),
4418         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4419                 &rx_int3_1_mix_inp1_mux),
4420         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4421                 &rx_int3_1_mix_inp2_mux),
4422         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4423                 &rx_int4_1_mix_inp0_mux),
4424         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4425                 &rx_int4_1_mix_inp1_mux),
4426         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4427                 &rx_int4_1_mix_inp2_mux),
4428         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4429                 &rx_int5_1_mix_inp0_mux),
4430         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4431                 &rx_int5_1_mix_inp1_mux),
4432         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4433                 &rx_int5_1_mix_inp2_mux),
4434         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4435                 &rx_int6_1_mix_inp0_mux),
4436         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4437                 &rx_int6_1_mix_inp1_mux),
4438         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4439                 &rx_int6_1_mix_inp2_mux),
4440         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4441                 &rx_int7_1_mix_inp0_mux),
4442         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4443                 &rx_int7_1_mix_inp1_mux),
4444         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4445                 &rx_int7_1_mix_inp2_mux),
4446         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4447                 &rx_int8_1_mix_inp0_mux),
4448         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4449                 &rx_int8_1_mix_inp1_mux),
4450         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4451                 &rx_int8_1_mix_inp2_mux),
4452
4453         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4454         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4455         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4456         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4457         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4458         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4459         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4460         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4461         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4462         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4463         SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4464         SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4465         SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466         SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4467         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4468         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4469         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4470         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4471
4472         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4473         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4474         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4475         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4476         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4477         SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4478         SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4479         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4480         SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4481
4482         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4483                 &rx_int0_dem_inp_mux),
4484         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4485                 &rx_int1_dem_inp_mux),
4486         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4487                 &rx_int2_dem_inp_mux),
4488
4489         SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4490                 INTERP_EAR, 0, &rx_int0_interp_mux,
4491                 wcd9335_codec_enable_interpolator,
4492                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4493                 SND_SOC_DAPM_POST_PMD),
4494         SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4495                 INTERP_HPHL, 0, &rx_int1_interp_mux,
4496                 wcd9335_codec_enable_interpolator,
4497                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4498                 SND_SOC_DAPM_POST_PMD),
4499         SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4500                 INTERP_HPHR, 0, &rx_int2_interp_mux,
4501                 wcd9335_codec_enable_interpolator,
4502                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4503                 SND_SOC_DAPM_POST_PMD),
4504         SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4505                 INTERP_LO1, 0, &rx_int3_interp_mux,
4506                 wcd9335_codec_enable_interpolator,
4507                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4508                 SND_SOC_DAPM_POST_PMD),
4509         SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4510                 INTERP_LO2, 0, &rx_int4_interp_mux,
4511                 wcd9335_codec_enable_interpolator,
4512                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4513                 SND_SOC_DAPM_POST_PMD),
4514         SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4515                 INTERP_LO3, 0, &rx_int5_interp_mux,
4516                 wcd9335_codec_enable_interpolator,
4517                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4518                 SND_SOC_DAPM_POST_PMD),
4519         SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4520                 INTERP_LO4, 0, &rx_int6_interp_mux,
4521                 wcd9335_codec_enable_interpolator,
4522                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4523                 SND_SOC_DAPM_POST_PMD),
4524         SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4525                 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4526                 wcd9335_codec_enable_interpolator,
4527                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4528                 SND_SOC_DAPM_POST_PMD),
4529         SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4530                 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4531                 wcd9335_codec_enable_interpolator,
4532                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4533                 SND_SOC_DAPM_POST_PMD),
4534
4535         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4536                 0, 0, wcd9335_codec_ear_dac_event,
4537                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4538                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4539         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4540                 5, 0, wcd9335_codec_hphl_dac_event,
4541                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4542                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4543         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4544                 4, 0, wcd9335_codec_hphr_dac_event,
4545                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4546                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4547         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4548                 0, 0, wcd9335_codec_lineout_dac_event,
4549                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4550         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4551                 0, 0, wcd9335_codec_lineout_dac_event,
4552                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4553         SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4554                 0, 0, wcd9335_codec_lineout_dac_event,
4555                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4556         SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4557                 0, 0, wcd9335_codec_lineout_dac_event,
4558                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4559         SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4560                            wcd9335_codec_enable_hphl_pa,
4561                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4562                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4563         SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4564                            wcd9335_codec_enable_hphr_pa,
4565                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4566                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4567         SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4568                            wcd9335_codec_enable_ear_pa,
4569                            SND_SOC_DAPM_POST_PMU |
4570                            SND_SOC_DAPM_POST_PMD),
4571         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4572                            wcd9335_codec_enable_lineout_pa,
4573                            SND_SOC_DAPM_POST_PMU |
4574                            SND_SOC_DAPM_POST_PMD),
4575         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4576                            wcd9335_codec_enable_lineout_pa,
4577                            SND_SOC_DAPM_POST_PMU |
4578                            SND_SOC_DAPM_POST_PMD),
4579         SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4580                            wcd9335_codec_enable_lineout_pa,
4581                            SND_SOC_DAPM_POST_PMU |
4582                            SND_SOC_DAPM_POST_PMD),
4583         SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4584                            wcd9335_codec_enable_lineout_pa,
4585                            SND_SOC_DAPM_POST_PMU |
4586                            SND_SOC_DAPM_POST_PMD),
4587         SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4588                 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4589                 SND_SOC_DAPM_POST_PMD),
4590         SND_SOC_DAPM_SUPPLY("MCLK",  SND_SOC_NOPM, 0, 0,
4591                 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4592                 SND_SOC_DAPM_POST_PMD),
4593
4594         /* TX */
4595         SND_SOC_DAPM_INPUT("AMIC1"),
4596         SND_SOC_DAPM_INPUT("AMIC2"),
4597         SND_SOC_DAPM_INPUT("AMIC3"),
4598         SND_SOC_DAPM_INPUT("AMIC4"),
4599         SND_SOC_DAPM_INPUT("AMIC5"),
4600         SND_SOC_DAPM_INPUT("AMIC6"),
4601
4602         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4603                 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4604                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4605
4606         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4607                 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4608                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4609
4610         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4611                 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4612                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4613
4614         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4615                                wcd9335_codec_enable_micbias,
4616                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4617                                SND_SOC_DAPM_POST_PMD),
4618         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4619                                wcd9335_codec_enable_micbias,
4620                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4621                                SND_SOC_DAPM_POST_PMD),
4622         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4623                                wcd9335_codec_enable_micbias,
4624                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4625                                SND_SOC_DAPM_POST_PMD),
4626         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4627                                wcd9335_codec_enable_micbias,
4628                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4629                                SND_SOC_DAPM_POST_PMD),
4630
4631         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4632                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4633         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4634                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4635         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4636                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4637         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4638                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4639         SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4640                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4641         SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4642                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4643
4644         /* Digital Mic Inputs */
4645         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4646                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4647                 SND_SOC_DAPM_POST_PMD),
4648
4649         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4650                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4651                 SND_SOC_DAPM_POST_PMD),
4652
4653         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4654                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4655                 SND_SOC_DAPM_POST_PMD),
4656
4657         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4658                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4659                 SND_SOC_DAPM_POST_PMD),
4660
4661         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4662                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4663                 SND_SOC_DAPM_POST_PMD),
4664
4665         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4666                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4667                 SND_SOC_DAPM_POST_PMD),
4668
4669         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4670                 &tx_dmic_mux0),
4671         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4672                 &tx_dmic_mux1),
4673         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4674                 &tx_dmic_mux2),
4675         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4676                 &tx_dmic_mux3),
4677         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4678                 &tx_dmic_mux4),
4679         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4680                 &tx_dmic_mux5),
4681         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4682                 &tx_dmic_mux6),
4683         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4684                 &tx_dmic_mux7),
4685         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4686                 &tx_dmic_mux8),
4687
4688         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4689                 &tx_amic_mux0),
4690         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4691                 &tx_amic_mux1),
4692         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4693                 &tx_amic_mux2),
4694         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4695                 &tx_amic_mux3),
4696         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4697                 &tx_amic_mux4),
4698         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4699                 &tx_amic_mux5),
4700         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4701                 &tx_amic_mux6),
4702         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4703                 &tx_amic_mux7),
4704         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4705                 &tx_amic_mux8),
4706
4707         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4708                 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4709
4710         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4711                 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4712
4713         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4714                 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4715
4716         SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4717                 &sb_tx0_mux),
4718         SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4719                 &sb_tx1_mux),
4720         SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4721                 &sb_tx2_mux),
4722         SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4723                 &sb_tx3_mux),
4724         SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4725                 &sb_tx4_mux),
4726         SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4727                 &sb_tx5_mux),
4728         SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4729                 &sb_tx6_mux),
4730         SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4731                 &sb_tx7_mux),
4732         SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4733                 &sb_tx8_mux),
4734
4735         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4736                            &tx_adc_mux0, wcd9335_codec_enable_dec,
4737                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4738                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4739
4740         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4741                            &tx_adc_mux1, wcd9335_codec_enable_dec,
4742                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4743                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4744
4745         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4746                            &tx_adc_mux2, wcd9335_codec_enable_dec,
4747                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4748                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4749
4750         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4751                            &tx_adc_mux3, wcd9335_codec_enable_dec,
4752                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4753                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4754
4755         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4756                            &tx_adc_mux4, wcd9335_codec_enable_dec,
4757                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4758                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4759
4760         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4761                            &tx_adc_mux5, wcd9335_codec_enable_dec,
4762                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4763                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4764
4765         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4766                            &tx_adc_mux6, wcd9335_codec_enable_dec,
4767                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4768                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4769
4770         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4771                            &tx_adc_mux7, wcd9335_codec_enable_dec,
4772                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4773                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4774
4775         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4776                            &tx_adc_mux8, wcd9335_codec_enable_dec,
4777                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4778                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4779 };
4780
4781 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4782 {
4783         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4784
4785         snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4786                                         WCD9335_ANA_RCO_BG_EN_MASK,
4787                                         WCD9335_ANA_RCO_BG_ENABLE);
4788         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4789                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4790                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4791         /* 100us sleep needed after IREF settings */
4792         usleep_range(100, 110);
4793         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4794                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4795                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4796         /* 100us sleep needed after VREF settings */
4797         usleep_range(100, 110);
4798         wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4799 }
4800
4801 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4802 {
4803         _wcd9335_codec_enable_mclk(comp, true);
4804         snd_soc_component_update_bits(comp,
4805                                 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4806                                 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4807                                 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4808         /*
4809          * 5ms sleep required after enabling efuse control
4810          * before checking the status.
4811          */
4812         usleep_range(5000, 5500);
4813
4814         if (!(snd_soc_component_read32(comp,
4815                                         WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4816                                         WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4817                 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4818
4819         wcd9335_enable_sido_buck(comp);
4820         _wcd9335_codec_enable_mclk(comp, false);
4821
4822         return 0;
4823 }
4824
4825 static void wcd9335_codec_init(struct snd_soc_component *component)
4826 {
4827         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4828         int i;
4829
4830         /* ungate MCLK and set clk rate */
4831         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4832                                 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4833
4834         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4835                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4836                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4837
4838         for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4839                 snd_soc_component_update_bits(component,
4840                                         wcd9335_codec_reg_init[i].reg,
4841                                         wcd9335_codec_reg_init[i].mask,
4842                                         wcd9335_codec_reg_init[i].val);
4843
4844         wcd9335_enable_efuse_sensing(component);
4845 }
4846
4847 static int wcd9335_codec_probe(struct snd_soc_component *component)
4848 {
4849         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4850         int i;
4851
4852         snd_soc_component_init_regmap(component, wcd->regmap);
4853         /* Class-H Init*/
4854         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
4855         if (IS_ERR(wcd->clsh_ctrl))
4856                 return PTR_ERR(wcd->clsh_ctrl);
4857
4858         /* Default HPH Mode to Class-H HiFi */
4859         wcd->hph_mode = CLS_H_HIFI;
4860         wcd->component = component;
4861
4862         wcd9335_codec_init(component);
4863
4864         for (i = 0; i < NUM_CODEC_DAIS; i++)
4865                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4866
4867         return wcd9335_setup_irqs(wcd);
4868 }
4869
4870 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4871 {
4872         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4873
4874         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4875         free_irq(regmap_irq_get_virq(wcd->irq_data, WCD9335_IRQ_SLIMBUS), wcd);
4876 }
4877
4878 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4879                                     int clk_id, int source,
4880                                     unsigned int freq, int dir)
4881 {
4882         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4883
4884         wcd->mclk_rate = freq;
4885
4886         if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4887                 snd_soc_component_update_bits(comp,
4888                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4889                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4890                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4891         else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4892                 snd_soc_component_update_bits(comp,
4893                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4894                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4895                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4896
4897         return clk_set_rate(wcd->mclk, freq);
4898 }
4899
4900 static const struct snd_soc_component_driver wcd9335_component_drv = {
4901         .probe = wcd9335_codec_probe,
4902         .remove = wcd9335_codec_remove,
4903         .set_sysclk = wcd9335_codec_set_sysclk,
4904         .controls = wcd9335_snd_controls,
4905         .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4906         .dapm_widgets = wcd9335_dapm_widgets,
4907         .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4908         .dapm_routes = wcd9335_audio_map,
4909         .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4910 };
4911
4912 static int wcd9335_probe(struct wcd9335_codec *wcd)
4913 {
4914         struct device *dev = wcd->dev;
4915
4916         memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4917         memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4918
4919         wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4920         wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4921
4922         return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4923                                                wcd9335_slim_dais,
4924                                                ARRAY_SIZE(wcd9335_slim_dais));
4925 }
4926
4927 static const struct regmap_range_cfg wcd9335_ranges[] = {
4928         {
4929                 .name = "WCD9335",
4930                 .range_min =  0x0,
4931                 .range_max =  WCD9335_MAX_REGISTER,
4932                 .selector_reg = WCD9335_REG(0x0, 0),
4933                 .selector_mask = 0xff,
4934                 .selector_shift = 0,
4935                 .window_start = 0x0,
4936                 .window_len = 0x1000,
4937         },
4938 };
4939
4940 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4941 {
4942         switch (reg) {
4943         case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4944         case WCD9335_ANA_MBHC_RESULT_3:
4945         case WCD9335_ANA_MBHC_RESULT_2:
4946         case WCD9335_ANA_MBHC_RESULT_1:
4947         case WCD9335_ANA_MBHC_MECH:
4948         case WCD9335_ANA_MBHC_ELECT:
4949         case WCD9335_ANA_MBHC_ZDET:
4950         case WCD9335_ANA_MICB2:
4951         case WCD9335_ANA_RCO:
4952         case WCD9335_ANA_BIAS:
4953                 return true;
4954         default:
4955                 return false;
4956         }
4957 }
4958
4959 static struct regmap_config wcd9335_regmap_config = {
4960         .reg_bits = 16,
4961         .val_bits = 8,
4962         .cache_type = REGCACHE_RBTREE,
4963         .max_register = WCD9335_MAX_REGISTER,
4964         .can_multi_write = true,
4965         .ranges = wcd9335_ranges,
4966         .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4967         .volatile_reg = wcd9335_is_volatile_register,
4968 };
4969
4970 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4971         {
4972                 .name = "WCD9335-IFC-DEV",
4973                 .range_min =  0x0,
4974                 .range_max = WCD9335_REG(0, 0x7ff),
4975                 .selector_reg = WCD9335_REG(0, 0x0),
4976                 .selector_mask = 0xff,
4977                 .selector_shift = 0,
4978                 .window_start = 0x0,
4979                 .window_len = 0x1000,
4980         },
4981 };
4982
4983 static struct regmap_config wcd9335_ifc_regmap_config = {
4984         .reg_bits = 16,
4985         .val_bits = 8,
4986         .can_multi_write = true,
4987         .max_register = WCD9335_REG(0, 0x7FF),
4988         .ranges = wcd9335_ifc_ranges,
4989         .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4990 };
4991
4992 static const struct regmap_irq wcd9335_codec_irqs[] = {
4993         /* INTR_REG 0 */
4994         [WCD9335_IRQ_SLIMBUS] = {
4995                 .reg_offset = 0,
4996                 .mask = BIT(0),
4997                 .type = {
4998                         .type_reg_offset = 0,
4999                         .types_supported = IRQ_TYPE_EDGE_BOTH,
5000                         .type_reg_mask  = BIT(0),
5001                 },
5002         },
5003 };
5004
5005 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
5006         .name = "wcd9335_pin1_irq",
5007         .status_base = WCD9335_INTR_PIN1_STATUS0,
5008         .mask_base = WCD9335_INTR_PIN1_MASK0,
5009         .ack_base = WCD9335_INTR_PIN1_CLEAR0,
5010         .type_base = WCD9335_INTR_LEVEL0,
5011         .num_type_reg = 4,
5012         .num_regs = 4,
5013         .irqs = wcd9335_codec_irqs,
5014         .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
5015 };
5016
5017 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
5018 {
5019         struct device *dev = wcd->dev;
5020         struct device_node *np = dev->of_node;
5021         int ret;
5022
5023         wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
5024         if (wcd->reset_gpio < 0) {
5025                 dev_err(dev, "Reset GPIO missing from DT\n");
5026                 return wcd->reset_gpio;
5027         }
5028
5029         wcd->mclk = devm_clk_get(dev, "mclk");
5030         if (IS_ERR(wcd->mclk)) {
5031                 dev_err(dev, "mclk not found\n");
5032                 return PTR_ERR(wcd->mclk);
5033         }
5034
5035         wcd->native_clk = devm_clk_get(dev, "slimbus");
5036         if (IS_ERR(wcd->native_clk)) {
5037                 dev_err(dev, "slimbus clock not found\n");
5038                 return PTR_ERR(wcd->native_clk);
5039         }
5040
5041         wcd->supplies[0].supply = "vdd-buck";
5042         wcd->supplies[1].supply = "vdd-buck-sido";
5043         wcd->supplies[2].supply = "vdd-tx";
5044         wcd->supplies[3].supply = "vdd-rx";
5045         wcd->supplies[4].supply = "vdd-io";
5046
5047         ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
5048         if (ret) {
5049                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5050                 return ret;
5051         }
5052
5053         return 0;
5054 }
5055
5056 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5057 {
5058         struct device *dev = wcd->dev;
5059         int ret;
5060
5061         ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
5062         if (ret) {
5063                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5064                 return ret;
5065         }
5066
5067         /*
5068          * For WCD9335, it takes about 600us for the Vout_A and
5069          * Vout_D to be ready after BUCK_SIDO is powered up.
5070          * SYS_RST_N shouldn't be pulled high during this time
5071          * Toggle the reset line to make sure the reset pulse is
5072          * correctly applied
5073          */
5074         usleep_range(600, 650);
5075
5076         gpio_direction_output(wcd->reset_gpio, 0);
5077         msleep(20);
5078         gpio_set_value(wcd->reset_gpio, 1);
5079         msleep(20);
5080
5081         return 0;
5082 }
5083
5084 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5085 {
5086         struct regmap *rm = wcd->regmap;
5087         int val, byte0;
5088
5089         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5090         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5091
5092         if ((val < 0) || (byte0 < 0)) {
5093                 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5094                 return -EINVAL;
5095         }
5096
5097         if (byte0 == 0x1) {
5098                 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5099                 wcd->version = WCD9335_VERSION_2_0;
5100                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5101                 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5102                 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5103                 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5104                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5105                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5106                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5107                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5108         } else {
5109                 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5110                 return -EINVAL;
5111         }
5112
5113         return 0;
5114 }
5115
5116 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5117 {
5118         int ret;
5119
5120         /*
5121          * INTR1 consists of all possible interrupt sources Ear OCP,
5122          * HPH OCP, MBHC, MAD, VBAT, and SVA
5123          * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5124          */
5125         wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5126         if (wcd->intr1 < 0) {
5127                 if (wcd->intr1 != -EPROBE_DEFER)
5128                         dev_err(wcd->dev, "Unable to configure IRQ\n");
5129
5130                 return wcd->intr1;
5131         }
5132
5133         ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5134                                  IRQF_TRIGGER_HIGH, 0,
5135                                  &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5136         if (ret)
5137                 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret);
5138
5139         return ret;
5140 }
5141
5142 static int wcd9335_slim_probe(struct slim_device *slim)
5143 {
5144         struct device *dev = &slim->dev;
5145         struct wcd9335_codec *wcd;
5146         int ret;
5147
5148         wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5149         if (!wcd)
5150                 return  -ENOMEM;
5151
5152         wcd->dev = dev;
5153         ret = wcd9335_parse_dt(wcd);
5154         if (ret) {
5155                 dev_err(dev, "Error parsing DT: %d\n", ret);
5156                 return ret;
5157         }
5158
5159         ret = wcd9335_power_on_reset(wcd);
5160         if (ret)
5161                 return ret;
5162
5163         dev_set_drvdata(dev, wcd);
5164
5165         return 0;
5166 }
5167
5168 static int wcd9335_slim_status(struct slim_device *sdev,
5169                                enum slim_device_status status)
5170 {
5171         struct device *dev = &sdev->dev;
5172         struct device_node *ifc_dev_np;
5173         struct wcd9335_codec *wcd;
5174         int ret;
5175
5176         wcd = dev_get_drvdata(dev);
5177
5178         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5179         if (!ifc_dev_np) {
5180                 dev_err(dev, "No Interface device found\n");
5181                 return -EINVAL;
5182         }
5183
5184         wcd->slim = sdev;
5185         wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5186         of_node_put(ifc_dev_np);
5187         if (!wcd->slim_ifc_dev) {
5188                 dev_err(dev, "Unable to get SLIM Interface device\n");
5189                 return -EINVAL;
5190         }
5191
5192         slim_get_logical_addr(wcd->slim_ifc_dev);
5193
5194         wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5195         if (IS_ERR(wcd->regmap)) {
5196                 dev_err(dev, "Failed to allocate slim register map\n");
5197                 return PTR_ERR(wcd->regmap);
5198         }
5199
5200         wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5201                                                   &wcd9335_ifc_regmap_config);
5202         if (IS_ERR(wcd->if_regmap)) {
5203                 dev_err(dev, "Failed to allocate ifc register map\n");
5204                 return PTR_ERR(wcd->if_regmap);
5205         }
5206
5207         ret = wcd9335_bring_up(wcd);
5208         if (ret) {
5209                 dev_err(dev, "Failed to bringup WCD9335\n");
5210                 return ret;
5211         }
5212
5213         ret = wcd9335_irq_init(wcd);
5214         if (ret)
5215                 return ret;
5216
5217         wcd9335_probe(wcd);
5218
5219         return ret;
5220 }
5221
5222 static const struct slim_device_id wcd9335_slim_id[] = {
5223         {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5224         {}
5225 };
5226 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5227
5228 static struct slim_driver wcd9335_slim_driver = {
5229         .driver = {
5230                 .name = "wcd9335-slim",
5231         },
5232         .probe = wcd9335_slim_probe,
5233         .device_status = wcd9335_slim_status,
5234         .id_table = wcd9335_slim_id,
5235 };
5236
5237 module_slim_driver(wcd9335_slim_driver);
5238 MODULE_DESCRIPTION("WCD9335 slim driver");
5239 MODULE_LICENSE("GPL v2");
5240 MODULE_ALIAS("slim:217:1a0:*");