2 * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * Author: Nicolin Chen <nicoleotsuka@gmail.com>
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/module.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_data/dma-imx.h>
19 #include <linux/pm_runtime.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
25 #define IDEAL_RATIO_DECIMAL_DEPTH 26
27 #define pair_err(fmt, ...) \
28 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
30 #define pair_dbg(fmt, ...) \
31 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
33 /* Sample rates are aligned with that defined in pcm.h file */
34 static const u8 process_option[][12][2] = {
35 /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
36 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
37 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
38 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
39 {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
40 {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
41 {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
42 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
43 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
44 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
45 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
46 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
47 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
48 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
51 /* Corresponding to process_option */
52 static int supported_input_rate[] = {
53 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
54 96000, 176400, 192000,
57 static int supported_asrc_rate[] = {
58 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
62 * The following tables map the relationship between asrc_inclk/asrc_outclk in
63 * fsl_asrc.h and the registers of ASRCSR
65 static unsigned char input_clk_map_imx35[] = {
66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
69 static unsigned char output_clk_map_imx35[] = {
70 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
73 /* i.MX53 uses the same map for input and output */
74 static unsigned char input_clk_map_imx53[] = {
75 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
76 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
79 static unsigned char output_clk_map_imx53[] = {
80 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
81 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
84 static unsigned char *clk_map[2];
89 * It assigns pair by the order of A->C->B because allocation of pair B,
90 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
91 * while pair A and pair C are comparatively independent.
93 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
95 enum asrc_pair_index index = ASRC_INVALID_PAIR;
96 struct fsl_asrc *asrc_priv = pair->asrc_priv;
97 struct device *dev = &asrc_priv->pdev->dev;
98 unsigned long lock_flags;
101 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
103 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
104 if (asrc_priv->pair[i] != NULL)
109 if (i != ASRC_PAIR_B)
113 if (index == ASRC_INVALID_PAIR) {
114 dev_err(dev, "all pairs are busy now\n");
116 } else if (asrc_priv->channel_avail < channels) {
117 dev_err(dev, "can't afford required channels: %d\n", channels);
120 asrc_priv->channel_avail -= channels;
121 asrc_priv->pair[index] = pair;
122 pair->channels = channels;
126 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
134 * It clears the resource from asrc_priv and releases the occupied channels.
136 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
138 struct fsl_asrc *asrc_priv = pair->asrc_priv;
139 enum asrc_pair_index index = pair->index;
140 unsigned long lock_flags;
142 /* Make sure the pair is disabled */
143 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
144 ASRCTR_ASRCEi_MASK(index), 0);
146 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
148 asrc_priv->channel_avail += pair->channels;
149 asrc_priv->pair[index] = NULL;
152 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
156 * Configure input and output thresholds
158 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
160 struct fsl_asrc *asrc_priv = pair->asrc_priv;
161 enum asrc_pair_index index = pair->index;
163 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
164 ASRMCRi_EXTTHRSHi_MASK |
165 ASRMCRi_INFIFO_THRESHOLD_MASK |
166 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
168 ASRMCRi_INFIFO_THRESHOLD(in) |
169 ASRMCRi_OUTFIFO_THRESHOLD(out));
173 * Calculate the total divisor between asrck clock rate and sample rate
175 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
177 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
181 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
182 for (ps = 0; div > 8; ps++)
185 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
189 * Calculate and set the ratio for Ideal Ratio mode only
191 * The ratio is a 32-bit fixed point value with 26 fractional bits.
193 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
194 int inrate, int outrate)
196 struct fsl_asrc *asrc_priv = pair->asrc_priv;
197 enum asrc_pair_index index = pair->index;
202 pair_err("output rate should not be zero\n");
206 /* Calculate the intergal part of the ratio */
207 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
209 /* ... and then the 26 depth decimal part */
212 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
215 if (inrate < outrate)
218 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
225 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
226 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
232 * Configure the assigned ASRC pair
234 * It configures those ASRC registers according to a configuration instance
235 * of struct asrc_config which includes in/output sample rate, width, channel
236 * and clock settings.
238 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
240 struct asrc_config *config = pair->config;
241 struct fsl_asrc *asrc_priv = pair->asrc_priv;
242 enum asrc_pair_index index = pair->index;
243 u32 inrate, outrate, indiv, outdiv;
244 u32 clk_index[2], div[2];
245 int in, out, channels;
250 pair_err("invalid pair config\n");
254 /* Validate channels */
255 if (config->channel_num < 1 || config->channel_num > 10) {
256 pair_err("does not support %d channels\n", config->channel_num);
260 /* Validate output width */
261 if (config->output_word_width == ASRC_WIDTH_8_BIT) {
262 pair_err("does not support 8bit width output\n");
266 inrate = config->input_sample_rate;
267 outrate = config->output_sample_rate;
268 ideal = config->inclk == INCLK_NONE;
270 /* Validate input and output sample rates */
271 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
272 if (inrate == supported_input_rate[in])
275 if (in == ARRAY_SIZE(supported_input_rate)) {
276 pair_err("unsupported input sample rate: %dHz\n", inrate);
280 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
281 if (outrate == supported_asrc_rate[out])
284 if (out == ARRAY_SIZE(supported_asrc_rate)) {
285 pair_err("unsupported output sample rate: %dHz\n", outrate);
289 if ((outrate > 8000 && outrate < 30000) &&
290 (outrate/inrate > 24 || inrate/outrate > 8)) {
291 pair_err("exceed supported ratio range [1/24, 8] for \
292 inrate/outrate: %d/%d\n", inrate, outrate);
296 /* Validate input and output clock sources */
297 clk_index[IN] = clk_map[IN][config->inclk];
298 clk_index[OUT] = clk_map[OUT][config->outclk];
300 /* We only have output clock for ideal ratio mode */
301 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
303 div[IN] = clk_get_rate(clk) / inrate;
305 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
306 inrate, clk_index[ideal ? OUT : IN]);
310 clk = asrc_priv->asrck_clk[clk_index[OUT]];
312 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
314 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
316 div[OUT] = clk_get_rate(clk) / outrate;
319 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
320 outrate, clk_index[OUT]);
324 /* Set the channel number */
325 channels = config->channel_num;
327 if (asrc_priv->channel_bits < 4)
330 /* Update channels for current pair */
331 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
332 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
333 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
335 /* Default setting: Automatic selection for processing mode */
336 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
337 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
338 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
339 ASRCTR_USRi_MASK(index), 0);
341 /* Set the input and output clock sources */
342 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
343 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
344 ASRCSR_AICS(index, clk_index[IN]) |
345 ASRCSR_AOCS(index, clk_index[OUT]));
347 /* Calculate the input clock divisors */
348 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
349 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
351 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
352 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
353 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
354 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
355 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
357 /* Implement word_width configurations */
358 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
359 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
360 ASRMCR1i_OW16(config->output_word_width) |
361 ASRMCR1i_IWD(config->input_word_width));
363 /* Enable BUFFER STALL */
364 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
365 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
367 /* Set default thresholds for input and output FIFO */
368 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
369 ASRC_INPUTFIFO_THRESHOLD);
371 /* Configure the following only for Ideal Ratio mode */
375 /* Clear ASTSx bit to use Ideal Ratio mode */
376 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
377 ASRCTR_ATSi_MASK(index), 0);
379 /* Enable Ideal Ratio mode */
380 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
381 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
382 ASRCTR_IDR(index) | ASRCTR_USR(index));
384 /* Apply configurations for pre- and post-processing */
385 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
386 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
387 ASRCFG_PREMOD(index, process_option[in][out][0]) |
388 ASRCFG_POSTMOD(index, process_option[in][out][1]));
390 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
394 * Start the assigned ASRC pair
396 * It enables the assigned pair and makes it stopped at the stall level.
398 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
400 struct fsl_asrc *asrc_priv = pair->asrc_priv;
401 enum asrc_pair_index index = pair->index;
402 int reg, retry = 10, i;
404 /* Enable the current pair */
405 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
406 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
408 /* Wait for status of initialization */
411 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
412 reg &= ASRCFG_INIRQi_MASK(index);
413 } while (!reg && --retry);
415 /* Make the input fifo to ASRC STALL level */
416 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
417 for (i = 0; i < pair->channels * 4; i++)
418 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
420 /* Enable overload interrupt */
421 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
425 * Stop the assigned ASRC pair
427 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
429 struct fsl_asrc *asrc_priv = pair->asrc_priv;
430 enum asrc_pair_index index = pair->index;
432 /* Stop the current pair */
433 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
434 ASRCTR_ASRCEi_MASK(index), 0);
438 * Get DMA channel according to the pair and direction.
440 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
442 struct fsl_asrc *asrc_priv = pair->asrc_priv;
443 enum asrc_pair_index index = pair->index;
446 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
448 return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
450 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
452 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
453 struct snd_pcm_hw_params *params,
454 struct snd_soc_dai *dai)
456 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
457 int width = params_width(params);
458 struct snd_pcm_runtime *runtime = substream->runtime;
459 struct fsl_asrc_pair *pair = runtime->private_data;
460 unsigned int channels = params_channels(params);
461 unsigned int rate = params_rate(params);
462 struct asrc_config config;
465 ret = fsl_asrc_request_pair(channels, pair);
467 dev_err(dai->dev, "fail to request asrc pair\n");
471 pair->config = &config;
474 width = ASRC_WIDTH_16_BIT;
476 width = ASRC_WIDTH_24_BIT;
478 if (asrc_priv->asrc_width == 16)
479 word_width = ASRC_WIDTH_16_BIT;
481 word_width = ASRC_WIDTH_24_BIT;
483 config.pair = pair->index;
484 config.channel_num = channels;
485 config.inclk = INCLK_NONE;
486 config.outclk = OUTCLK_ASRCK1_CLK;
488 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
489 config.input_word_width = width;
490 config.output_word_width = word_width;
491 config.input_sample_rate = rate;
492 config.output_sample_rate = asrc_priv->asrc_rate;
494 config.input_word_width = word_width;
495 config.output_word_width = width;
496 config.input_sample_rate = asrc_priv->asrc_rate;
497 config.output_sample_rate = rate;
500 ret = fsl_asrc_config_pair(pair);
502 dev_err(dai->dev, "fail to config asrc pair\n");
509 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
510 struct snd_soc_dai *dai)
512 struct snd_pcm_runtime *runtime = substream->runtime;
513 struct fsl_asrc_pair *pair = runtime->private_data;
516 fsl_asrc_release_pair(pair);
521 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
522 struct snd_soc_dai *dai)
524 struct snd_pcm_runtime *runtime = substream->runtime;
525 struct fsl_asrc_pair *pair = runtime->private_data;
528 case SNDRV_PCM_TRIGGER_START:
529 case SNDRV_PCM_TRIGGER_RESUME:
530 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
531 fsl_asrc_start_pair(pair);
533 case SNDRV_PCM_TRIGGER_STOP:
534 case SNDRV_PCM_TRIGGER_SUSPEND:
535 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
536 fsl_asrc_stop_pair(pair);
545 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
546 .hw_params = fsl_asrc_dai_hw_params,
547 .hw_free = fsl_asrc_dai_hw_free,
548 .trigger = fsl_asrc_dai_trigger,
551 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
553 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
555 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
556 &asrc_priv->dma_params_rx);
561 #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
562 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
563 SNDRV_PCM_FMTBIT_S16_LE | \
564 SNDRV_PCM_FMTBIT_S20_3LE)
566 static struct snd_soc_dai_driver fsl_asrc_dai = {
567 .probe = fsl_asrc_dai_probe,
569 .stream_name = "ASRC-Playback",
572 .rates = FSL_ASRC_RATES,
573 .formats = FSL_ASRC_FORMATS,
576 .stream_name = "ASRC-Capture",
579 .rates = FSL_ASRC_RATES,
580 .formats = FSL_ASRC_FORMATS,
582 .ops = &fsl_asrc_dai_ops,
585 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
629 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
649 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
690 static struct reg_default fsl_asrc_reg[] = {
691 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
692 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
693 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
694 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
695 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
696 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
697 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
698 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
699 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
700 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
701 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
702 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
703 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
704 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
705 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
706 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
707 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
708 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
709 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
710 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
711 { REG_ASRMCR1C, 0x0000 },
714 static const struct regmap_config fsl_asrc_regmap_config = {
719 .max_register = REG_ASRMCR1C,
720 .reg_defaults = fsl_asrc_reg,
721 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
722 .readable_reg = fsl_asrc_readable_reg,
723 .volatile_reg = fsl_asrc_volatile_reg,
724 .writeable_reg = fsl_asrc_writeable_reg,
725 .cache_type = REGCACHE_FLAT,
729 * Initialize ASRC registers with a default configurations
731 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
733 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
734 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
736 /* Disable interrupt by default */
737 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
739 /* Apply recommended settings for parameters from Reference Manual */
740 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
741 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
742 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
743 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
744 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
746 /* Base address for task queue FIFO. Set to 0x7C */
747 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
748 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
750 /* Set the processing clock for 76KHz to 133M */
751 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
753 /* Set the processing clock for 56KHz to 133M */
754 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
758 * Interrupt handler for ASRC
760 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
762 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
763 struct device *dev = &asrc_priv->pdev->dev;
764 enum asrc_pair_index index;
767 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
769 /* Clean overload error */
770 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
773 * We here use dev_dbg() for all exceptions because ASRC itself does
774 * not care if FIFO overflowed or underrun while a warning in the
775 * interrupt would result a ridged conversion.
777 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
778 if (!asrc_priv->pair[index])
781 if (status & ASRSTR_ATQOL) {
782 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
783 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
786 if (status & ASRSTR_AOOL(index)) {
787 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
788 pair_dbg("Output Task Overload\n");
791 if (status & ASRSTR_AIOL(index)) {
792 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
793 pair_dbg("Input Task Overload\n");
796 if (status & ASRSTR_AODO(index)) {
797 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
798 pair_dbg("Output Data Buffer has overflowed\n");
801 if (status & ASRSTR_AIDU(index)) {
802 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
803 pair_dbg("Input Data Buffer has underflowed\n");
810 static int fsl_asrc_probe(struct platform_device *pdev)
812 struct device_node *np = pdev->dev.of_node;
813 struct fsl_asrc *asrc_priv;
814 struct resource *res;
819 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
823 asrc_priv->pdev = pdev;
825 /* Get the addresses and IRQ */
826 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
827 regs = devm_ioremap_resource(&pdev->dev, res);
829 return PTR_ERR(regs);
831 asrc_priv->paddr = res->start;
833 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
834 &fsl_asrc_regmap_config);
835 if (IS_ERR(asrc_priv->regmap)) {
836 dev_err(&pdev->dev, "failed to init regmap\n");
837 return PTR_ERR(asrc_priv->regmap);
840 irq = platform_get_irq(pdev, 0);
842 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
846 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
847 dev_name(&pdev->dev), asrc_priv);
849 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
853 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
854 if (IS_ERR(asrc_priv->mem_clk)) {
855 dev_err(&pdev->dev, "failed to get mem clock\n");
856 return PTR_ERR(asrc_priv->mem_clk);
859 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
860 if (IS_ERR(asrc_priv->ipg_clk)) {
861 dev_err(&pdev->dev, "failed to get ipg clock\n");
862 return PTR_ERR(asrc_priv->ipg_clk);
865 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
866 if (IS_ERR(asrc_priv->spba_clk))
867 dev_warn(&pdev->dev, "failed to get spba clock\n");
869 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
870 sprintf(tmp, "asrck_%x", i);
871 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
872 if (IS_ERR(asrc_priv->asrck_clk[i])) {
873 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
874 return PTR_ERR(asrc_priv->asrck_clk[i]);
878 if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
879 asrc_priv->channel_bits = 3;
880 clk_map[IN] = input_clk_map_imx35;
881 clk_map[OUT] = output_clk_map_imx35;
883 asrc_priv->channel_bits = 4;
884 clk_map[IN] = input_clk_map_imx53;
885 clk_map[OUT] = output_clk_map_imx53;
888 ret = fsl_asrc_init(asrc_priv);
890 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
894 asrc_priv->channel_avail = 10;
896 ret = of_property_read_u32(np, "fsl,asrc-rate",
897 &asrc_priv->asrc_rate);
899 dev_err(&pdev->dev, "failed to get output rate\n");
903 ret = of_property_read_u32(np, "fsl,asrc-width",
904 &asrc_priv->asrc_width);
906 dev_err(&pdev->dev, "failed to get output width\n");
910 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
911 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
912 asrc_priv->asrc_width = 24;
915 platform_set_drvdata(pdev, asrc_priv);
916 pm_runtime_enable(&pdev->dev);
917 spin_lock_init(&asrc_priv->lock);
919 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
922 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
930 static int fsl_asrc_runtime_resume(struct device *dev)
932 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
935 ret = clk_prepare_enable(asrc_priv->mem_clk);
938 ret = clk_prepare_enable(asrc_priv->ipg_clk);
940 goto disable_mem_clk;
941 if (!IS_ERR(asrc_priv->spba_clk)) {
942 ret = clk_prepare_enable(asrc_priv->spba_clk);
944 goto disable_ipg_clk;
946 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
947 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
949 goto disable_asrck_clk;
955 for (i--; i >= 0; i--)
956 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
957 if (!IS_ERR(asrc_priv->spba_clk))
958 clk_disable_unprepare(asrc_priv->spba_clk);
960 clk_disable_unprepare(asrc_priv->ipg_clk);
962 clk_disable_unprepare(asrc_priv->mem_clk);
966 static int fsl_asrc_runtime_suspend(struct device *dev)
968 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
971 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
972 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
973 if (!IS_ERR(asrc_priv->spba_clk))
974 clk_disable_unprepare(asrc_priv->spba_clk);
975 clk_disable_unprepare(asrc_priv->ipg_clk);
976 clk_disable_unprepare(asrc_priv->mem_clk);
980 #endif /* CONFIG_PM */
982 #ifdef CONFIG_PM_SLEEP
983 static int fsl_asrc_suspend(struct device *dev)
985 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
987 regmap_read(asrc_priv->regmap, REG_ASRCFG,
988 &asrc_priv->regcache_cfg);
990 regcache_cache_only(asrc_priv->regmap, true);
991 regcache_mark_dirty(asrc_priv->regmap);
996 static int fsl_asrc_resume(struct device *dev)
998 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1001 /* Stop all pairs provisionally */
1002 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
1003 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1004 ASRCTR_ASRCEi_ALL_MASK, 0);
1006 /* Restore all registers */
1007 regcache_cache_only(asrc_priv->regmap, false);
1008 regcache_sync(asrc_priv->regmap);
1010 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1011 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1012 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1014 /* Restart enabled pairs */
1015 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1016 ASRCTR_ASRCEi_ALL_MASK, asrctr);
1020 #endif /* CONFIG_PM_SLEEP */
1022 static const struct dev_pm_ops fsl_asrc_pm = {
1023 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1024 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1027 static const struct of_device_id fsl_asrc_ids[] = {
1028 { .compatible = "fsl,imx35-asrc", },
1029 { .compatible = "fsl,imx53-asrc", },
1032 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1034 static struct platform_driver fsl_asrc_driver = {
1035 .probe = fsl_asrc_probe,
1038 .of_match_table = fsl_asrc_ids,
1042 module_platform_driver(fsl_asrc_driver);
1044 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1045 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1046 MODULE_ALIAS("platform:fsl-asrc");
1047 MODULE_LICENSE("GPL v2");