1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
7 // Author: Nicolin Chen <nicoleotsuka@gmail.com>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_data/dma-imx.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
21 #define IDEAL_RATIO_DECIMAL_DEPTH 26
23 #define pair_err(fmt, ...) \
24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
26 #define pair_dbg(fmt, ...) \
27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 /* Corresponding to process_option */
30 static unsigned int supported_asrc_rate[] = {
31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
32 64000, 88200, 96000, 128000, 176400, 192000,
35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
36 .count = ARRAY_SIZE(supported_asrc_rate),
37 .list = supported_asrc_rate,
41 * The following tables map the relationship between asrc_inclk/asrc_outclk in
42 * fsl_asrc.h and the registers of ASRCSR
44 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
46 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
47 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
50 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
51 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
53 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
56 /* i.MX53 uses the same map for input and output */
57 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
58 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
59 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
60 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
61 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
64 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
65 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
66 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
67 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
68 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
72 * i.MX8QM/i.MX8QXP uses the same map for input and output.
73 * clk_map_imx8qm[0] is for i.MX8QM asrc0
74 * clk_map_imx8qm[1] is for i.MX8QM asrc1
75 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
76 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1
78 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
81 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
82 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
85 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
86 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
87 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
91 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
93 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
94 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
95 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
98 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
99 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
100 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
105 * Select the pre-processing and post-processing options
106 * Make sure to exclude following unsupported cases before
107 * calling this function:
108 * 1) inrate > 8.125 * outrate
109 * 2) inrate > 16.125 * outrate
111 * inrate: input sample rate
112 * outrate: output sample rate
113 * pre_proc: return value for pre-processing option
114 * post_proc: return value for post-processing option
116 static void fsl_asrc_sel_proc(int inrate, int outrate,
117 int *pre_proc, int *post_proc)
119 bool post_proc_cond2;
120 bool post_proc_cond0;
122 /* select pre_proc between [0, 2] */
123 if (inrate * 8 > 33 * outrate)
125 else if (inrate * 8 > 15 * outrate) {
130 } else if (inrate < 76000)
132 else if (inrate > 152000)
137 /* Condition for selection of post-processing */
138 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
139 (inrate > 56000 && outrate < 56000);
140 post_proc_cond0 = inrate * 23 < outrate * 8;
144 else if (post_proc_cond0)
153 * It assigns pair by the order of A->C->B because allocation of pair B,
154 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
155 * while pair A and pair C are comparatively independent.
157 int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
159 enum asrc_pair_index index = ASRC_INVALID_PAIR;
160 struct fsl_asrc *asrc_priv = pair->asrc_priv;
161 struct device *dev = &asrc_priv->pdev->dev;
162 unsigned long lock_flags;
165 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
167 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
168 if (asrc_priv->pair[i] != NULL)
173 if (i != ASRC_PAIR_B)
177 if (index == ASRC_INVALID_PAIR) {
178 dev_err(dev, "all pairs are busy now\n");
180 } else if (asrc_priv->channel_avail < channels) {
181 dev_err(dev, "can't afford required channels: %d\n", channels);
184 asrc_priv->channel_avail -= channels;
185 asrc_priv->pair[index] = pair;
186 pair->channels = channels;
190 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
198 * It clears the resource from asrc_priv and releases the occupied channels.
200 void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
202 struct fsl_asrc *asrc_priv = pair->asrc_priv;
203 enum asrc_pair_index index = pair->index;
204 unsigned long lock_flags;
206 /* Make sure the pair is disabled */
207 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
208 ASRCTR_ASRCEi_MASK(index), 0);
210 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
212 asrc_priv->channel_avail += pair->channels;
213 asrc_priv->pair[index] = NULL;
216 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
220 * Configure input and output thresholds
222 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
224 struct fsl_asrc *asrc_priv = pair->asrc_priv;
225 enum asrc_pair_index index = pair->index;
227 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
228 ASRMCRi_EXTTHRSHi_MASK |
229 ASRMCRi_INFIFO_THRESHOLD_MASK |
230 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
232 ASRMCRi_INFIFO_THRESHOLD(in) |
233 ASRMCRi_OUTFIFO_THRESHOLD(out));
237 * Calculate the total divisor between asrck clock rate and sample rate
239 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
241 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
245 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
246 for (ps = 0; div > 8; ps++)
249 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
253 * Calculate and set the ratio for Ideal Ratio mode only
255 * The ratio is a 32-bit fixed point value with 26 fractional bits.
257 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
258 int inrate, int outrate)
260 struct fsl_asrc *asrc_priv = pair->asrc_priv;
261 enum asrc_pair_index index = pair->index;
266 pair_err("output rate should not be zero\n");
270 /* Calculate the intergal part of the ratio */
271 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
273 /* ... and then the 26 depth decimal part */
276 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
279 if (inrate < outrate)
282 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
289 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
290 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
296 * Configure the assigned ASRC pair
298 * It configures those ASRC registers according to a configuration instance
299 * of struct asrc_config which includes in/output sample rate, width, channel
300 * and clock settings.
303 * The ideal ratio configuration can work with a flexible clock rate setting.
304 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
305 * For a regular audio playback, the clock rate should not be slower than an
306 * clock rate aligning with the output sample rate; For a use case requiring
307 * faster conversion, set use_ideal_rate to have the faster speed.
309 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
311 struct asrc_config *config = pair->config;
312 struct fsl_asrc *asrc_priv = pair->asrc_priv;
313 enum asrc_pair_index index = pair->index;
314 enum asrc_word_width input_word_width;
315 enum asrc_word_width output_word_width;
316 u32 inrate, outrate, indiv, outdiv;
317 u32 clk_index[2], div[2], rem[2];
319 int in, out, channels;
320 int pre_proc, post_proc;
325 pair_err("invalid pair config\n");
329 /* Validate channels */
330 if (config->channel_num < 1 || config->channel_num > 10) {
331 pair_err("does not support %d channels\n", config->channel_num);
335 switch (snd_pcm_format_width(config->input_format)) {
337 input_word_width = ASRC_WIDTH_8_BIT;
340 input_word_width = ASRC_WIDTH_16_BIT;
343 input_word_width = ASRC_WIDTH_24_BIT;
346 pair_err("does not support this input format, %d\n",
347 config->input_format);
351 switch (snd_pcm_format_width(config->output_format)) {
353 output_word_width = ASRC_WIDTH_16_BIT;
356 output_word_width = ASRC_WIDTH_24_BIT;
359 pair_err("does not support this output format, %d\n",
360 config->output_format);
364 inrate = config->input_sample_rate;
365 outrate = config->output_sample_rate;
366 ideal = config->inclk == INCLK_NONE;
368 /* Validate input and output sample rates */
369 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
370 if (inrate == supported_asrc_rate[in])
373 if (in == ARRAY_SIZE(supported_asrc_rate)) {
374 pair_err("unsupported input sample rate: %dHz\n", inrate);
378 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
379 if (outrate == supported_asrc_rate[out])
382 if (out == ARRAY_SIZE(supported_asrc_rate)) {
383 pair_err("unsupported output sample rate: %dHz\n", outrate);
387 if ((outrate >= 5512 && outrate <= 30000) &&
388 (outrate > 24 * inrate || inrate > 8 * outrate)) {
389 pair_err("exceed supported ratio range [1/24, 8] for \
390 inrate/outrate: %d/%d\n", inrate, outrate);
394 /* Validate input and output clock sources */
395 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
396 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
398 /* We only have output clock for ideal ratio mode */
399 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
401 clk_rate = clk_get_rate(clk);
402 rem[IN] = do_div(clk_rate, inrate);
403 div[IN] = (u32)clk_rate;
406 * The divider range is [1, 1024], defined by the hardware. For non-
407 * ideal ratio configuration, clock rate has to be strictly aligned
408 * with the sample rate. For ideal ratio configuration, clock rates
409 * only result in different converting speeds. So remainder does not
410 * matter, as long as we keep the divider within its valid range.
412 if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) {
413 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
414 inrate, clk_index[ideal ? OUT : IN]);
418 div[IN] = min_t(u32, 1024, div[IN]);
420 clk = asrc_priv->asrck_clk[clk_index[OUT]];
421 clk_rate = clk_get_rate(clk);
422 if (ideal && use_ideal_rate)
423 rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE);
425 rem[OUT] = do_div(clk_rate, outrate);
428 /* Output divider has the same limitation as the input one */
429 if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) {
430 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
431 outrate, clk_index[OUT]);
435 div[OUT] = min_t(u32, 1024, div[OUT]);
437 /* Set the channel number */
438 channels = config->channel_num;
440 if (asrc_priv->soc->channel_bits < 4)
443 /* Update channels for current pair */
444 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
445 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
446 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
448 /* Default setting: Automatic selection for processing mode */
449 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
450 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
451 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
452 ASRCTR_USRi_MASK(index), 0);
454 /* Set the input and output clock sources */
455 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
456 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
457 ASRCSR_AICS(index, clk_index[IN]) |
458 ASRCSR_AOCS(index, clk_index[OUT]));
460 /* Calculate the input clock divisors */
461 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
462 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
464 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
465 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
466 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
467 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
468 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
470 /* Implement word_width configurations */
471 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
472 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
473 ASRMCR1i_OW16(output_word_width) |
474 ASRMCR1i_IWD(input_word_width));
476 /* Enable BUFFER STALL */
477 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
478 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
480 /* Set default thresholds for input and output FIFO */
481 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
482 ASRC_INPUTFIFO_THRESHOLD);
484 /* Configure the following only for Ideal Ratio mode */
488 /* Clear ASTSx bit to use Ideal Ratio mode */
489 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
490 ASRCTR_ATSi_MASK(index), 0);
492 /* Enable Ideal Ratio mode */
493 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
494 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
495 ASRCTR_IDR(index) | ASRCTR_USR(index));
497 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
499 /* Apply configurations for pre- and post-processing */
500 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
501 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
502 ASRCFG_PREMOD(index, pre_proc) |
503 ASRCFG_POSTMOD(index, post_proc));
505 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
509 * Start the assigned ASRC pair
511 * It enables the assigned pair and makes it stopped at the stall level.
513 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
515 struct fsl_asrc *asrc_priv = pair->asrc_priv;
516 enum asrc_pair_index index = pair->index;
517 int reg, retry = 10, i;
519 /* Enable the current pair */
520 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
521 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
523 /* Wait for status of initialization */
526 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
527 reg &= ASRCFG_INIRQi_MASK(index);
528 } while (!reg && --retry);
530 /* Make the input fifo to ASRC STALL level */
531 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
532 for (i = 0; i < pair->channels * 4; i++)
533 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
535 /* Enable overload interrupt */
536 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
540 * Stop the assigned ASRC pair
542 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
544 struct fsl_asrc *asrc_priv = pair->asrc_priv;
545 enum asrc_pair_index index = pair->index;
547 /* Stop the current pair */
548 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
549 ASRCTR_ASRCEi_MASK(index), 0);
553 * Get DMA channel according to the pair and direction.
555 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
557 struct fsl_asrc *asrc_priv = pair->asrc_priv;
558 enum asrc_pair_index index = pair->index;
561 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
563 return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
565 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
567 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
568 struct snd_soc_dai *dai)
570 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
572 /* Odd channel number is not valid for older ASRC (channel_bits==3) */
573 if (asrc_priv->soc->channel_bits == 3)
574 snd_pcm_hw_constraint_step(substream->runtime, 0,
575 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
578 return snd_pcm_hw_constraint_list(substream->runtime, 0,
579 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
582 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
583 struct snd_pcm_hw_params *params,
584 struct snd_soc_dai *dai)
586 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
587 struct snd_pcm_runtime *runtime = substream->runtime;
588 struct fsl_asrc_pair *pair = runtime->private_data;
589 unsigned int channels = params_channels(params);
590 unsigned int rate = params_rate(params);
591 struct asrc_config config;
592 snd_pcm_format_t format;
595 ret = fsl_asrc_request_pair(channels, pair);
597 dev_err(dai->dev, "fail to request asrc pair\n");
601 pair->config = &config;
603 if (asrc_priv->asrc_width == 16)
604 format = SNDRV_PCM_FORMAT_S16_LE;
606 format = SNDRV_PCM_FORMAT_S24_LE;
608 config.pair = pair->index;
609 config.channel_num = channels;
610 config.inclk = INCLK_NONE;
611 config.outclk = OUTCLK_ASRCK1_CLK;
613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
614 config.input_format = params_format(params);
615 config.output_format = format;
616 config.input_sample_rate = rate;
617 config.output_sample_rate = asrc_priv->asrc_rate;
619 config.input_format = format;
620 config.output_format = params_format(params);
621 config.input_sample_rate = asrc_priv->asrc_rate;
622 config.output_sample_rate = rate;
625 ret = fsl_asrc_config_pair(pair, false);
627 dev_err(dai->dev, "fail to config asrc pair\n");
634 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
635 struct snd_soc_dai *dai)
637 struct snd_pcm_runtime *runtime = substream->runtime;
638 struct fsl_asrc_pair *pair = runtime->private_data;
641 fsl_asrc_release_pair(pair);
646 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
647 struct snd_soc_dai *dai)
649 struct snd_pcm_runtime *runtime = substream->runtime;
650 struct fsl_asrc_pair *pair = runtime->private_data;
653 case SNDRV_PCM_TRIGGER_START:
654 case SNDRV_PCM_TRIGGER_RESUME:
655 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
656 fsl_asrc_start_pair(pair);
658 case SNDRV_PCM_TRIGGER_STOP:
659 case SNDRV_PCM_TRIGGER_SUSPEND:
660 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
661 fsl_asrc_stop_pair(pair);
670 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
671 .startup = fsl_asrc_dai_startup,
672 .hw_params = fsl_asrc_dai_hw_params,
673 .hw_free = fsl_asrc_dai_hw_free,
674 .trigger = fsl_asrc_dai_trigger,
677 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
679 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
681 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
682 &asrc_priv->dma_params_rx);
687 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
688 SNDRV_PCM_FMTBIT_S16_LE | \
689 SNDRV_PCM_FMTBIT_S24_3LE)
691 static struct snd_soc_dai_driver fsl_asrc_dai = {
692 .probe = fsl_asrc_dai_probe,
694 .stream_name = "ASRC-Playback",
699 .rates = SNDRV_PCM_RATE_KNOT,
700 .formats = FSL_ASRC_FORMATS |
704 .stream_name = "ASRC-Capture",
709 .rates = SNDRV_PCM_RATE_KNOT,
710 .formats = FSL_ASRC_FORMATS,
712 .ops = &fsl_asrc_dai_ops,
715 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
759 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
779 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
820 static struct reg_default fsl_asrc_reg[] = {
821 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
822 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
823 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
824 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
825 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
826 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
827 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
828 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
829 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
830 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
831 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
832 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
833 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
834 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
835 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
836 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
837 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
838 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
839 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
840 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
841 { REG_ASRMCR1C, 0x0000 },
844 static const struct regmap_config fsl_asrc_regmap_config = {
849 .max_register = REG_ASRMCR1C,
850 .reg_defaults = fsl_asrc_reg,
851 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
852 .readable_reg = fsl_asrc_readable_reg,
853 .volatile_reg = fsl_asrc_volatile_reg,
854 .writeable_reg = fsl_asrc_writeable_reg,
855 .cache_type = REGCACHE_FLAT,
859 * Initialize ASRC registers with a default configurations
861 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
863 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
864 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
866 /* Disable interrupt by default */
867 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
869 /* Apply recommended settings for parameters from Reference Manual */
870 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
871 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
872 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
873 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
874 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
876 /* Base address for task queue FIFO. Set to 0x7C */
877 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
878 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
880 /* Set the processing clock for 76KHz to 133M */
881 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
883 /* Set the processing clock for 56KHz to 133M */
884 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
888 * Interrupt handler for ASRC
890 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
892 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
893 struct device *dev = &asrc_priv->pdev->dev;
894 enum asrc_pair_index index;
897 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
899 /* Clean overload error */
900 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
903 * We here use dev_dbg() for all exceptions because ASRC itself does
904 * not care if FIFO overflowed or underrun while a warning in the
905 * interrupt would result a ridged conversion.
907 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
908 if (!asrc_priv->pair[index])
911 if (status & ASRSTR_ATQOL) {
912 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
913 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
916 if (status & ASRSTR_AOOL(index)) {
917 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
918 pair_dbg("Output Task Overload\n");
921 if (status & ASRSTR_AIOL(index)) {
922 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
923 pair_dbg("Input Task Overload\n");
926 if (status & ASRSTR_AODO(index)) {
927 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
928 pair_dbg("Output Data Buffer has overflowed\n");
931 if (status & ASRSTR_AIDU(index)) {
932 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
933 pair_dbg("Input Data Buffer has underflowed\n");
940 static int fsl_asrc_probe(struct platform_device *pdev)
942 struct device_node *np = pdev->dev.of_node;
943 struct fsl_asrc *asrc_priv;
944 struct resource *res;
950 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
954 asrc_priv->pdev = pdev;
956 /* Get the addresses and IRQ */
957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
958 regs = devm_ioremap_resource(&pdev->dev, res);
960 return PTR_ERR(regs);
962 asrc_priv->paddr = res->start;
964 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
965 &fsl_asrc_regmap_config);
966 if (IS_ERR(asrc_priv->regmap)) {
967 dev_err(&pdev->dev, "failed to init regmap\n");
968 return PTR_ERR(asrc_priv->regmap);
971 irq = platform_get_irq(pdev, 0);
975 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
976 dev_name(&pdev->dev), asrc_priv);
978 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
982 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
983 if (IS_ERR(asrc_priv->mem_clk)) {
984 dev_err(&pdev->dev, "failed to get mem clock\n");
985 return PTR_ERR(asrc_priv->mem_clk);
988 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
989 if (IS_ERR(asrc_priv->ipg_clk)) {
990 dev_err(&pdev->dev, "failed to get ipg clock\n");
991 return PTR_ERR(asrc_priv->ipg_clk);
994 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
995 if (IS_ERR(asrc_priv->spba_clk))
996 dev_warn(&pdev->dev, "failed to get spba clock\n");
998 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
999 sprintf(tmp, "asrck_%x", i);
1000 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
1001 if (IS_ERR(asrc_priv->asrck_clk[i])) {
1002 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
1003 return PTR_ERR(asrc_priv->asrck_clk[i]);
1007 asrc_priv->soc = of_device_get_match_data(&pdev->dev);
1008 if (!asrc_priv->soc) {
1009 dev_err(&pdev->dev, "failed to get soc data\n");
1013 if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
1014 asrc_priv->clk_map[IN] = input_clk_map_imx35;
1015 asrc_priv->clk_map[OUT] = output_clk_map_imx35;
1016 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
1017 asrc_priv->clk_map[IN] = input_clk_map_imx53;
1018 asrc_priv->clk_map[OUT] = output_clk_map_imx53;
1019 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
1020 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
1021 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
1023 dev_err(&pdev->dev, "failed to get clk map index\n");
1028 dev_err(&pdev->dev, "unsupported clk map index\n");
1031 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
1032 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
1033 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
1035 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
1036 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
1040 ret = fsl_asrc_init(asrc_priv);
1042 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
1046 asrc_priv->channel_avail = 10;
1048 ret = of_property_read_u32(np, "fsl,asrc-rate",
1049 &asrc_priv->asrc_rate);
1051 dev_err(&pdev->dev, "failed to get output rate\n");
1055 ret = of_property_read_u32(np, "fsl,asrc-width",
1056 &asrc_priv->asrc_width);
1058 dev_err(&pdev->dev, "failed to get output width\n");
1062 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
1063 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
1064 asrc_priv->asrc_width = 24;
1067 platform_set_drvdata(pdev, asrc_priv);
1068 pm_runtime_enable(&pdev->dev);
1069 spin_lock_init(&asrc_priv->lock);
1071 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
1074 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
1082 static int fsl_asrc_runtime_resume(struct device *dev)
1084 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1087 ret = clk_prepare_enable(asrc_priv->mem_clk);
1090 ret = clk_prepare_enable(asrc_priv->ipg_clk);
1092 goto disable_mem_clk;
1093 if (!IS_ERR(asrc_priv->spba_clk)) {
1094 ret = clk_prepare_enable(asrc_priv->spba_clk);
1096 goto disable_ipg_clk;
1098 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
1099 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
1101 goto disable_asrck_clk;
1107 for (i--; i >= 0; i--)
1108 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1109 if (!IS_ERR(asrc_priv->spba_clk))
1110 clk_disable_unprepare(asrc_priv->spba_clk);
1112 clk_disable_unprepare(asrc_priv->ipg_clk);
1114 clk_disable_unprepare(asrc_priv->mem_clk);
1118 static int fsl_asrc_runtime_suspend(struct device *dev)
1120 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1123 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
1124 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1125 if (!IS_ERR(asrc_priv->spba_clk))
1126 clk_disable_unprepare(asrc_priv->spba_clk);
1127 clk_disable_unprepare(asrc_priv->ipg_clk);
1128 clk_disable_unprepare(asrc_priv->mem_clk);
1132 #endif /* CONFIG_PM */
1134 #ifdef CONFIG_PM_SLEEP
1135 static int fsl_asrc_suspend(struct device *dev)
1137 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1139 regmap_read(asrc_priv->regmap, REG_ASRCFG,
1140 &asrc_priv->regcache_cfg);
1142 regcache_cache_only(asrc_priv->regmap, true);
1143 regcache_mark_dirty(asrc_priv->regmap);
1148 static int fsl_asrc_resume(struct device *dev)
1150 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1153 /* Stop all pairs provisionally */
1154 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
1155 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1156 ASRCTR_ASRCEi_ALL_MASK, 0);
1158 /* Restore all registers */
1159 regcache_cache_only(asrc_priv->regmap, false);
1160 regcache_sync(asrc_priv->regmap);
1162 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1163 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1164 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1166 /* Restart enabled pairs */
1167 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1168 ASRCTR_ASRCEi_ALL_MASK, asrctr);
1172 #endif /* CONFIG_PM_SLEEP */
1174 static const struct dev_pm_ops fsl_asrc_pm = {
1175 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1176 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1179 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
1184 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
1189 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
1194 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
1199 static const struct of_device_id fsl_asrc_ids[] = {
1200 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
1201 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
1202 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
1203 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
1206 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1208 static struct platform_driver fsl_asrc_driver = {
1209 .probe = fsl_asrc_probe,
1212 .of_match_table = fsl_asrc_ids,
1216 module_platform_driver(fsl_asrc_driver);
1218 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1219 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1220 MODULE_ALIAS("platform:fsl-asrc");
1221 MODULE_LICENSE("GPL v2");