2 * bxt-sst.c - DSP library functions for BXT platform
4 * Copyright (C) 2015-16 Intel Corp
5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
6 * Jeeja KP <jeeja.kp@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/device.h>
23 #include "../common/sst-dsp.h"
24 #include "../common/sst-dsp-priv.h"
25 #include "skl-sst-ipc.h"
27 #define BXT_BASEFW_TIMEOUT 3000
28 #define BXT_INIT_TIMEOUT 300
29 #define BXT_ROM_INIT_TIMEOUT 70
30 #define BXT_IPC_PURGE_FW 0x01004000
32 #define BXT_ROM_INIT 0x5
33 #define BXT_ADSP_SRAM0_BASE 0x80000
35 /* Firmware status window */
36 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
37 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
39 #define BXT_ADSP_SRAM1_BASE 0xA0000
41 #define BXT_INSTANCE_ID 0
42 #define BXT_BASE_FW_MODULE_ID 0
44 #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
46 /* Delay before scheduling D0i3 entry */
47 #define BXT_D0I3_DELAY 5000
49 #define BXT_FW_ROM_INIT_RETRY 3
51 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
53 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
56 static void sst_bxt_release_library(struct skl_lib_info *linfo, int lib_count)
60 for (i = 1; i < lib_count; i++) {
62 release_firmware(linfo[i].fw);
69 bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
71 struct snd_dma_buffer dmab;
72 struct skl_sst *skl = ctx->thread_context;
73 struct firmware stripped_fw;
74 int ret = 0, i, dma_id, stream_tag;
76 /* library indices start from 1 to N. 0 represents base FW */
77 for (i = 1; i < lib_count; i++) {
78 if (linfo[i].fw == NULL) {
79 ret = request_firmware(&linfo[i].fw, linfo[i].name,
82 dev_err(ctx->dev, "Request lib %s failed:%d\n",
84 goto load_library_failed;
88 if (skl->is_first_boot) {
89 ret = snd_skl_parse_uuids(ctx, linfo[i].fw,
90 BXT_ADSP_FW_BIN_HDR_OFFSET, i);
92 goto load_library_failed;
95 stripped_fw.data = linfo[i].fw->data;
96 stripped_fw.size = linfo[i].fw->size;
97 skl_dsp_strip_extended_manifest(&stripped_fw);
99 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
100 stripped_fw.size, &dmab);
101 if (stream_tag <= 0) {
102 dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
105 goto load_library_failed;
108 dma_id = stream_tag - 1;
109 memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
111 ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
112 ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i);
114 dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
117 ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
118 ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
124 sst_bxt_release_library(linfo, lib_count);
129 * First boot sequence has some extra steps. Core 0 waits for power
130 * status on core 1, so power up core 1 also momentarily, keep it in
131 * reset/stall and then turn it off
133 static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
134 const void *fwdata, u32 fwsize)
138 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
139 if (stream_tag <= 0) {
140 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
145 ctx->dsp_ops.stream_tag = stream_tag;
146 memcpy(ctx->dmab.area, fwdata, fwsize);
148 /* Step 1: Power up core 0 and core1 */
149 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
150 SKL_DSP_CORE_MASK(1));
152 dev_err(ctx->dev, "dsp core0/1 power up failed\n");
153 goto base_fw_load_failed;
156 /* Step 2: Purge FW request */
157 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
158 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
160 /* Step 3: Unset core0 reset state & unstall/run core0 */
161 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
163 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
165 goto base_fw_load_failed;
168 /* Step 4: Wait for DONE Bit */
169 ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
170 SKL_ADSP_REG_HIPCIE_DONE,
171 SKL_ADSP_REG_HIPCIE_DONE,
172 BXT_INIT_TIMEOUT, "HIPCIE Done");
174 dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
175 goto base_fw_load_failed;
178 /* Step 5: power down core1 */
179 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
181 dev_err(ctx->dev, "dsp core1 power down failed\n");
182 goto base_fw_load_failed;
185 /* Step 6: Enable Interrupt */
186 skl_ipc_int_enable(ctx);
187 skl_ipc_op_int_enable(ctx);
189 /* Step 7: Wait for ROM init */
190 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
191 SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
193 dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
194 goto base_fw_load_failed;
200 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
201 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
202 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
206 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
210 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
211 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
212 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
214 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
215 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
220 static int bxt_load_base_firmware(struct sst_dsp *ctx)
222 struct firmware stripped_fw;
223 struct skl_sst *skl = ctx->thread_context;
226 if (ctx->fw == NULL) {
227 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
229 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
234 /* prase uuids on first boot */
235 if (skl->is_first_boot) {
236 ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
238 goto sst_load_base_firmware_failed;
241 stripped_fw.data = ctx->fw->data;
242 stripped_fw.size = ctx->fw->size;
243 skl_dsp_strip_extended_manifest(&stripped_fw);
246 for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
247 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
253 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
254 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
255 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
257 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
258 goto sst_load_base_firmware_failed;
261 ret = sst_transfer_fw_host_dma(ctx);
263 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
264 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
265 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
266 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
268 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
270 dev_dbg(ctx->dev, "Firmware download successful\n");
271 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
272 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
274 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
275 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
279 skl->fw_loaded = true;
285 sst_load_base_firmware_failed:
286 release_firmware(ctx->fw);
292 * Decide the D0i3 state that can be targeted based on the usecase
293 * ref counts and DSP state
295 * Decision Matrix: (X= dont care; state = target state)
297 * DSP state != SKL_DSP_RUNNING ; state = no d0i3
299 * DSP state == SKL_DSP_RUNNING , the following matrix applies
300 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
301 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
302 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
303 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
305 static int bxt_d0i3_target_state(struct sst_dsp *ctx)
307 struct skl_sst *skl = ctx->thread_context;
308 struct skl_d0i3_data *d0i3 = &skl->d0i3;
310 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
311 return SKL_DSP_D0I3_NONE;
314 return SKL_DSP_D0I3_NONE;
315 else if (d0i3->streaming)
316 return SKL_DSP_D0I3_STREAMING;
317 else if (d0i3->non_streaming)
318 return SKL_DSP_D0I3_NON_STREAMING;
320 return SKL_DSP_D0I3_NONE;
323 static void bxt_set_dsp_D0i3(struct work_struct *work)
326 struct skl_ipc_d0ix_msg msg;
327 struct skl_sst *skl = container_of(work,
328 struct skl_sst, d0i3.work.work);
329 struct sst_dsp *ctx = skl->dsp;
330 struct skl_d0i3_data *d0i3 = &skl->d0i3;
333 dev_dbg(ctx->dev, "In %s:\n", __func__);
335 /* D0i3 entry allowed only if core 0 alone is running */
336 if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
338 "D0i3 allowed when only core0 running:Exit\n");
342 target_state = bxt_d0i3_target_state(ctx);
343 if (target_state == SKL_DSP_D0I3_NONE)
350 if (target_state == SKL_DSP_D0I3_STREAMING)
353 ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
356 dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
360 /* Set Vendor specific register D0I3C.I3 to enable D0i3*/
361 if (skl->update_d0i3c)
362 skl->update_d0i3c(skl->dev, true);
364 d0i3->state = target_state;
365 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
368 static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
370 struct skl_sst *skl = ctx->thread_context;
371 struct skl_d0i3_data *d0i3 = &skl->d0i3;
373 /* Schedule D0i3 only if the usecase ref counts are appropriate */
374 if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
376 dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
378 schedule_delayed_work(&d0i3->work,
379 msecs_to_jiffies(BXT_D0I3_DELAY));
385 static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
388 struct skl_ipc_d0ix_msg msg;
389 struct skl_sst *skl = ctx->thread_context;
391 dev_dbg(ctx->dev, "In %s:\n", __func__);
393 /* First Cancel any pending attempt to put DSP to D0i3 */
394 cancel_delayed_work_sync(&skl->d0i3.work);
396 /* If DSP is currently in D0i3, bring it to D0i0 */
397 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
400 dev_dbg(ctx->dev, "Set DSP to D0i0\n");
407 if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
410 /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
411 if (skl->update_d0i3c)
412 skl->update_d0i3c(skl->dev, false);
414 ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
416 dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
420 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
421 skl->d0i3.state = SKL_DSP_D0I3_NONE;
426 static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
428 struct skl_sst *skl = ctx->thread_context;
430 struct skl_ipc_dxstate_info dx;
431 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
433 if (skl->fw_loaded == false) {
434 skl->boot_complete = false;
435 ret = bxt_load_base_firmware(ctx);
437 dev_err(ctx->dev, "reload fw failed: %d\n", ret);
441 if (skl->lib_count > 1) {
442 ret = bxt_load_library(ctx, skl->lib_info,
445 dev_err(ctx->dev, "reload libs failed: %d\n", ret);
449 skl->cores.state[core_id] = SKL_DSP_RUNNING;
453 /* If core 0 is being turned on, turn on core 1 as well */
454 if (core_id == SKL_DSP_CORE0_ID)
455 ret = skl_dsp_core_power_up(ctx, core_mask |
456 SKL_DSP_CORE_MASK(1));
458 ret = skl_dsp_core_power_up(ctx, core_mask);
463 if (core_id == SKL_DSP_CORE0_ID) {
466 * Enable interrupt after SPA is set and before
469 skl_ipc_int_enable(ctx);
470 skl_ipc_op_int_enable(ctx);
471 skl->boot_complete = false;
474 ret = skl_dsp_start_core(ctx, core_mask);
478 if (core_id == SKL_DSP_CORE0_ID) {
479 ret = wait_event_timeout(skl->boot_wait,
481 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
483 /* If core 1 was turned on for booting core 0, turn it off */
484 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
486 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
487 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
488 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
489 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
490 dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
496 /* Tell FW if additional core in now On */
498 if (core_id != SKL_DSP_CORE0_ID) {
499 dx.core_mask = core_mask;
500 dx.dx_mask = core_mask;
502 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
503 BXT_BASE_FW_MODULE_ID, &dx);
505 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
511 skl->cores.state[core_id] = SKL_DSP_RUNNING;
514 if (core_id == SKL_DSP_CORE0_ID)
515 core_mask |= SKL_DSP_CORE_MASK(1);
516 skl_dsp_disable_core(ctx, core_mask);
521 static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
524 struct skl_ipc_dxstate_info dx;
525 struct skl_sst *skl = ctx->thread_context;
526 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
528 dx.core_mask = core_mask;
529 dx.dx_mask = SKL_IPC_D3_MASK;
531 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
532 dx.core_mask, dx.dx_mask);
534 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
535 BXT_BASE_FW_MODULE_ID, &dx);
538 "Failed to set DSP to D3:core id = %d;Continue reset\n",
541 * In case of D3 failure, re-download the firmware, so set
542 * fw_loaded to false.
544 skl->fw_loaded = false;
547 if (core_id == SKL_DSP_CORE0_ID) {
548 /* disable Interrupt */
549 skl_ipc_op_int_disable(ctx);
550 skl_ipc_int_disable(ctx);
552 ret = skl_dsp_disable_core(ctx, core_mask);
554 dev_err(ctx->dev, "Failed to disable core %d\n", ret);
557 skl->cores.state[core_id] = SKL_DSP_RESET;
561 static struct skl_dsp_fw_ops bxt_fw_ops = {
562 .set_state_D0 = bxt_set_dsp_D0,
563 .set_state_D3 = bxt_set_dsp_D3,
564 .set_state_D0i3 = bxt_schedule_dsp_D0i3,
565 .set_state_D0i0 = bxt_set_dsp_D0i0,
566 .load_fw = bxt_load_base_firmware,
567 .get_fw_errcode = bxt_get_errorcode,
568 .load_library = bxt_load_library,
571 static struct sst_ops skl_ops = {
572 .irq_handler = skl_dsp_sst_interrupt,
573 .write = sst_shim32_write,
574 .read = sst_shim32_read,
575 .ram_read = sst_memcpy_fromio_32,
576 .ram_write = sst_memcpy_toio_32,
577 .free = skl_dsp_free,
580 static struct sst_dsp_device skl_dev = {
581 .thread = skl_dsp_irq_thread_handler,
585 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
586 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
587 struct skl_sst **dsp)
593 ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
595 dev_err(skl->dev, "%s: no device\n", __func__);
601 sst->fw_ops = bxt_fw_ops;
602 sst->addr.lpe = mmio_base;
603 sst->addr.shim = mmio_base;
605 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
606 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
608 /* set the D0i3 check */
609 skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
611 skl->cores.count = 2;
612 skl->boot_complete = false;
613 init_waitqueue_head(&skl->boot_wait);
614 INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
615 skl->d0i3.state = SKL_DSP_D0I3_NONE;
619 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
621 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx)
624 struct sst_dsp *sst = ctx->dsp;
626 ret = sst->fw_ops.load_fw(sst);
628 dev_err(dev, "Load base fw failed: %x\n", ret);
632 skl_dsp_init_core_state(sst);
634 if (ctx->lib_count > 1) {
635 ret = sst->fw_ops.load_library(sst, ctx->lib_info,
638 dev_err(dev, "Load Library failed : %x\n", ret);
642 ctx->is_first_boot = false;
646 EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
648 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
651 sst_bxt_release_library(ctx->lib_info, ctx->lib_count);
653 release_firmware(ctx->dsp->fw);
654 skl_freeup_uuid_list(ctx);
655 skl_ipc_free(&ctx->ipc);
656 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
658 if (ctx->dsp->addr.lpe)
659 iounmap(ctx->dsp->addr.lpe);
661 ctx->dsp->ops->free(ctx->dsp);
663 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
665 MODULE_LICENSE("GPL v2");
666 MODULE_DESCRIPTION("Intel Broxton IPC driver");