2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
23 #include <linux/pxa2xx_ssp.h>
25 #include <linux/dmaengine.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
37 #include "../../arm/pxa2xx-pcm.h"
41 * SSP audio private data
44 struct ssp_device *ssp;
47 unsigned int configured_dai_fmt;
56 static void dump_registers(struct ssp_device *ssp)
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
59 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
60 pxa_ssp_read_reg(ssp, SSTO));
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
63 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
64 pxa_ssp_read_reg(ssp, SSACD));
67 static void pxa_ssp_enable(struct ssp_device *ssp)
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
75 static void pxa_ssp_disable(struct ssp_device *ssp)
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
83 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
84 int out, struct snd_dmaengine_dai_dma_data *dma)
86 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
87 DMA_SLAVE_BUSWIDTH_2_BYTES;
89 dma->addr = ssp->phys_base + SSDR;
92 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
93 struct snd_soc_dai *cpu_dai)
95 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
96 struct ssp_device *ssp = priv->ssp;
97 struct snd_dmaengine_dai_dma_data *dma;
100 if (!cpu_dai->active) {
101 clk_prepare_enable(ssp->clk);
102 pxa_ssp_disable(ssp);
105 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
109 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
110 &ssp->drcmr_tx : &ssp->drcmr_rx;
112 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
117 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
118 struct snd_soc_dai *cpu_dai)
120 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
121 struct ssp_device *ssp = priv->ssp;
123 if (!cpu_dai->active) {
124 pxa_ssp_disable(ssp);
125 clk_disable_unprepare(ssp->clk);
128 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
129 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
134 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
136 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
137 struct ssp_device *ssp = priv->ssp;
139 if (!cpu_dai->active)
140 clk_prepare_enable(ssp->clk);
142 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
143 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
144 priv->to = __raw_readl(ssp->mmio_base + SSTO);
145 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
147 pxa_ssp_disable(ssp);
148 clk_disable_unprepare(ssp->clk);
152 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
154 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
155 struct ssp_device *ssp = priv->ssp;
156 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
158 clk_prepare_enable(ssp->clk);
160 __raw_writel(sssr, ssp->mmio_base + SSSR);
161 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
162 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
163 __raw_writel(priv->to, ssp->mmio_base + SSTO);
164 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
169 clk_disable_unprepare(ssp->clk);
175 #define pxa_ssp_suspend NULL
176 #define pxa_ssp_resume NULL
180 * ssp_set_clkdiv - set SSP clock divider
181 * @div: serial clock rate divider
183 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
185 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
187 if (ssp->type == PXA25x_SSP) {
188 sscr0 &= ~0x0000ff00;
189 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
191 sscr0 &= ~0x000fff00;
192 sscr0 |= (div - 1) << 8; /* 1..4096 */
194 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
198 * pxa_ssp_get_clkdiv - get SSP clock divider
200 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
202 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
205 if (ssp->type == PXA25x_SSP)
206 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
208 div = ((sscr0 >> 8) & 0xfff) + 1;
213 * Set the SSP ports SYSCLK.
215 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
216 int clk_id, unsigned int freq, int dir)
218 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
219 struct ssp_device *ssp = priv->ssp;
221 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
222 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
224 dev_dbg(&ssp->pdev->dev,
225 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
226 cpu_dai->id, clk_id, freq);
229 case PXA_SSP_CLK_NET_PLL:
232 case PXA_SSP_CLK_PLL:
233 /* Internal PLL is fixed */
234 if (ssp->type == PXA25x_SSP)
235 priv->sysclk = 1843200;
237 priv->sysclk = 13000000;
239 case PXA_SSP_CLK_EXT:
243 case PXA_SSP_CLK_NET:
245 sscr0 |= SSCR0_NCS | SSCR0_MOD;
247 case PXA_SSP_CLK_AUDIO:
249 pxa_ssp_set_scr(ssp, 1);
256 /* The SSP clock must be disabled when changing SSP clock mode
257 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
258 if (ssp->type != PXA3xx_SSP)
259 clk_disable_unprepare(ssp->clk);
260 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
261 if (ssp->type != PXA3xx_SSP)
262 clk_prepare_enable(ssp->clk);
268 * Set the SSP clock dividers.
270 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
273 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
274 struct ssp_device *ssp = priv->ssp;
278 case PXA_SSP_AUDIO_DIV_ACDS:
279 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
280 pxa_ssp_write_reg(ssp, SSACD, val);
282 case PXA_SSP_AUDIO_DIV_SCDB:
283 val = pxa_ssp_read_reg(ssp, SSACD);
285 if (ssp->type == PXA3xx_SSP)
288 case PXA_SSP_CLK_SCDB_1:
291 case PXA_SSP_CLK_SCDB_4:
293 case PXA_SSP_CLK_SCDB_8:
294 if (ssp->type == PXA3xx_SSP)
302 pxa_ssp_write_reg(ssp, SSACD, val);
304 case PXA_SSP_DIV_SCR:
305 pxa_ssp_set_scr(ssp, div);
315 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
317 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
318 int source, unsigned int freq_in, unsigned int freq_out)
320 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
321 struct ssp_device *ssp = priv->ssp;
322 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
324 if (ssp->type == PXA3xx_SSP)
325 pxa_ssp_write_reg(ssp, SSACDD, 0);
350 /* PXA3xx has a clock ditherer which can be used to generate
351 * a wider range of frequencies - calculate a value for it.
353 if (ssp->type == PXA3xx_SSP) {
358 do_div(tmp, freq_out);
361 val = (val << 16) | 64;
362 pxa_ssp_write_reg(ssp, SSACDD, val);
366 dev_dbg(&ssp->pdev->dev,
367 "Using SSACDD %x to supply %uHz\n",
375 pxa_ssp_write_reg(ssp, SSACD, ssacd);
381 * Set the active slots in TDM/Network mode
383 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
384 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
386 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
387 struct ssp_device *ssp = priv->ssp;
390 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
391 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
395 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
397 sscr0 |= SSCR0_DataSize(slot_width);
400 /* enable network mode */
403 /* set number of active slots */
404 sscr0 |= SSCR0_SlotsPerFrm(slots);
406 /* set active slot mask */
407 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
408 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
410 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
416 * Tristate the SSP DAI lines
418 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
421 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
422 struct ssp_device *ssp = priv->ssp;
425 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
430 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
435 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
438 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
441 case SND_SOC_DAIFMT_CBM_CFM:
442 case SND_SOC_DAIFMT_CBM_CFS:
443 case SND_SOC_DAIFMT_CBS_CFS:
449 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
450 case SND_SOC_DAIFMT_NB_NF:
451 case SND_SOC_DAIFMT_NB_IF:
452 case SND_SOC_DAIFMT_IB_IF:
453 case SND_SOC_DAIFMT_IB_NF:
459 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
460 case SND_SOC_DAIFMT_I2S:
461 case SND_SOC_DAIFMT_DSP_A:
462 case SND_SOC_DAIFMT_DSP_B:
469 /* Settings will be applied in hw_params() */
476 * Set up the SSP DAI format.
477 * The SSP Port must be inactive before calling this function as the
478 * physical interface format is changed.
480 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
482 struct ssp_device *ssp = priv->ssp;
483 u32 sscr0, sscr1, sspsp, scfr;
485 /* check if we need to change anything at all */
486 if (priv->configured_dai_fmt == priv->dai_fmt)
489 /* reset port settings */
490 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
491 ~(SSCR0_PSP | SSCR0_MOD);
492 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
493 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
494 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
495 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
496 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
498 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
500 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
501 case SND_SOC_DAIFMT_CBM_CFM:
502 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
504 case SND_SOC_DAIFMT_CBM_CFS:
505 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
507 case SND_SOC_DAIFMT_CBS_CFS:
513 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
514 case SND_SOC_DAIFMT_NB_NF:
515 sspsp |= SSPSP_SFRMP;
517 case SND_SOC_DAIFMT_NB_IF:
519 case SND_SOC_DAIFMT_IB_IF:
520 sspsp |= SSPSP_SCMODE(2);
522 case SND_SOC_DAIFMT_IB_NF:
523 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
529 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
530 case SND_SOC_DAIFMT_I2S:
532 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
533 /* See hw_params() */
536 case SND_SOC_DAIFMT_DSP_A:
538 case SND_SOC_DAIFMT_DSP_B:
539 sscr0 |= SSCR0_MOD | SSCR0_PSP;
540 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
547 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
548 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
549 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
551 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
552 case SND_SOC_DAIFMT_CBM_CFM:
553 case SND_SOC_DAIFMT_CBM_CFS:
554 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
555 pxa_ssp_write_reg(ssp, SSCR1, scfr);
557 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
564 /* Since we are configuring the timings for the format by hand
565 * we have to defer some things until hw_params() where we
566 * know parameters like the sample size.
568 priv->configured_dai_fmt = priv->dai_fmt;
574 * Set the SSP audio DMA parameters and sample size.
575 * Can be called multiple times by oss emulation.
577 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
578 struct snd_pcm_hw_params *params,
579 struct snd_soc_dai *cpu_dai)
581 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
582 struct ssp_device *ssp = priv->ssp;
583 int chn = params_channels(params);
586 int width = snd_pcm_format_physical_width(params_format(params));
587 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
588 struct snd_dmaengine_dai_dma_data *dma_data;
591 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
593 /* Network mode with one active slot (ttsa == 1) can be used
594 * to force 16-bit frame width on the wire (for S16_LE), even
595 * with two channels. Use 16-bit DMA transfers for this case.
597 pxa_ssp_set_dma_params(ssp,
598 ((chn == 2) && (ttsa != 1)) || (width == 32),
599 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
601 /* we can only change the settings if the port is not in use */
602 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
605 ret = pxa_ssp_configure_dai_fmt(priv);
609 /* clear selected SSP bits */
610 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
613 switch (params_format(params)) {
614 case SNDRV_PCM_FORMAT_S16_LE:
615 if (ssp->type == PXA3xx_SSP)
616 sscr0 |= SSCR0_FPCKE;
617 sscr0 |= SSCR0_DataSize(16);
619 case SNDRV_PCM_FORMAT_S24_LE:
620 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
622 case SNDRV_PCM_FORMAT_S32_LE:
623 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
626 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
628 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
629 case SND_SOC_DAIFMT_I2S:
630 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
632 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
633 /* This is a special case where the bitclk is 64fs
634 * and we're not dealing with 2*32 bits of audio
637 * The SSP values used for that are all found out by
638 * trying and failing a lot; some of the registers
639 * needed for that mode are only available on PXA3xx.
641 if (ssp->type != PXA3xx_SSP)
644 sspsp |= SSPSP_SFRMWDTH(width * 2);
645 sspsp |= SSPSP_SFRMDLY(width * 4);
646 sspsp |= SSPSP_EDMYSTOP(3);
647 sspsp |= SSPSP_DMYSTOP(3);
648 sspsp |= SSPSP_DMYSTRT(1);
650 /* The frame width is the width the LRCLK is
651 * asserted for; the delay is expressed in
652 * half cycle units. We need the extra cycle
653 * because the data starts clocking out one BCLK
654 * after LRCLK changes polarity.
656 sspsp |= SSPSP_SFRMWDTH(width + 1);
657 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
658 sspsp |= SSPSP_DMYSTRT(1);
661 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
667 /* When we use a network mode, we always require TDM slots
668 * - complain loudly and fail if they've not been set up yet.
670 if ((sscr0 & SSCR0_MOD) && !ttsa) {
671 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
680 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
681 struct ssp_device *ssp, int value)
683 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
684 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
685 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
686 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
688 if (value && (sscr0 & SSCR0_SSE))
689 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
691 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
695 sscr1 &= ~SSCR1_TSRE;
700 sscr1 &= ~SSCR1_RSRE;
703 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
706 pxa_ssp_write_reg(ssp, SSSR, sssr);
707 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
708 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
712 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
713 struct snd_soc_dai *cpu_dai)
716 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
717 struct ssp_device *ssp = priv->ssp;
721 case SNDRV_PCM_TRIGGER_RESUME:
724 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
725 pxa_ssp_set_running_bit(substream, ssp, 1);
726 val = pxa_ssp_read_reg(ssp, SSSR);
727 pxa_ssp_write_reg(ssp, SSSR, val);
729 case SNDRV_PCM_TRIGGER_START:
730 pxa_ssp_set_running_bit(substream, ssp, 1);
732 case SNDRV_PCM_TRIGGER_STOP:
733 pxa_ssp_set_running_bit(substream, ssp, 0);
735 case SNDRV_PCM_TRIGGER_SUSPEND:
736 pxa_ssp_disable(ssp);
738 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
739 pxa_ssp_set_running_bit(substream, ssp, 0);
751 static int pxa_ssp_probe(struct snd_soc_dai *dai)
753 struct device *dev = dai->dev;
754 struct ssp_priv *priv;
757 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
762 struct device_node *ssp_handle;
764 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
766 dev_err(dev, "unable to get 'port' phandle\n");
771 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
772 if (priv->ssp == NULL) {
777 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
778 if (priv->ssp == NULL) {
784 priv->dai_fmt = (unsigned int) -1;
785 snd_soc_dai_set_drvdata(dai, priv);
794 static int pxa_ssp_remove(struct snd_soc_dai *dai)
796 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
798 pxa_ssp_free(priv->ssp);
803 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
804 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
805 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
806 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
807 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
809 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
811 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
812 .startup = pxa_ssp_startup,
813 .shutdown = pxa_ssp_shutdown,
814 .trigger = pxa_ssp_trigger,
815 .hw_params = pxa_ssp_hw_params,
816 .set_sysclk = pxa_ssp_set_dai_sysclk,
817 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
818 .set_pll = pxa_ssp_set_dai_pll,
819 .set_fmt = pxa_ssp_set_dai_fmt,
820 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
821 .set_tristate = pxa_ssp_set_dai_tristate,
824 static struct snd_soc_dai_driver pxa_ssp_dai = {
825 .probe = pxa_ssp_probe,
826 .remove = pxa_ssp_remove,
827 .suspend = pxa_ssp_suspend,
828 .resume = pxa_ssp_resume,
832 .rates = PXA_SSP_RATES,
833 .formats = PXA_SSP_FORMATS,
838 .rates = PXA_SSP_RATES,
839 .formats = PXA_SSP_FORMATS,
841 .ops = &pxa_ssp_dai_ops,
844 static const struct snd_soc_component_driver pxa_ssp_component = {
849 static const struct of_device_id pxa_ssp_of_ids[] = {
850 { .compatible = "mrvl,pxa-ssp-dai" },
853 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
856 static int asoc_ssp_probe(struct platform_device *pdev)
858 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
862 static struct platform_driver asoc_ssp_driver = {
864 .name = "pxa-ssp-dai",
865 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
868 .probe = asoc_ssp_probe,
871 module_platform_driver(asoc_ssp_driver);
873 /* Module information */
874 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
875 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
876 MODULE_LICENSE("GPL");
877 MODULE_ALIAS("platform:pxa-ssp-dai");