1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_device.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
24 #include "rockchip_i2s.h"
26 #define DRV_NAME "rockchip-i2s"
39 struct snd_dmaengine_dai_dma_data capture_dma_data;
40 struct snd_dmaengine_dai_dma_data playback_dma_data;
42 struct regmap *regmap;
46 * Used to indicate the tx/rx status.
47 * I2S controller hopes to start the tx and rx together,
48 * also to stop them when they are both try to stop.
53 const struct rk_i2s_pins *pins;
56 static int i2s_runtime_suspend(struct device *dev)
58 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
60 regcache_cache_only(i2s->regmap, true);
61 clk_disable_unprepare(i2s->mclk);
66 static int i2s_runtime_resume(struct device *dev)
68 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
71 ret = clk_prepare_enable(i2s->mclk);
73 dev_err(i2s->dev, "clock enable failed %d\n", ret);
77 regcache_cache_only(i2s->regmap, false);
78 regcache_mark_dirty(i2s->regmap);
80 ret = regcache_sync(i2s->regmap);
82 clk_disable_unprepare(i2s->mclk);
87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
89 return snd_soc_dai_get_drvdata(dai);
92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
98 regmap_update_bits(i2s->regmap, I2S_DMACR,
99 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
101 regmap_update_bits(i2s->regmap, I2S_XFER,
102 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
103 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
105 i2s->tx_start = true;
107 i2s->tx_start = false;
109 regmap_update_bits(i2s->regmap, I2S_DMACR,
110 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
112 if (!i2s->rx_start) {
113 regmap_update_bits(i2s->regmap, I2S_XFER,
119 regmap_update_bits(i2s->regmap, I2S_CLR,
120 I2S_CLR_TXC | I2S_CLR_RXC,
121 I2S_CLR_TXC | I2S_CLR_RXC);
123 regmap_read(i2s->regmap, I2S_CLR, &val);
125 /* Should wait for clear operation to finish */
127 regmap_read(i2s->regmap, I2S_CLR, &val);
130 dev_warn(i2s->dev, "fail to clear\n");
138 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
140 unsigned int val = 0;
144 regmap_update_bits(i2s->regmap, I2S_DMACR,
145 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
147 regmap_update_bits(i2s->regmap, I2S_XFER,
148 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
149 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
151 i2s->rx_start = true;
153 i2s->rx_start = false;
155 regmap_update_bits(i2s->regmap, I2S_DMACR,
156 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
158 if (!i2s->tx_start) {
159 regmap_update_bits(i2s->regmap, I2S_XFER,
165 regmap_update_bits(i2s->regmap, I2S_CLR,
166 I2S_CLR_TXC | I2S_CLR_RXC,
167 I2S_CLR_TXC | I2S_CLR_RXC);
169 regmap_read(i2s->regmap, I2S_CLR, &val);
171 /* Should wait for clear operation to finish */
173 regmap_read(i2s->regmap, I2S_CLR, &val);
176 dev_warn(i2s->dev, "fail to clear\n");
184 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
187 struct rk_i2s_dev *i2s = to_info(cpu_dai);
188 unsigned int mask = 0, val = 0;
190 mask = I2S_CKR_MSS_MASK;
191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
192 case SND_SOC_DAIFMT_CBS_CFS:
193 /* Set source clock in Master mode */
194 val = I2S_CKR_MSS_MASTER;
195 i2s->is_master_mode = true;
197 case SND_SOC_DAIFMT_CBM_CFM:
198 val = I2S_CKR_MSS_SLAVE;
199 i2s->is_master_mode = false;
205 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
207 mask = I2S_TXCR_IBM_MASK;
208 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
209 case SND_SOC_DAIFMT_RIGHT_J:
210 val = I2S_TXCR_IBM_RSJM;
212 case SND_SOC_DAIFMT_LEFT_J:
213 val = I2S_TXCR_IBM_LSJM;
215 case SND_SOC_DAIFMT_I2S:
216 val = I2S_TXCR_IBM_NORMAL;
222 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
224 mask = I2S_RXCR_IBM_MASK;
225 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
226 case SND_SOC_DAIFMT_RIGHT_J:
227 val = I2S_RXCR_IBM_RSJM;
229 case SND_SOC_DAIFMT_LEFT_J:
230 val = I2S_RXCR_IBM_LSJM;
232 case SND_SOC_DAIFMT_I2S:
233 val = I2S_RXCR_IBM_NORMAL;
239 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
244 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
245 struct snd_pcm_hw_params *params,
246 struct snd_soc_dai *dai)
248 struct rk_i2s_dev *i2s = to_info(dai);
249 struct snd_soc_pcm_runtime *rtd = substream->private_data;
250 unsigned int val = 0;
251 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
253 if (i2s->is_master_mode) {
254 mclk_rate = clk_get_rate(i2s->mclk);
255 bclk_rate = 2 * 32 * params_rate(params);
256 if (bclk_rate && mclk_rate % bclk_rate)
259 div_bclk = mclk_rate / bclk_rate;
260 div_lrck = bclk_rate / params_rate(params);
261 regmap_update_bits(i2s->regmap, I2S_CKR,
263 I2S_CKR_MDIV(div_bclk));
265 regmap_update_bits(i2s->regmap, I2S_CKR,
268 I2S_CKR_TSD(div_lrck) |
269 I2S_CKR_RSD(div_lrck));
272 switch (params_format(params)) {
273 case SNDRV_PCM_FORMAT_S8:
274 val |= I2S_TXCR_VDW(8);
276 case SNDRV_PCM_FORMAT_S16_LE:
277 val |= I2S_TXCR_VDW(16);
279 case SNDRV_PCM_FORMAT_S20_3LE:
280 val |= I2S_TXCR_VDW(20);
282 case SNDRV_PCM_FORMAT_S24_LE:
283 val |= I2S_TXCR_VDW(24);
285 case SNDRV_PCM_FORMAT_S32_LE:
286 val |= I2S_TXCR_VDW(32);
292 switch (params_channels(params)) {
306 dev_err(i2s->dev, "invalid channel: %d\n",
307 params_channels(params));
311 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
312 regmap_update_bits(i2s->regmap, I2S_RXCR,
313 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
316 regmap_update_bits(i2s->regmap, I2S_TXCR,
317 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
320 if (!IS_ERR(i2s->grf) && i2s->pins) {
321 regmap_read(i2s->regmap, I2S_TXCR, &val);
322 val &= I2S_TXCR_CSR_MASK;
326 val = I2S_IO_4CH_OUT_6CH_IN;
329 val = I2S_IO_6CH_OUT_4CH_IN;
332 val = I2S_IO_8CH_OUT_2CH_IN;
335 val = I2S_IO_2CH_OUT_8CH_IN;
339 val <<= i2s->pins->shift;
340 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
341 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
344 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
346 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
349 val = I2S_CKR_TRCM_TXRX;
350 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
351 val = I2S_CKR_TRCM_TXONLY;
353 regmap_update_bits(i2s->regmap, I2S_CKR,
359 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
360 int cmd, struct snd_soc_dai *dai)
362 struct rk_i2s_dev *i2s = to_info(dai);
366 case SNDRV_PCM_TRIGGER_START:
367 case SNDRV_PCM_TRIGGER_RESUME:
368 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
369 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
370 rockchip_snd_rxctrl(i2s, 1);
372 rockchip_snd_txctrl(i2s, 1);
374 case SNDRV_PCM_TRIGGER_SUSPEND:
375 case SNDRV_PCM_TRIGGER_STOP:
376 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
377 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
378 rockchip_snd_rxctrl(i2s, 0);
380 rockchip_snd_txctrl(i2s, 0);
390 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
391 unsigned int freq, int dir)
393 struct rk_i2s_dev *i2s = to_info(cpu_dai);
396 ret = clk_set_rate(i2s->mclk, freq);
398 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
403 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
405 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
407 dai->capture_dma_data = &i2s->capture_dma_data;
408 dai->playback_dma_data = &i2s->playback_dma_data;
413 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
414 .hw_params = rockchip_i2s_hw_params,
415 .set_sysclk = rockchip_i2s_set_sysclk,
416 .set_fmt = rockchip_i2s_set_fmt,
417 .trigger = rockchip_i2s_trigger,
420 static struct snd_soc_dai_driver rockchip_i2s_dai = {
421 .probe = rockchip_i2s_dai_probe,
423 .stream_name = "Playback",
426 .rates = SNDRV_PCM_RATE_8000_192000,
427 .formats = (SNDRV_PCM_FMTBIT_S8 |
428 SNDRV_PCM_FMTBIT_S16_LE |
429 SNDRV_PCM_FMTBIT_S20_3LE |
430 SNDRV_PCM_FMTBIT_S24_LE |
431 SNDRV_PCM_FMTBIT_S32_LE),
434 .stream_name = "Capture",
437 .rates = SNDRV_PCM_RATE_8000_192000,
438 .formats = (SNDRV_PCM_FMTBIT_S8 |
439 SNDRV_PCM_FMTBIT_S16_LE |
440 SNDRV_PCM_FMTBIT_S20_3LE |
441 SNDRV_PCM_FMTBIT_S24_LE |
442 SNDRV_PCM_FMTBIT_S32_LE),
444 .ops = &rockchip_i2s_dai_ops,
445 .symmetric_rates = 1,
448 static const struct snd_soc_component_driver rockchip_i2s_component = {
452 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
469 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
488 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
499 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
507 static const struct reg_default rockchip_i2s_reg_defaults[] = {
515 static const struct regmap_config rockchip_i2s_regmap_config = {
519 .max_register = I2S_RXDR,
520 .reg_defaults = rockchip_i2s_reg_defaults,
521 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
522 .writeable_reg = rockchip_i2s_wr_reg,
523 .readable_reg = rockchip_i2s_rd_reg,
524 .volatile_reg = rockchip_i2s_volatile_reg,
525 .precious_reg = rockchip_i2s_precious_reg,
526 .cache_type = REGCACHE_FLAT,
529 static const struct rk_i2s_pins rk3399_i2s_pins = {
530 .reg_offset = 0xe220,
534 static const struct of_device_id rockchip_i2s_match[] = {
535 { .compatible = "rockchip,rk3066-i2s", },
536 { .compatible = "rockchip,rk3188-i2s", },
537 { .compatible = "rockchip,rk3288-i2s", },
538 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
542 static int rockchip_i2s_probe(struct platform_device *pdev)
544 struct device_node *node = pdev->dev.of_node;
545 const struct of_device_id *of_id;
546 struct rk_i2s_dev *i2s;
547 struct snd_soc_dai_driver *soc_dai;
548 struct resource *res;
553 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
555 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
559 i2s->dev = &pdev->dev;
561 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
562 if (!IS_ERR(i2s->grf)) {
563 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
564 if (!of_id || !of_id->data)
567 i2s->pins = of_id->data;
570 /* try to prepare related clocks */
571 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
572 if (IS_ERR(i2s->hclk)) {
573 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
574 return PTR_ERR(i2s->hclk);
576 ret = clk_prepare_enable(i2s->hclk);
578 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
582 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
583 if (IS_ERR(i2s->mclk)) {
584 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
585 return PTR_ERR(i2s->mclk);
588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589 regs = devm_ioremap_resource(&pdev->dev, res);
591 return PTR_ERR(regs);
593 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
594 &rockchip_i2s_regmap_config);
595 if (IS_ERR(i2s->regmap)) {
597 "Failed to initialise managed register map\n");
598 return PTR_ERR(i2s->regmap);
601 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
602 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
603 i2s->playback_dma_data.maxburst = 4;
605 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
606 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
607 i2s->capture_dma_data.maxburst = 4;
609 dev_set_drvdata(&pdev->dev, i2s);
611 pm_runtime_enable(&pdev->dev);
612 if (!pm_runtime_enabled(&pdev->dev)) {
613 ret = i2s_runtime_resume(&pdev->dev);
618 soc_dai = devm_kzalloc(&pdev->dev,
619 sizeof(*soc_dai), GFP_KERNEL);
623 memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
624 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
625 if (val >= 2 && val <= 8)
626 soc_dai->playback.channels_max = val;
629 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
630 if (val >= 2 && val <= 8)
631 soc_dai->capture.channels_max = val;
634 ret = devm_snd_soc_register_component(&pdev->dev,
635 &rockchip_i2s_component,
639 dev_err(&pdev->dev, "Could not register DAI\n");
643 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
645 dev_err(&pdev->dev, "Could not register PCM\n");
652 if (!pm_runtime_status_suspended(&pdev->dev))
653 i2s_runtime_suspend(&pdev->dev);
655 pm_runtime_disable(&pdev->dev);
660 static int rockchip_i2s_remove(struct platform_device *pdev)
662 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
664 pm_runtime_disable(&pdev->dev);
665 if (!pm_runtime_status_suspended(&pdev->dev))
666 i2s_runtime_suspend(&pdev->dev);
668 clk_disable_unprepare(i2s->mclk);
669 clk_disable_unprepare(i2s->hclk);
674 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
675 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
679 static struct platform_driver rockchip_i2s_driver = {
680 .probe = rockchip_i2s_probe,
681 .remove = rockchip_i2s_remove,
684 .of_match_table = of_match_ptr(rockchip_i2s_match),
685 .pm = &rockchip_i2s_pm_ops,
688 module_platform_driver(rockchip_i2s_driver);
690 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
691 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
692 MODULE_LICENSE("GPL v2");
693 MODULE_ALIAS("platform:" DRV_NAME);
694 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);