2 * s3c24xx-i2s.c -- ALSA Soc Audio Layer
4 * (c) 2006 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
7 * Copyright 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/delay.h>
18 #include <linux/clk.h>
20 #include <linux/gpio.h>
21 #include <linux/module.h>
23 #include <sound/soc.h>
24 #include <sound/pcm_params.h>
26 #include <mach/gpio-samsung.h>
27 #include <plat/gpio-cfg.h>
31 #include "s3c24xx-i2s.h"
33 static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_out = {
38 static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_in = {
43 struct s3c24xx_i2s_info {
51 static struct s3c24xx_i2s_info s3c24xx_i2s;
53 static void s3c24xx_snd_txctrl(int on)
59 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
60 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
61 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
63 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
66 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
67 iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
68 iiscon &= ~S3C2410_IISCON_TXIDLE;
69 iismod |= S3C2410_IISMOD_TXMODE;
71 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
72 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
73 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
75 /* note, we have to disable the FIFOs otherwise bad things
76 * seem to happen when the DMA stops. According to the
77 * Samsung supplied kernel, this should allow the DMA
78 * engine and FIFOs to reset. If this isn't allowed, the
79 * DMA engine will simply freeze randomly.
82 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
83 iisfcon &= ~S3C2410_IISFCON_TXDMA;
84 iiscon |= S3C2410_IISCON_TXIDLE;
85 iiscon &= ~S3C2410_IISCON_TXDMAEN;
86 iismod &= ~S3C2410_IISMOD_TXMODE;
88 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
89 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
90 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
93 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
96 static void s3c24xx_snd_rxctrl(int on)
102 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
103 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
104 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
106 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
109 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
110 iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
111 iiscon &= ~S3C2410_IISCON_RXIDLE;
112 iismod |= S3C2410_IISMOD_RXMODE;
114 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
115 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
116 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
118 /* note, we have to disable the FIFOs otherwise bad things
119 * seem to happen when the DMA stops. According to the
120 * Samsung supplied kernel, this should allow the DMA
121 * engine and FIFOs to reset. If this isn't allowed, the
122 * DMA engine will simply freeze randomly.
125 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
126 iisfcon &= ~S3C2410_IISFCON_RXDMA;
127 iiscon |= S3C2410_IISCON_RXIDLE;
128 iiscon &= ~S3C2410_IISCON_RXDMAEN;
129 iismod &= ~S3C2410_IISMOD_RXMODE;
131 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
132 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
133 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
136 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
140 * Wait for the LR signal to allow synchronisation to the L/R clock
141 * from the codec. May only be needed for slave mode.
143 static int s3c24xx_snd_lrsync(void)
146 int timeout = 50; /* 5ms */
149 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
150 if (iiscon & S3C2410_IISCON_LRINDEX)
162 * Check whether CPU is the master or slave
164 static inline int s3c24xx_snd_is_clkmaster(void)
166 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
170 * Set S3C24xx I2S DAI format
172 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
177 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
178 pr_debug("hw_params r: IISMOD: %x \n", iismod);
180 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
181 case SND_SOC_DAIFMT_CBM_CFM:
182 iismod |= S3C2410_IISMOD_SLAVE;
184 case SND_SOC_DAIFMT_CBS_CFS:
185 iismod &= ~S3C2410_IISMOD_SLAVE;
191 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
192 case SND_SOC_DAIFMT_LEFT_J:
193 iismod |= S3C2410_IISMOD_MSB;
195 case SND_SOC_DAIFMT_I2S:
196 iismod &= ~S3C2410_IISMOD_MSB;
202 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
203 pr_debug("hw_params w: IISMOD: %x \n", iismod);
208 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
209 struct snd_pcm_hw_params *params,
210 struct snd_soc_dai *dai)
212 struct snd_dmaengine_dai_dma_data *dma_data;
215 dma_data = snd_soc_dai_get_dma_data(dai, substream);
217 /* Working copies of register */
218 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
219 pr_debug("hw_params r: IISMOD: %x\n", iismod);
221 switch (params_width(params)) {
223 iismod &= ~S3C2410_IISMOD_16BIT;
224 dma_data->addr_width = 1;
227 iismod |= S3C2410_IISMOD_16BIT;
228 dma_data->addr_width = 2;
234 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
235 pr_debug("hw_params w: IISMOD: %x\n", iismod);
240 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
241 struct snd_soc_dai *dai)
246 case SNDRV_PCM_TRIGGER_START:
247 case SNDRV_PCM_TRIGGER_RESUME:
248 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
249 if (!s3c24xx_snd_is_clkmaster()) {
250 ret = s3c24xx_snd_lrsync();
255 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
256 s3c24xx_snd_rxctrl(1);
258 s3c24xx_snd_txctrl(1);
261 case SNDRV_PCM_TRIGGER_STOP:
262 case SNDRV_PCM_TRIGGER_SUSPEND:
263 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
264 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
265 s3c24xx_snd_rxctrl(0);
267 s3c24xx_snd_txctrl(0);
279 * Set S3C24xx Clock source
281 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
282 int clk_id, unsigned int freq, int dir)
284 u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
286 iismod &= ~S3C2440_IISMOD_MPLL;
289 case S3C24XX_CLKSRC_PCLK:
291 case S3C24XX_CLKSRC_MPLL:
292 iismod |= S3C2440_IISMOD_MPLL;
298 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
303 * Set S3C24xx Clock dividers
305 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
311 case S3C24XX_DIV_BCLK:
312 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
313 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
315 case S3C24XX_DIV_MCLK:
316 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
317 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
319 case S3C24XX_DIV_PRESCALER:
320 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
321 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
322 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
332 * To avoid duplicating clock code, allow machine driver to
333 * get the clockrate from here.
335 u32 s3c24xx_i2s_get_clockrate(void)
337 return clk_get_rate(s3c24xx_i2s.iis_clk);
339 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
341 static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
344 snd_soc_dai_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
345 &s3c24xx_i2s_pcm_stereo_in);
347 s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
348 if (IS_ERR(s3c24xx_i2s.iis_clk)) {
349 pr_err("failed to get iis_clock\n");
350 return PTR_ERR(s3c24xx_i2s.iis_clk);
352 ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
356 /* Configure the I2S pins (GPE0...GPE4) in correct mode */
357 s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
360 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
362 s3c24xx_snd_txctrl(0);
363 s3c24xx_snd_rxctrl(0);
369 static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
371 s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
372 s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
373 s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
374 s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
376 clk_disable_unprepare(s3c24xx_i2s.iis_clk);
381 static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
385 ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
389 writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
390 writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
391 writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
392 writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
397 #define s3c24xx_i2s_suspend NULL
398 #define s3c24xx_i2s_resume NULL
401 #define S3C24XX_I2S_RATES \
402 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
403 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
404 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
406 static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
407 .trigger = s3c24xx_i2s_trigger,
408 .hw_params = s3c24xx_i2s_hw_params,
409 .set_fmt = s3c24xx_i2s_set_fmt,
410 .set_clkdiv = s3c24xx_i2s_set_clkdiv,
411 .set_sysclk = s3c24xx_i2s_set_sysclk,
414 static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
415 .probe = s3c24xx_i2s_probe,
416 .suspend = s3c24xx_i2s_suspend,
417 .resume = s3c24xx_i2s_resume,
421 .rates = S3C24XX_I2S_RATES,
422 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
426 .rates = S3C24XX_I2S_RATES,
427 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
428 .ops = &s3c24xx_i2s_dai_ops,
431 static const struct snd_soc_component_driver s3c24xx_i2s_component = {
432 .name = "s3c24xx-i2s",
435 static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
437 struct resource *res;
440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
442 if (IS_ERR(s3c24xx_i2s.regs))
443 return PTR_ERR(s3c24xx_i2s.regs);
445 s3c24xx_i2s_pcm_stereo_out.addr = res->start + S3C2410_IISFIFO;
446 s3c24xx_i2s_pcm_stereo_in.addr = res->start + S3C2410_IISFIFO;
448 ret = samsung_asoc_dma_platform_register(&pdev->dev, NULL,
451 dev_err(&pdev->dev, "Failed to register the DMA: %d\n", ret);
455 ret = devm_snd_soc_register_component(&pdev->dev,
456 &s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
458 dev_err(&pdev->dev, "Failed to register the DAI\n");
463 static struct platform_driver s3c24xx_iis_driver = {
464 .probe = s3c24xx_iis_dev_probe,
466 .name = "s3c24xx-iis",
470 module_platform_driver(s3c24xx_iis_driver);
472 /* Module information */
473 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
474 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
475 MODULE_LICENSE("GPL");
476 MODULE_ALIAS("platform:s3c24xx-iis");