1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <sound/hdaudio_ext.h>
19 #include <sound/hda_register.h>
28 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
34 /* set reset bits for cores */
35 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
36 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
40 /* poll with timeout to check if operation successful */
41 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
42 HDA_DSP_REG_ADSPCS, adspcs,
43 ((adspcs & reset) == reset),
44 HDA_DSP_REG_POLL_INTERVAL_US,
45 HDA_DSP_RESET_TIMEOUT_US);
48 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
53 /* has core entered reset ? */
54 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
56 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
57 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
59 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
67 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
73 /* clear reset bits for cores */
74 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
76 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
79 /* poll with timeout to check if operation successful */
80 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
81 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
82 HDA_DSP_REG_ADSPCS, adspcs,
84 HDA_DSP_REG_POLL_INTERVAL_US,
85 HDA_DSP_RESET_TIMEOUT_US);
89 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
94 /* has core left reset ? */
95 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
97 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
99 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
107 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
110 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
112 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
113 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
115 /* set reset state */
116 return hda_dsp_core_reset_enter(sdev, core_mask);
119 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
123 /* leave reset state */
124 ret = hda_dsp_core_reset_leave(sdev, core_mask);
129 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
130 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
132 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
135 /* is core now running ? */
136 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
137 hda_dsp_core_stall_reset(sdev, core_mask);
138 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
150 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
157 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
158 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
159 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
161 /* poll with timeout to check if operation successful */
162 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
163 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
164 HDA_DSP_REG_ADSPCS, adspcs,
165 (adspcs & cpa) == cpa,
166 HDA_DSP_REG_POLL_INTERVAL_US,
167 HDA_DSP_RESET_TIMEOUT_US);
170 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
175 /* did core power up ? */
176 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
178 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
179 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
181 "error: power up core failed core_mask %xadspcs 0x%x\n",
189 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
195 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
197 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
199 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
200 HDA_DSP_REG_ADSPCS, adspcs,
201 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
202 HDA_DSP_REG_POLL_INTERVAL_US,
203 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
206 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
212 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
213 unsigned int core_mask)
218 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
220 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
221 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
222 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
223 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
225 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
226 is_enable, core_mask);
231 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
235 /* return if core is already enabled */
236 if (hda_dsp_core_is_enabled(sdev, core_mask))
240 ret = hda_dsp_core_power_up(sdev, core_mask);
242 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
247 return hda_dsp_core_run(sdev, core_mask);
250 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
251 unsigned int core_mask)
255 /* place core in reset prior to power down */
256 ret = hda_dsp_core_stall_reset(sdev, core_mask);
258 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
263 /* power down core */
264 ret = hda_dsp_core_power_down(sdev, core_mask);
266 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
271 /* make sure we are in OFF state */
272 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
273 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
281 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
283 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
284 const struct sof_intel_dsp_desc *chip = hda->desc;
286 /* enable IPC DONE and BUSY interrupts */
287 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
288 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
289 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
291 /* enable IPC interrupt */
292 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
293 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
296 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
298 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
299 const struct sof_intel_dsp_desc *chip = hda->desc;
301 /* disable IPC interrupt */
302 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
303 HDA_DSP_ADSPIC_IPC, 0);
305 /* disable IPC BUSY and DONE interrupt */
306 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
307 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
310 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
312 struct hdac_bus *bus = sof_to_bus(sdev);
313 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
315 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
318 usleep_range(10, 15);
324 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
326 struct sof_ipc_pm_gate pm_gate;
327 struct sof_ipc_reply reply;
329 memset(&pm_gate, 0, sizeof(pm_gate));
331 /* configure pm_gate ipc message */
332 pm_gate.hdr.size = sizeof(pm_gate);
333 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
334 pm_gate.flags = flags;
336 /* send pm_gate ipc to dsp */
337 return sof_ipc_tx_message(sdev->ipc, pm_gate.hdr.cmd, &pm_gate,
338 sizeof(pm_gate), &reply, sizeof(reply));
341 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
342 enum sof_d0_substate d0_substate)
344 struct hdac_bus *bus = sof_to_bus(sdev);
349 /* Write to D0I3C after Command-In-Progress bit is cleared */
350 ret = hda_dsp_wait_d0i3c_done(sdev);
352 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
356 /* Update D0I3C register */
357 value = d0_substate == SOF_DSP_D0I3 ? SOF_HDA_VS_D0I3C_I3 : 0;
358 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
360 /* Wait for cmd in progress to be cleared before exiting the function */
361 ret = hda_dsp_wait_d0i3c_done(sdev);
363 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
367 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
368 snd_hdac_chip_readb(bus, VS_D0I3C));
370 if (d0_substate == SOF_DSP_D0I0)
371 flags = HDA_PM_PPG;/* prevent power gating in D0 */
373 flags = HDA_PM_NO_DMA_TRACE;/* disable DMA trace in D0I3*/
375 /* sending pm_gate IPC */
376 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
379 "error: PM_GATE ipc error %d\n", ret);
384 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
386 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
387 const struct sof_intel_dsp_desc *chip = hda->desc;
388 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
389 struct hdac_bus *bus = sof_to_bus(sdev);
393 /* disable IPC interrupts */
394 hda_dsp_ipc_int_disable(sdev);
396 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
398 hda_codec_jack_wake_enable(sdev);
400 /* power down all hda link */
401 snd_hdac_ext_bus_link_power_down_all(bus);
405 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
408 "error: failed to power down core during suspend\n");
412 /* disable ppcap interrupt */
413 hda_dsp_ctrl_ppcap_enable(sdev, false);
414 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
416 /* disable hda bus irq and streams */
417 hda_dsp_ctrl_stop_chip(sdev);
419 /* disable LP retention mode */
420 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
421 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
423 /* reset controller */
424 ret = hda_dsp_ctrl_link_reset(sdev, true);
427 "error: failed to reset controller during suspend\n");
434 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
436 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
437 struct hdac_bus *bus = sof_to_bus(sdev);
438 struct hdac_ext_link *hlink = NULL;
443 * clear TCSEL to clear playback on some HD Audio
444 * codecs. PCI TCSEL is defined in the Intel manuals.
446 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
448 /* reset and start hda controller */
449 ret = hda_dsp_ctrl_init_chip(sdev, true);
452 "error: failed to start controller after resume\n");
456 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
457 /* check jack status */
459 hda_codec_jack_check(sdev);
461 /* turn off the links that were off before suspend */
462 list_for_each_entry(hlink, &bus->hlink_list, list) {
463 if (!hlink->ref_count)
464 snd_hdac_ext_bus_link_power_down(hlink);
467 /* check dma status and clean up CORB/RIRB buffers */
468 if (!bus->cmd_dma_state)
469 snd_hdac_bus_stop_cmd_io(bus);
472 /* enable ppcap interrupt */
473 hda_dsp_ctrl_ppcap_enable(sdev, true);
474 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
479 int hda_dsp_resume(struct snd_sof_dev *sdev)
481 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
482 struct pci_dev *pci = to_pci_dev(sdev->dev);
484 if (sdev->s0_suspend) {
485 /* restore L1SEN bit */
486 if (hda->l1_support_changed)
487 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
489 HDA_VS_INTEL_EM2_L1SEN, 0);
491 /* restore and disable the system wakeup */
492 pci_restore_state(pci);
493 disable_irq_wake(pci->irq);
497 /* init hda controller. DSP cores will be powered up during fw boot */
498 return hda_resume(sdev, false);
501 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
503 /* init hda controller. DSP cores will be powered up during fw boot */
504 return hda_resume(sdev, true);
507 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
509 struct hdac_bus *hbus = sof_to_bus(sdev);
511 if (hbus->codec_powered) {
512 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
513 (unsigned int)hbus->codec_powered);
520 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
522 /* stop hda controller and power dsp off */
523 return hda_suspend(sdev, true);
526 int hda_dsp_suspend(struct snd_sof_dev *sdev)
528 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
529 struct hdac_bus *bus = sof_to_bus(sdev);
530 struct pci_dev *pci = to_pci_dev(sdev->dev);
533 if (sdev->s0_suspend) {
534 /* enable L1SEN to make sure the system can enter S0Ix */
535 hda->l1_support_changed =
536 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
538 HDA_VS_INTEL_EM2_L1SEN,
539 HDA_VS_INTEL_EM2_L1SEN);
541 /* enable the system waking up via IPC IRQ */
542 enable_irq_wake(pci->irq);
547 /* stop hda controller and power dsp off */
548 ret = hda_suspend(sdev, false);
550 dev_err(bus->dev, "error: suspending dsp\n");
557 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
559 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
560 struct hdac_bus *bus = sof_to_bus(sdev);
561 struct snd_soc_pcm_runtime *rtd;
562 struct hdac_ext_stream *stream;
563 struct hdac_ext_link *link;
564 struct hdac_stream *s;
568 /* set internal flag for BE */
569 list_for_each_entry(s, &bus->stream_list, list) {
570 stream = stream_to_hdac_ext_stream(s);
573 * clear stream. This should already be taken care for running
574 * streams when the SUSPEND trigger is called. But paused
575 * streams do not get suspended, so this needs to be done
576 * explicitly during suspend.
578 if (stream->link_substream) {
579 rtd = snd_pcm_substream_chip(stream->link_substream);
580 name = rtd->codec_dai->component->name;
581 link = snd_hdac_ext_bus_get_link(bus, name);
585 stream->link_prepared = 0;
587 if (hdac_stream(stream)->direction ==
588 SNDRV_PCM_STREAM_CAPTURE)
591 stream_tag = hdac_stream(stream)->stream_tag;
592 snd_hdac_ext_link_clear_stream_id(link, stream_tag);