sound/soc/stm/stm32_i2s.c

   1 /*
   2  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   3  *
   4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   5  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   6  *
   7  * License terms: GPL V2.0.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16  * details.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset.h>
  26 #include <linux/spinlock.h>
  27
  28 #include <sound/dmaengine_pcm.h>
  29 #include <sound/pcm_params.h>
  30
  31 #define STM32_I2S_CR1_REG       0x0
  32 #define STM32_I2S_CFG1_REG      0x08
  33 #define STM32_I2S_CFG2_REG      0x0C
  34 #define STM32_I2S_IER_REG       0x10
  35 #define STM32_I2S_SR_REG        0x14
  36 #define STM32_I2S_IFCR_REG      0x18
  37 #define STM32_I2S_TXDR_REG      0X20
  38 #define STM32_I2S_RXDR_REG      0x30
  39 #define STM32_I2S_CGFR_REG      0X50
  40
  41 /* Bit definition for SPI2S_CR1 register */
  42 #define I2S_CR1_SPE             BIT(0)
  43 #define I2S_CR1_CSTART          BIT(9)
  44 #define I2S_CR1_CSUSP           BIT(10)
  45 #define I2S_CR1_HDDIR           BIT(11)
  46 #define I2S_CR1_SSI             BIT(12)
  47 #define I2S_CR1_CRC33_17        BIT(13)
  48 #define I2S_CR1_RCRCI           BIT(14)
  49 #define I2S_CR1_TCRCI           BIT(15)
  50
  51 /* Bit definition for SPI_CFG2 register */
  52 #define I2S_CFG2_IOSWP_SHIFT    15
  53 #define I2S_CFG2_IOSWP          BIT(I2S_CFG2_IOSWP_SHIFT)
  54 #define I2S_CFG2_LSBFRST        BIT(23)
  55 #define I2S_CFG2_AFCNTR         BIT(31)
  56
  57 /* Bit definition for SPI_CFG1 register */
  58 #define I2S_CFG1_FTHVL_SHIFT    5
  59 #define I2S_CFG1_FTHVL_MASK     GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  60 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
  61
  62 #define I2S_CFG1_TXDMAEN        BIT(15)
  63 #define I2S_CFG1_RXDMAEN        BIT(14)
  64
  65 /* Bit definition for SPI2S_IER register */
  66 #define I2S_IER_RXPIE           BIT(0)
  67 #define I2S_IER_TXPIE           BIT(1)
  68 #define I2S_IER_DPXPIE          BIT(2)
  69 #define I2S_IER_EOTIE           BIT(3)
  70 #define I2S_IER_TXTFIE          BIT(4)
  71 #define I2S_IER_UDRIE           BIT(5)
  72 #define I2S_IER_OVRIE           BIT(6)
  73 #define I2S_IER_CRCEIE          BIT(7)
  74 #define I2S_IER_TIFREIE         BIT(8)
  75 #define I2S_IER_MODFIE          BIT(9)
  76 #define I2S_IER_TSERFIE         BIT(10)
  77
  78 /* Bit definition for SPI2S_SR register */
  79 #define I2S_SR_RXP              BIT(0)
  80 #define I2S_SR_TXP              BIT(1)
  81 #define I2S_SR_DPXP             BIT(2)
  82 #define I2S_SR_EOT              BIT(3)
  83 #define I2S_SR_TXTF             BIT(4)
  84 #define I2S_SR_UDR              BIT(5)
  85 #define I2S_SR_OVR              BIT(6)
  86 #define I2S_SR_CRCERR           BIT(7)
  87 #define I2S_SR_TIFRE            BIT(8)
  88 #define I2S_SR_MODF             BIT(9)
  89 #define I2S_SR_TSERF            BIT(10)
  90 #define I2S_SR_SUSP             BIT(11)
  91 #define I2S_SR_TXC              BIT(12)
  92 #define I2S_SR_RXPLVL           GENMASK(14, 13)
  93 #define I2S_SR_RXWNE            BIT(15)
  94
  95 #define I2S_SR_MASK             GENMASK(15, 0)
  96
  97 /* Bit definition for SPI_IFCR register */
  98 #define I2S_IFCR_EOTC           BIT(3)
  99 #define I2S_IFCR_TXTFC          BIT(4)
 100 #define I2S_IFCR_UDRC           BIT(5)
 101 #define I2S_IFCR_OVRC           BIT(6)
 102 #define I2S_IFCR_CRCEC          BIT(7)
 103 #define I2S_IFCR_TIFREC         BIT(8)
 104 #define I2S_IFCR_MODFC          BIT(9)
 105 #define I2S_IFCR_TSERFC         BIT(10)
 106 #define I2S_IFCR_SUSPC          BIT(11)
 107
 108 #define I2S_IFCR_MASK           GENMASK(11, 3)
 109
 110 /* Bit definition for SPI_I2SCGFR register */
 111 #define I2S_CGFR_I2SMOD         BIT(0)
 112
 113 #define I2S_CGFR_I2SCFG_SHIFT   1
 114 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 115 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
 116
 117 #define I2S_CGFR_I2SSTD_SHIFT   4
 118 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 119 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
 120
 121 #define I2S_CGFR_PCMSYNC        BIT(7)
 122
 123 #define I2S_CGFR_DATLEN_SHIFT   8
 124 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 125 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
 126
 127 #define I2S_CGFR_CHLEN_SHIFT    10
 128 #define I2S_CGFR_CHLEN          BIT(I2S_CGFR_CHLEN_SHIFT)
 129 #define I2S_CGFR_CKPOL          BIT(11)
 130 #define I2S_CGFR_FIXCH          BIT(12)
 131 #define I2S_CGFR_WSINV          BIT(13)
 132 #define I2S_CGFR_DATFMT         BIT(14)
 133
 134 #define I2S_CGFR_I2SDIV_SHIFT   16
 135 #define I2S_CGFR_I2SDIV_BIT_H   23
 136 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 137                                 I2S_CGFR_I2SDIV_SHIFT)
 138 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
 139 #define I2S_CGFR_I2SDIV_MAX     ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 140                                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
 141
 142 #define I2S_CGFR_ODD_SHIFT      24
 143 #define I2S_CGFR_ODD            BIT(I2S_CGFR_ODD_SHIFT)
 144 #define I2S_CGFR_MCKOE          BIT(25)
 145
 146 enum i2s_master_mode {
 147         I2S_MS_NOT_SET,
 148         I2S_MS_MASTER,
 149         I2S_MS_SLAVE,
 150 };
 151
 152 enum i2s_mode {
 153         I2S_I2SMOD_TX_SLAVE,
 154         I2S_I2SMOD_RX_SLAVE,
 155         I2S_I2SMOD_TX_MASTER,
 156         I2S_I2SMOD_RX_MASTER,
 157         I2S_I2SMOD_FD_SLAVE,
 158         I2S_I2SMOD_FD_MASTER,
 159 };
 160
 161 enum i2s_fifo_th {
 162         I2S_FIFO_TH_NONE,
 163         I2S_FIFO_TH_ONE_QUARTER,
 164         I2S_FIFO_TH_HALF,
 165         I2S_FIFO_TH_THREE_QUARTER,
 166         I2S_FIFO_TH_FULL,
 167 };
 168
 169 enum i2s_std {
 170         I2S_STD_I2S,
 171         I2S_STD_LEFT_J,
 172         I2S_STD_RIGHT_J,
 173         I2S_STD_DSP,
 174 };
 175
 176 enum i2s_datlen {
 177         I2S_I2SMOD_DATLEN_16,
 178         I2S_I2SMOD_DATLEN_24,
 179         I2S_I2SMOD_DATLEN_32,
 180 };
 181
 182 #define STM32_I2S_DAI_NAME_SIZE         20
 183 #define STM32_I2S_FIFO_SIZE             16
 184
 185 #define STM32_I2S_IS_MASTER(x)          ((x)->ms_flg == I2S_MS_MASTER)
 186 #define STM32_I2S_IS_SLAVE(x)           ((x)->ms_flg == I2S_MS_SLAVE)
 187
 188 /**
 189  * struct stm32_i2s_data - private data of I2S
 190  * @regmap_conf: I2S register map configuration pointer
 191  * @regmap: I2S register map pointer
 192  * @pdev: device data pointer
 193  * @dai_drv: DAI driver pointer
 194  * @dma_data_tx: dma configuration data for tx channel
 195  * @dma_data_rx: dma configuration data for tx channel
 196  * @substream: PCM substream data pointer
 197  * @i2sclk: kernel clock feeding the I2S clock generator
 198  * @pclk: peripheral clock driving bus interface
 199  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 200  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 201  * @base:  mmio register base virtual address
 202  * @phys_addr: I2S registers physical base address
 203  * @lock_fd: lock to manage race conditions in full duplex mode
 204  * @dais_name: DAI name
 205  * @mclk_rate: master clock frequency (Hz)
 206  * @fmt: DAI protocol
 207  * @refcount: keep count of opened streams on I2S
 208  * @ms_flg: master mode flag.
 209  */
 210 struct stm32_i2s_data {
 211         const struct regmap_config *regmap_conf;
 212         struct regmap *regmap;
 213         struct platform_device *pdev;
 214         struct snd_soc_dai_driver *dai_drv;
 215         struct snd_dmaengine_dai_dma_data dma_data_tx;
 216         struct snd_dmaengine_dai_dma_data dma_data_rx;
 217         struct snd_pcm_substream *substream;
 218         struct clk *i2sclk;
 219         struct clk *pclk;
 220         struct clk *x8kclk;
 221         struct clk *x11kclk;
 222         void __iomem *base;
 223         dma_addr_t phys_addr;
 224         spinlock_t lock_fd; /* Manage race conditions for full duplex */
 225         char dais_name[STM32_I2S_DAI_NAME_SIZE];
 226         unsigned int mclk_rate;
 227         unsigned int fmt;
 228         int refcount;
 229         int ms_flg;
 230 };
 231
 232 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 233 {
 234         struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 235         struct platform_device *pdev = i2s->pdev;
 236         u32 sr, ier;
 237         unsigned long flags;
 238         int err = 0;
 239
 240         regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 241         regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 242
 243         flags = sr & ier;
 244         if (!flags) {
 245                 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 246                         sr, ier);
 247                 return IRQ_NONE;
 248         }
 249
 250         regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 251                            I2S_IFCR_MASK, flags);
 252
 253         if (flags & I2S_SR_OVR) {
 254                 dev_dbg(&pdev->dev, "Overrun\n");
 255                 err = 1;
 256         }
 257
 258         if (flags & I2S_SR_UDR) {
 259                 dev_dbg(&pdev->dev, "Underrun\n");
 260                 err = 1;
 261         }
 262
 263         if (flags & I2S_SR_TIFRE)
 264                 dev_dbg(&pdev->dev, "Frame error\n");
 265
 266         if (err)
 267                 snd_pcm_stop_xrun(i2s->substream);
 268
 269         return IRQ_HANDLED;
 270 }
 271
 272 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 273 {
 274         switch (reg) {
 275         case STM32_I2S_CR1_REG:
 276         case STM32_I2S_CFG1_REG:
 277         case STM32_I2S_CFG2_REG:
 278         case STM32_I2S_IER_REG:
 279         case STM32_I2S_SR_REG:
 280         case STM32_I2S_IFCR_REG:
 281         case STM32_I2S_TXDR_REG:
 282         case STM32_I2S_RXDR_REG:
 283         case STM32_I2S_CGFR_REG:
 284                 return true;
 285         default:
 286                 return false;
 287         }
 288 }
 289
 290 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 291 {
 292         switch (reg) {
 293         case STM32_I2S_TXDR_REG:
 294         case STM32_I2S_RXDR_REG:
 295                 return true;
 296         default:
 297                 return false;
 298         }
 299 }
 300
 301 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 302 {
 303         switch (reg) {
 304         case STM32_I2S_CR1_REG:
 305         case STM32_I2S_CFG1_REG:
 306         case STM32_I2S_CFG2_REG:
 307         case STM32_I2S_IER_REG:
 308         case STM32_I2S_IFCR_REG:
 309         case STM32_I2S_TXDR_REG:
 310         case STM32_I2S_CGFR_REG:
 311                 return true;
 312         default:
 313                 return false;
 314         }
 315 }
 316
 317 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 318 {
 319         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 320         u32 cgfr;
 321         u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 322                          I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 323
 324         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 325
 326         /*
 327          * winv = 0 : default behavior (high/low) for all standards
 328          * ckpol = 0 for all standards.
 329          */
 330         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 331         case SND_SOC_DAIFMT_I2S:
 332                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 333                 break;
 334         case SND_SOC_DAIFMT_MSB:
 335                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 336                 break;
 337         case SND_SOC_DAIFMT_LSB:
 338                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 339                 break;
 340         case SND_SOC_DAIFMT_DSP_A:
 341                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 342                 break;
 343         /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 344         default:
 345                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 346                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 347                 return -EINVAL;
 348         }
 349
 350         /* DAI clock strobing */
 351         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 352         case SND_SOC_DAIFMT_NB_NF:
 353                 break;
 354         case SND_SOC_DAIFMT_IB_NF:
 355                 cgfr |= I2S_CGFR_CKPOL;
 356                 break;
 357         case SND_SOC_DAIFMT_NB_IF:
 358                 cgfr |= I2S_CGFR_WSINV;
 359                 break;
 360         case SND_SOC_DAIFMT_IB_IF:
 361                 cgfr |= I2S_CGFR_CKPOL;
 362                 cgfr |= I2S_CGFR_WSINV;
 363                 break;
 364         default:
 365                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 366                         fmt & SND_SOC_DAIFMT_INV_MASK);
 367                 return -EINVAL;
 368         }
 369
 370         /* DAI clock master masks */
 371         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 372         case SND_SOC_DAIFMT_CBM_CFM:
 373                 i2s->ms_flg = I2S_MS_SLAVE;
 374                 break;
 375         case SND_SOC_DAIFMT_CBS_CFS:
 376                 i2s->ms_flg = I2S_MS_MASTER;
 377                 break;
 378         default:
 379                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 380                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
 381                 return -EINVAL;
 382         }
 383
 384         i2s->fmt = fmt;
 385         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 386                                   cgfr_mask, cgfr);
 387 }
 388
 389 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 390                                 int clk_id, unsigned int freq, int dir)
 391 {
 392         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 393
 394         dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
 395
 396         if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
 397                 i2s->mclk_rate = freq;
 398
 399                 /* Enable master clock if master mode and mclk-fs are set */
 400                 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 401                                           I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 408                                      struct snd_pcm_hw_params *params)
 409 {
 410         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 411         unsigned long i2s_clock_rate;
 412         unsigned int tmp, div, real_div, nb_bits, frame_len;
 413         unsigned int rate = params_rate(params);
 414         int ret;
 415         u32 cgfr, cgfr_mask;
 416         bool odd;
 417
 418         if (!(rate % 11025))
 419                 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
 420         else
 421                 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
 422         i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 423
 424         /*
 425          * mckl = mclk_ratio x ws
 426          *   i2s mode : mclk_ratio = 256
 427          *   dsp mode : mclk_ratio = 128
 428          *
 429          * mclk on
 430          *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 431          *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 432          * mclk off
 433          *   i2s mode : div = i2s_clk / (nb_bits x ws)
 434          *   dsp mode : div = i2s_clk / (nb_bits x ws)
 435          */
 436         if (i2s->mclk_rate) {
 437                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
 438         } else {
 439                 frame_len = 32;
 440                 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 441                     SND_SOC_DAIFMT_DSP_A)
 442                         frame_len = 16;
 443
 444                 /* master clock not enabled */
 445                 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 446                 if (ret < 0)
 447                         return ret;
 448
 449                 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
 450                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
 451         }
 452
 453         /* Check the parity of the divider */
 454         odd = tmp & 0x1;
 455
 456         /* Compute the div prescaler */
 457         div = tmp >> 1;
 458
 459         cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
 460         cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 461
 462         real_div = ((2 * div) + odd);
 463         dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
 464                 i2s_clock_rate, rate);
 465         dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 466                 div, odd, real_div);
 467
 468         if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
 469                 dev_err(cpu_dai->dev, "Wrong divider setting\n");
 470                 return -EINVAL;
 471         }
 472
 473         if (!div && !odd)
 474                 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
 475
 476         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 477                                  cgfr_mask, cgfr);
 478         if (ret < 0)
 479                 return ret;
 480
 481         /* Set bitclock and frameclock to their inactive state */
 482         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 483                                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 484 }
 485
 486 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 487                                struct snd_pcm_hw_params *params,
 488                                struct snd_pcm_substream *substream)
 489 {
 490         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 491         int format = params_width(params);
 492         u32 cfgr, cfgr_mask, cfg1, cfg1_mask;
 493         unsigned int fthlv;
 494         int ret;
 495
 496         if ((params_channels(params) == 1) &&
 497             ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)) {
 498                 dev_err(cpu_dai->dev, "Mono mode supported only by DSP_A\n");
 499                 return -EINVAL;
 500         }
 501
 502         switch (format) {
 503         case 16:
 504                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 505                 cfgr_mask = I2S_CGFR_DATLEN_MASK;
 506                 break;
 507         case 32:
 508                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 509                                            I2S_CGFR_CHLEN;
 510                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 511                 break;
 512         default:
 513                 dev_err(cpu_dai->dev, "Unexpected format %d", format);
 514                 return -EINVAL;
 515         }
 516
 517         if (STM32_I2S_IS_SLAVE(i2s)) {
 518                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 519
 520                 /* As data length is either 16 or 32 bits, fixch always set */
 521                 cfgr |= I2S_CGFR_FIXCH;
 522                 cfgr_mask |= I2S_CGFR_FIXCH;
 523         } else {
 524                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 525         }
 526         cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 527
 528         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 529                                  cfgr_mask, cfgr);
 530         if (ret < 0)
 531                 return ret;
 532
 533         cfg1 = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 534         cfg1_mask = cfg1;
 535
 536         fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 537         cfg1 |= I2S_CFG1_FTHVL_SET(fthlv - 1);
 538         cfg1_mask |= I2S_CFG1_FTHVL_MASK;
 539
 540         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 541                                   cfg1_mask, cfg1);
 542 }
 543
 544 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 545                              struct snd_soc_dai *cpu_dai)
 546 {
 547         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 548
 549         i2s->substream = substream;
 550
 551         spin_lock(&i2s->lock_fd);
 552         i2s->refcount++;
 553         spin_unlock(&i2s->lock_fd);
 554
 555         return regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 556                                   I2S_IFCR_MASK, I2S_IFCR_MASK);
 557 }
 558
 559 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 560                                struct snd_pcm_hw_params *params,
 561                                struct snd_soc_dai *cpu_dai)
 562 {
 563         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 564         int ret;
 565
 566         ret = stm32_i2s_configure(cpu_dai, params, substream);
 567         if (ret < 0) {
 568                 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 569                 return ret;
 570         }
 571
 572         if (STM32_I2S_IS_MASTER(i2s))
 573                 ret = stm32_i2s_configure_clock(cpu_dai, params);
 574
 575         return ret;
 576 }
 577
 578 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 579                              struct snd_soc_dai *cpu_dai)
 580 {
 581         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 582         bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 583         u32 cfg1_mask, ier;
 584         int ret;
 585
 586         switch (cmd) {
 587         case SNDRV_PCM_TRIGGER_START:
 588         case SNDRV_PCM_TRIGGER_RESUME:
 589         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 590                 /* Enable i2s */
 591                 dev_dbg(cpu_dai->dev, "start I2S\n");
 592
 593                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 594                                          I2S_CR1_SPE, I2S_CR1_SPE);
 595                 if (ret < 0) {
 596                         dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 597                         return ret;
 598                 }
 599
 600                 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
 601                                         I2S_CR1_CSTART, I2S_CR1_CSTART);
 602                 if (ret < 0) {
 603                         dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 604                         return ret;
 605                 }
 606
 607                 regmap_update_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 608                                    I2S_IFCR_MASK, I2S_IFCR_MASK);
 609
 610                 if (playback_flg) {
 611                         ier = I2S_IER_UDRIE;
 612                 } else {
 613                         ier = I2S_IER_OVRIE;
 614
 615                         spin_lock(&i2s->lock_fd);
 616                         if (i2s->refcount == 1)
 617                                 /* dummy write to trigger capture */
 618                                 regmap_write(i2s->regmap,
 619                                              STM32_I2S_TXDR_REG, 0);
 620                         spin_unlock(&i2s->lock_fd);
 621                 }
 622
 623                 if (STM32_I2S_IS_SLAVE(i2s))
 624                         ier |= I2S_IER_TIFREIE;
 625
 626                 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
 627                 break;
 628         case SNDRV_PCM_TRIGGER_STOP:
 629         case SNDRV_PCM_TRIGGER_SUSPEND:
 630         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 631                 if (playback_flg)
 632                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 633                                            I2S_IER_UDRIE,
 634                                            (unsigned int)~I2S_IER_UDRIE);
 635                 else
 636                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 637                                            I2S_IER_OVRIE,
 638                                            (unsigned int)~I2S_IER_OVRIE);
 639
 640                 spin_lock(&i2s->lock_fd);
 641                 i2s->refcount--;
 642                 if (i2s->refcount) {
 643                         spin_unlock(&i2s->lock_fd);
 644                         break;
 645                 }
 646                 spin_unlock(&i2s->lock_fd);
 647
 648                 dev_dbg(cpu_dai->dev, "stop I2S\n");
 649
 650                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 651                                          I2S_CR1_SPE, 0);
 652                 if (ret < 0) {
 653                         dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
 654                         return ret;
 655                 }
 656
 657                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 658                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 659                                    cfg1_mask, 0);
 660                 break;
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
 669                                struct snd_soc_dai *cpu_dai)
 670 {
 671         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 672
 673         i2s->substream = NULL;
 674
 675         regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 676                            I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
 677 }
 678
 679 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
 680 {
 681         struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
 682         struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
 683         struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
 684
 685         /* Buswidth will be set by framework */
 686         dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 687         dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
 688         dma_data_tx->maxburst = 1;
 689         dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 690         dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
 691         dma_data_rx->maxburst = 1;
 692
 693         snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
 694
 695         return 0;
 696 }
 697
 698 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
 699         .reg_bits = 32,
 700         .reg_stride = 4,
 701         .val_bits = 32,
 702         .max_register = STM32_I2S_CGFR_REG,
 703         .readable_reg = stm32_i2s_readable_reg,
 704         .volatile_reg = stm32_i2s_volatile_reg,
 705         .writeable_reg = stm32_i2s_writeable_reg,
 706         .fast_io = true,
 707         .cache_type = REGCACHE_FLAT,
 708 };
 709
 710 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
 711         .set_sysclk     = stm32_i2s_set_sysclk,
 712         .set_fmt        = stm32_i2s_set_dai_fmt,
 713         .startup        = stm32_i2s_startup,
 714         .hw_params      = stm32_i2s_hw_params,
 715         .trigger        = stm32_i2s_trigger,
 716         .shutdown       = stm32_i2s_shutdown,
 717 };
 718
 719 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
 720         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 721         .buffer_bytes_max = 8 * PAGE_SIZE,
 722         .period_bytes_max = 2048,
 723         .periods_min = 2,
 724         .periods_max = 8,
 725 };
 726
 727 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
 728         .pcm_hardware   = &stm32_i2s_pcm_hw,
 729         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 730         .prealloc_buffer_size = PAGE_SIZE * 8,
 731 };
 732
 733 static const struct snd_soc_component_driver stm32_i2s_component = {
 734         .name = "stm32-i2s",
 735 };
 736
 737 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
 738                                char *stream_name)
 739 {
 740         stream->stream_name = stream_name;
 741         stream->channels_min = 1;
 742         stream->channels_max = 2;
 743         stream->rates = SNDRV_PCM_RATE_8000_192000;
 744         stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
 745                                    SNDRV_PCM_FMTBIT_S32_LE;
 746 }
 747
 748 static int stm32_i2s_dais_init(struct platform_device *pdev,
 749                                struct stm32_i2s_data *i2s)
 750 {
 751         struct snd_soc_dai_driver *dai_ptr;
 752
 753         dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
 754                                GFP_KERNEL);
 755         if (!dai_ptr)
 756                 return -ENOMEM;
 757
 758         snprintf(i2s->dais_name, STM32_I2S_DAI_NAME_SIZE,
 759                  "%s", dev_name(&pdev->dev));
 760
 761         dai_ptr->probe = stm32_i2s_dai_probe;
 762         dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
 763         dai_ptr->name = i2s->dais_name;
 764         dai_ptr->id = 1;
 765         stm32_i2s_dai_init(&dai_ptr->playback, "playback");
 766         stm32_i2s_dai_init(&dai_ptr->capture, "capture");
 767         i2s->dai_drv = dai_ptr;
 768
 769         return 0;
 770 }
 771
 772 static const struct of_device_id stm32_i2s_ids[] = {
 773         {
 774                 .compatible = "st,stm32h7-i2s",
 775                 .data = &stm32_h7_i2s_regmap_conf
 776         },
 777         {},
 778 };
 779
 780 static int stm32_i2s_parse_dt(struct platform_device *pdev,
 781                               struct stm32_i2s_data *i2s)
 782 {
 783         struct device_node *np = pdev->dev.of_node;
 784         const struct of_device_id *of_id;
 785         struct reset_control *rst;
 786         struct resource *res;
 787         int irq, ret;
 788
 789         if (!np)
 790                 return -ENODEV;
 791
 792         of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
 793         if (of_id)
 794                 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
 795         else
 796                 return -EINVAL;
 797
 798         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 799         i2s->base = devm_ioremap_resource(&pdev->dev, res);
 800         if (IS_ERR(i2s->base))
 801                 return PTR_ERR(i2s->base);
 802
 803         i2s->phys_addr = res->start;
 804
 805         /* Get clocks */
 806         i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
 807         if (IS_ERR(i2s->pclk)) {
 808                 dev_err(&pdev->dev, "Could not get pclk\n");
 809                 return PTR_ERR(i2s->pclk);
 810         }
 811
 812         i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
 813         if (IS_ERR(i2s->i2sclk)) {
 814                 dev_err(&pdev->dev, "Could not get i2sclk\n");
 815                 return PTR_ERR(i2s->i2sclk);
 816         }
 817
 818         i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
 819         if (IS_ERR(i2s->x8kclk)) {
 820                 dev_err(&pdev->dev, "missing x8k parent clock\n");
 821                 return PTR_ERR(i2s->x8kclk);
 822         }
 823
 824         i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
 825         if (IS_ERR(i2s->x11kclk)) {
 826                 dev_err(&pdev->dev, "missing x11k parent clock\n");
 827                 return PTR_ERR(i2s->x11kclk);
 828         }
 829
 830         /* Get irqs */
 831         irq = platform_get_irq(pdev, 0);
 832         if (irq < 0) {
 833                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
 834                 return -ENOENT;
 835         }
 836
 837         ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
 838                                dev_name(&pdev->dev), i2s);
 839         if (ret) {
 840                 dev_err(&pdev->dev, "irq request returned %d\n", ret);
 841                 return ret;
 842         }
 843
 844         /* Reset */
 845         rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 846         if (!IS_ERR(rst)) {
 847                 reset_control_assert(rst);
 848                 udelay(2);
 849                 reset_control_deassert(rst);
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int stm32_i2s_probe(struct platform_device *pdev)
 856 {
 857         struct stm32_i2s_data *i2s;
 858         int ret;
 859
 860         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 861         if (!i2s)
 862                 return -ENOMEM;
 863
 864         ret = stm32_i2s_parse_dt(pdev, i2s);
 865         if (ret)
 866                 return ret;
 867
 868         i2s->pdev = pdev;
 869         i2s->ms_flg = I2S_MS_NOT_SET;
 870         spin_lock_init(&i2s->lock_fd);
 871         platform_set_drvdata(pdev, i2s);
 872
 873         ret = stm32_i2s_dais_init(pdev, i2s);
 874         if (ret)
 875                 return ret;
 876
 877         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->base,
 878                                             i2s->regmap_conf);
 879         if (IS_ERR(i2s->regmap)) {
 880                 dev_err(&pdev->dev, "regmap init failed\n");
 881                 return PTR_ERR(i2s->regmap);
 882         }
 883
 884         ret = clk_prepare_enable(i2s->pclk);
 885         if (ret) {
 886                 dev_err(&pdev->dev, "Enable pclk failed: %d\n", ret);
 887                 return ret;
 888         }
 889
 890         ret = clk_prepare_enable(i2s->i2sclk);
 891         if (ret) {
 892                 dev_err(&pdev->dev, "Enable i2sclk failed: %d\n", ret);
 893                 goto err_pclk_disable;
 894         }
 895
 896         ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
 897                                               i2s->dai_drv, 1);
 898         if (ret)
 899                 goto err_clocks_disable;
 900
 901         ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
 902                                               &stm32_i2s_pcm_config, 0);
 903         if (ret)
 904                 goto err_clocks_disable;
 905
 906         /* Set SPI/I2S in i2s mode */
 907         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 908                                  I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
 909         if (ret)
 910                 goto err_clocks_disable;
 911
 912         return ret;
 913
 914 err_clocks_disable:
 915         clk_disable_unprepare(i2s->i2sclk);
 916 err_pclk_disable:
 917         clk_disable_unprepare(i2s->pclk);
 918
 919         return ret;
 920 }
 921
 922 static int stm32_i2s_remove(struct platform_device *pdev)
 923 {
 924         struct stm32_i2s_data *i2s = platform_get_drvdata(pdev);
 925
 926         clk_disable_unprepare(i2s->i2sclk);
 927         clk_disable_unprepare(i2s->pclk);
 928
 929         return 0;
 930 }
 931
 932 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
 933
 934 #ifdef CONFIG_PM_SLEEP
 935 static int stm32_i2s_suspend(struct device *dev)
 936 {
 937         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 938
 939         regcache_cache_only(i2s->regmap, true);
 940         regcache_mark_dirty(i2s->regmap);
 941
 942         return 0;
 943 }
 944
 945 static int stm32_i2s_resume(struct device *dev)
 946 {
 947         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 948
 949         regcache_cache_only(i2s->regmap, false);
 950         return regcache_sync(i2s->regmap);
 951 }
 952 #endif /* CONFIG_PM_SLEEP */
 953
 954 static const struct dev_pm_ops stm32_i2s_pm_ops = {
 955         SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
 956 };
 957
 958 static struct platform_driver stm32_i2s_driver = {
 959         .driver = {
 960                 .name = "st,stm32-i2s",
 961                 .of_match_table = stm32_i2s_ids,
 962                 .pm = &stm32_i2s_pm_ops,
 963         },
 964         .probe = stm32_i2s_probe,
 965         .remove = stm32_i2s_remove,
 966 };
 967
 968 module_platform_driver(stm32_i2s_driver);
 969
 970 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
 971 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
 972 MODULE_ALIAS("platform:stm32-i2s");
 973 MODULE_LICENSE("GPL v2");