1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Andrea Venturi
4 * Andrea Venturi <be17068@iperbole.bo.it>
6 * Copyright (C) 2016 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
11 #include <linux/dmaengine.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/soc-dai.h>
24 #define SUN4I_I2S_CTRL_REG 0x00
25 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
26 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
27 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
28 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
29 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
30 #define SUN4I_I2S_CTRL_TX_EN BIT(2)
31 #define SUN4I_I2S_CTRL_RX_EN BIT(1)
32 #define SUN4I_I2S_CTRL_GL_EN BIT(0)
34 #define SUN4I_I2S_FMT0_REG 0x04
35 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
36 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
38 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
39 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
41 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
42 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
43 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
44 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
45 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
47 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
48 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
50 #define SUN4I_I2S_FMT1_REG 0x08
51 #define SUN4I_I2S_FIFO_TX_REG 0x0c
52 #define SUN4I_I2S_FIFO_RX_REG 0x10
54 #define SUN4I_I2S_FIFO_CTRL_REG 0x14
55 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
56 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
57 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
58 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
59 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
60 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
62 #define SUN4I_I2S_FIFO_STA_REG 0x18
64 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
65 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
66 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
68 #define SUN4I_I2S_INT_STA_REG 0x20
70 #define SUN4I_I2S_CLK_DIV_REG 0x24
71 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
72 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
73 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
74 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
75 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
77 #define SUN4I_I2S_TX_CNT_REG 0x28
78 #define SUN4I_I2S_RX_CNT_REG 0x2c
80 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
81 #define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
82 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
84 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
85 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
87 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
88 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
90 /* Defines required for sun8i-h3 support */
91 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
92 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
94 #define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
95 #define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
96 #define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
97 #define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
99 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
100 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
101 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
102 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
103 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
104 #define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
105 #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
106 #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
108 #define SUN8I_I2S_INT_STA_REG 0x0c
109 #define SUN8I_I2S_FIFO_TX_REG 0x20
111 #define SUN8I_I2S_CHAN_CFG_REG 0x30
112 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4)
113 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
114 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0)
115 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
117 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
118 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
119 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
120 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
121 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
122 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
124 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
125 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
130 * struct sun4i_i2s_quirks - Differences between SoC variants.
132 * @has_reset: SoC needs reset deasserted.
133 * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
134 * @reg_offset_txdata: offset of the tx fifo.
135 * @sun4i_i2s_regmap: regmap config to use.
136 * @field_clkdiv_mclk_en: regmap field to enable mclk output.
137 * @field_fmt_wss: regmap field to set word select size.
138 * @field_fmt_sr: regmap field to set sample resolution.
140 struct sun4i_i2s_quirks {
142 bool has_fmt_set_lrck_period;
143 unsigned int reg_offset_txdata; /* TX FIFO */
144 const struct regmap_config *sun4i_i2s_regmap;
146 /* Register fields for i2s */
147 struct reg_field field_clkdiv_mclk_en;
148 struct reg_field field_fmt_wss;
149 struct reg_field field_fmt_sr;
151 const struct sun4i_i2s_clk_div *bclk_dividers;
152 unsigned int num_bclk_dividers;
153 const struct sun4i_i2s_clk_div *mclk_dividers;
154 unsigned int num_mclk_dividers;
156 unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
157 s8 (*get_sr)(const struct sun4i_i2s *, int);
158 s8 (*get_wss)(const struct sun4i_i2s *, int);
159 int (*set_chan_cfg)(const struct sun4i_i2s *,
160 const struct snd_pcm_hw_params *);
161 int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
167 struct regmap *regmap;
168 struct reset_control *rst;
170 unsigned int mclk_freq;
172 unsigned int slot_width;
174 struct snd_dmaengine_dai_dma_data capture_dma_data;
175 struct snd_dmaengine_dai_dma_data playback_dma_data;
177 /* Register fields for i2s */
178 struct regmap_field *field_clkdiv_mclk_en;
179 struct regmap_field *field_fmt_wss;
180 struct regmap_field *field_fmt_sr;
182 const struct sun4i_i2s_quirks *variant;
185 struct sun4i_i2s_clk_div {
190 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
191 { .div = 2, .val = 0 },
192 { .div = 4, .val = 1 },
193 { .div = 6, .val = 2 },
194 { .div = 8, .val = 3 },
195 { .div = 12, .val = 4 },
196 { .div = 16, .val = 5 },
197 /* TODO - extend divide ratio supported by newer SoCs */
200 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
201 { .div = 1, .val = 0 },
202 { .div = 2, .val = 1 },
203 { .div = 4, .val = 2 },
204 { .div = 6, .val = 3 },
205 { .div = 8, .val = 4 },
206 { .div = 12, .val = 5 },
207 { .div = 16, .val = 6 },
208 { .div = 24, .val = 7 },
209 /* TODO - extend divide ratio supported by newer SoCs */
212 static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
213 { .div = 1, .val = 1 },
214 { .div = 2, .val = 2 },
215 { .div = 4, .val = 3 },
216 { .div = 6, .val = 4 },
217 { .div = 8, .val = 5 },
218 { .div = 12, .val = 6 },
219 { .div = 16, .val = 7 },
220 { .div = 24, .val = 8 },
221 { .div = 32, .val = 9 },
222 { .div = 48, .val = 10 },
223 { .div = 64, .val = 11 },
224 { .div = 96, .val = 12 },
225 { .div = 128, .val = 13 },
226 { .div = 176, .val = 14 },
227 { .div = 192, .val = 15 },
230 static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
232 return i2s->mclk_freq;
235 static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
237 return clk_get_rate(i2s->mod_clk);
240 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
241 unsigned long parent_rate,
242 unsigned int sampling_rate,
243 unsigned int channels,
244 unsigned int word_size)
246 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
247 int div = parent_rate / sampling_rate / word_size / channels;
250 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
251 const struct sun4i_i2s_clk_div *bdiv = ÷rs[i];
253 if (bdiv->div == div)
260 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
261 unsigned long parent_rate,
262 unsigned long mclk_rate)
264 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
265 int div = parent_rate / mclk_rate;
268 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
269 const struct sun4i_i2s_clk_div *mdiv = ÷rs[i];
271 if (mdiv->div == div)
278 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
279 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
283 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
284 if (sun4i_i2s_oversample_rates[i] == oversample)
290 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
293 unsigned int slot_width)
295 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
296 unsigned int oversample_rate, clk_rate, bclk_parent_rate;
297 int bclk_div, mclk_div;
323 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
327 ret = clk_set_rate(i2s->mod_clk, clk_rate);
331 oversample_rate = i2s->mclk_freq / rate;
332 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
333 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
338 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
339 bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
340 rate, slots, slot_width);
342 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
346 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
348 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
352 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
353 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
354 SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
356 regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
358 /* Set sync period */
359 if (i2s->variant->has_fmt_set_lrck_period)
360 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
361 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
362 SUN8I_I2S_FMT0_LRCK_PERIOD(slot_width));
367 static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
369 if (width < 16 || width > 24)
375 return (width - 16) / 4;
378 static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
380 if (width < 16 || width > 32)
386 return (width - 16) / 4;
389 static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
394 if (width < 8 || width > 32)
397 return (width - 8) / 4 + 1;
400 static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
401 const struct snd_pcm_hw_params *params)
403 unsigned int channels = params_channels(params);
405 /* Map the channels for playback and capture */
406 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
407 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);
409 /* Configure the channels */
410 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
411 SUN4I_I2S_CHAN_SEL_MASK,
412 SUN4I_I2S_CHAN_SEL(channels));
413 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG,
414 SUN4I_I2S_CHAN_SEL_MASK,
415 SUN4I_I2S_CHAN_SEL(channels));
420 static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
421 const struct snd_pcm_hw_params *params)
423 unsigned int channels = params_channels(params);
424 unsigned int slots = channels;
429 /* Map the channels for playback and capture */
430 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
431 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
433 /* Configure the channels */
434 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
435 SUN4I_I2S_CHAN_SEL_MASK,
436 SUN4I_I2S_CHAN_SEL(channels));
437 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
438 SUN4I_I2S_CHAN_SEL_MASK,
439 SUN4I_I2S_CHAN_SEL(channels));
441 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
442 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
443 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
444 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
445 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
446 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
448 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
449 SUN8I_I2S_TX_CHAN_EN_MASK,
450 SUN8I_I2S_TX_CHAN_EN(channels));
455 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
456 struct snd_pcm_hw_params *params,
457 struct snd_soc_dai *dai)
459 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
460 unsigned int word_size = params_width(params);
461 unsigned int slot_width = params_physical_width(params);
462 unsigned int channels = params_channels(params);
463 unsigned int slots = channels;
471 slot_width = i2s->slot_width;
473 ret = i2s->variant->set_chan_cfg(i2s, params);
475 dev_err(dai->dev, "Invalid channel configuration\n");
479 switch (params_physical_width(params)) {
481 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
484 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
485 params_physical_width(params));
488 i2s->playback_dma_data.addr_width = width;
490 sr = i2s->variant->get_sr(i2s, params_width(params));
494 wss = i2s->variant->get_wss(i2s, slot_width);
498 regmap_field_write(i2s->field_fmt_wss, wss);
499 regmap_field_write(i2s->field_fmt_sr, sr);
501 return sun4i_i2s_set_clk_rate(dai, params_rate(params),
505 static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
510 /* DAI clock polarity */
511 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
512 case SND_SOC_DAIFMT_IB_IF:
513 /* Invert both clocks */
514 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
515 SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
517 case SND_SOC_DAIFMT_IB_NF:
518 /* Invert bit clock */
519 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED;
521 case SND_SOC_DAIFMT_NB_IF:
522 /* Invert frame clock */
523 val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
525 case SND_SOC_DAIFMT_NB_NF:
532 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
533 SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK |
534 SUN4I_I2S_FMT0_BCLK_POLARITY_MASK,
538 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
539 case SND_SOC_DAIFMT_I2S:
540 val = SUN4I_I2S_FMT0_FMT_I2S;
543 case SND_SOC_DAIFMT_LEFT_J:
544 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
547 case SND_SOC_DAIFMT_RIGHT_J:
548 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
555 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
556 SUN4I_I2S_FMT0_FMT_MASK, val);
558 /* DAI clock master masks */
559 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
560 case SND_SOC_DAIFMT_CBS_CFS:
561 /* BCLK and LRCLK master */
562 val = SUN4I_I2S_CTRL_MODE_MASTER;
565 case SND_SOC_DAIFMT_CBM_CFM:
566 /* BCLK and LRCLK slave */
567 val = SUN4I_I2S_CTRL_MODE_SLAVE;
573 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
574 SUN4I_I2S_CTRL_MODE_MASK, val);
578 static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
587 * The setup for LRCK contradicts the datasheet, but under a
588 * scope it's clear that the LRCK polarity is reversed
589 * compared to the expected polarity on the bus.
591 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
592 case SND_SOC_DAIFMT_IB_IF:
593 /* Invert both clocks */
594 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
596 case SND_SOC_DAIFMT_IB_NF:
597 /* Invert bit clock */
598 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
599 SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
601 case SND_SOC_DAIFMT_NB_IF:
602 /* Invert frame clock */
605 case SND_SOC_DAIFMT_NB_NF:
606 val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
612 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
613 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
614 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
618 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
619 case SND_SOC_DAIFMT_I2S:
620 mode = SUN8I_I2S_CTRL_MODE_LEFT;
624 case SND_SOC_DAIFMT_LEFT_J:
625 mode = SUN8I_I2S_CTRL_MODE_LEFT;
629 case SND_SOC_DAIFMT_RIGHT_J:
630 mode = SUN8I_I2S_CTRL_MODE_RIGHT;
638 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
639 SUN8I_I2S_CTRL_MODE_MASK, mode);
640 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
641 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
642 SUN8I_I2S_TX_CHAN_OFFSET(offset));
643 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
644 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
645 SUN8I_I2S_TX_CHAN_OFFSET(offset));
647 /* DAI clock master masks */
648 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
649 case SND_SOC_DAIFMT_CBS_CFS:
650 /* BCLK and LRCLK master */
651 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
654 case SND_SOC_DAIFMT_CBM_CFM:
655 /* BCLK and LRCLK slave */
663 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
664 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
670 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
672 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
675 ret = i2s->variant->set_fmt(i2s, fmt);
677 dev_err(dai->dev, "Unsupported format configuration\n");
681 /* Set significant bits in our FIFOs */
682 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
683 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
684 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
685 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
686 SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
690 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
693 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
694 SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
695 SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
697 /* Clear RX counter */
698 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
700 /* Enable RX Block */
701 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
702 SUN4I_I2S_CTRL_RX_EN,
703 SUN4I_I2S_CTRL_RX_EN);
706 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
707 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
708 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
711 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
714 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
715 SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
716 SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
718 /* Clear TX counter */
719 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
721 /* Enable TX Block */
722 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
723 SUN4I_I2S_CTRL_TX_EN,
724 SUN4I_I2S_CTRL_TX_EN);
727 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
728 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
729 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
732 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
734 /* Disable RX Block */
735 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
736 SUN4I_I2S_CTRL_RX_EN,
740 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
741 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
745 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
747 /* Disable TX Block */
748 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
749 SUN4I_I2S_CTRL_TX_EN,
753 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
754 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
758 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
759 struct snd_soc_dai *dai)
761 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
764 case SNDRV_PCM_TRIGGER_START:
765 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
766 case SNDRV_PCM_TRIGGER_RESUME:
767 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
768 sun4i_i2s_start_playback(i2s);
770 sun4i_i2s_start_capture(i2s);
773 case SNDRV_PCM_TRIGGER_STOP:
774 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
775 case SNDRV_PCM_TRIGGER_SUSPEND:
776 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
777 sun4i_i2s_stop_playback(i2s);
779 sun4i_i2s_stop_capture(i2s);
789 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
790 unsigned int freq, int dir)
792 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
797 i2s->mclk_freq = freq;
802 static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai,
803 unsigned int tx_mask, unsigned int rx_mask,
804 int slots, int slot_width)
806 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
812 i2s->slot_width = slot_width;
817 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
818 .hw_params = sun4i_i2s_hw_params,
819 .set_fmt = sun4i_i2s_set_fmt,
820 .set_sysclk = sun4i_i2s_set_sysclk,
821 .set_tdm_slot = sun4i_i2s_set_tdm_slot,
822 .trigger = sun4i_i2s_trigger,
825 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
827 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
829 snd_soc_dai_init_dma_data(dai,
830 &i2s->playback_dma_data,
831 &i2s->capture_dma_data);
833 snd_soc_dai_set_drvdata(dai, i2s);
838 static struct snd_soc_dai_driver sun4i_i2s_dai = {
839 .probe = sun4i_i2s_dai_probe,
841 .stream_name = "Capture",
844 .rates = SNDRV_PCM_RATE_8000_192000,
845 .formats = SNDRV_PCM_FMTBIT_S16_LE,
848 .stream_name = "Playback",
851 .rates = SNDRV_PCM_RATE_8000_192000,
852 .formats = SNDRV_PCM_FMTBIT_S16_LE,
854 .ops = &sun4i_i2s_dai_ops,
855 .symmetric_rates = 1,
858 static const struct snd_soc_component_driver sun4i_i2s_component = {
862 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
865 case SUN4I_I2S_FIFO_TX_REG:
873 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
876 case SUN4I_I2S_FIFO_RX_REG:
877 case SUN4I_I2S_FIFO_STA_REG:
885 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
888 case SUN4I_I2S_FIFO_RX_REG:
889 case SUN4I_I2S_INT_STA_REG:
890 case SUN4I_I2S_RX_CNT_REG:
891 case SUN4I_I2S_TX_CNT_REG:
899 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
902 case SUN8I_I2S_FIFO_TX_REG:
910 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
912 if (reg == SUN8I_I2S_INT_STA_REG)
914 if (reg == SUN8I_I2S_FIFO_TX_REG)
917 return sun4i_i2s_volatile_reg(dev, reg);
920 static const struct reg_default sun4i_i2s_reg_defaults[] = {
921 { SUN4I_I2S_CTRL_REG, 0x00000000 },
922 { SUN4I_I2S_FMT0_REG, 0x0000000c },
923 { SUN4I_I2S_FMT1_REG, 0x00004020 },
924 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
925 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
926 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
927 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
928 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
929 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
930 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
933 static const struct reg_default sun8i_i2s_reg_defaults[] = {
934 { SUN4I_I2S_CTRL_REG, 0x00060000 },
935 { SUN4I_I2S_FMT0_REG, 0x00000033 },
936 { SUN4I_I2S_FMT1_REG, 0x00000030 },
937 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
938 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
939 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
940 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
941 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
942 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
943 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
944 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
947 static const struct regmap_config sun4i_i2s_regmap_config = {
951 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
953 .cache_type = REGCACHE_FLAT,
954 .reg_defaults = sun4i_i2s_reg_defaults,
955 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
956 .writeable_reg = sun4i_i2s_wr_reg,
957 .readable_reg = sun4i_i2s_rd_reg,
958 .volatile_reg = sun4i_i2s_volatile_reg,
961 static const struct regmap_config sun8i_i2s_regmap_config = {
965 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
966 .cache_type = REGCACHE_FLAT,
967 .reg_defaults = sun8i_i2s_reg_defaults,
968 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
969 .writeable_reg = sun4i_i2s_wr_reg,
970 .readable_reg = sun8i_i2s_rd_reg,
971 .volatile_reg = sun8i_i2s_volatile_reg,
974 static int sun4i_i2s_runtime_resume(struct device *dev)
976 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
979 ret = clk_prepare_enable(i2s->bus_clk);
981 dev_err(dev, "Failed to enable bus clock\n");
985 regcache_cache_only(i2s->regmap, false);
986 regcache_mark_dirty(i2s->regmap);
988 ret = regcache_sync(i2s->regmap);
990 dev_err(dev, "Failed to sync regmap cache\n");
991 goto err_disable_clk;
994 /* Enable the whole hardware block */
995 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
996 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
998 /* Enable the first output line */
999 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1000 SUN4I_I2S_CTRL_SDO_EN_MASK,
1001 SUN4I_I2S_CTRL_SDO_EN(0));
1003 ret = clk_prepare_enable(i2s->mod_clk);
1005 dev_err(dev, "Failed to enable module clock\n");
1006 goto err_disable_clk;
1012 clk_disable_unprepare(i2s->bus_clk);
1016 static int sun4i_i2s_runtime_suspend(struct device *dev)
1018 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
1020 clk_disable_unprepare(i2s->mod_clk);
1022 /* Disable our output lines */
1023 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1024 SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
1026 /* Disable the whole hardware block */
1027 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
1028 SUN4I_I2S_CTRL_GL_EN, 0);
1030 regcache_cache_only(i2s->regmap, true);
1032 clk_disable_unprepare(i2s->bus_clk);
1037 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
1039 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
1040 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1041 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1042 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1043 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1044 .bclk_dividers = sun4i_i2s_bclk_div,
1045 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1046 .mclk_dividers = sun4i_i2s_mclk_div,
1047 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1048 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1049 .get_sr = sun4i_i2s_get_sr,
1050 .get_wss = sun4i_i2s_get_wss,
1051 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1052 .set_fmt = sun4i_i2s_set_soc_fmt,
1055 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
1057 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
1058 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1059 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1060 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1061 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1062 .bclk_dividers = sun4i_i2s_bclk_div,
1063 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1064 .mclk_dividers = sun4i_i2s_mclk_div,
1065 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1066 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1067 .get_sr = sun4i_i2s_get_sr,
1068 .get_wss = sun4i_i2s_get_wss,
1069 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1070 .set_fmt = sun4i_i2s_set_soc_fmt,
1073 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
1075 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1076 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1077 .has_fmt_set_lrck_period = true,
1078 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
1079 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
1080 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
1081 .bclk_dividers = sun8i_i2s_clk_div,
1082 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1083 .mclk_dividers = sun8i_i2s_clk_div,
1084 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
1085 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
1086 .get_sr = sun8i_i2s_get_sr_wss,
1087 .get_wss = sun8i_i2s_get_sr_wss,
1088 .set_chan_cfg = sun8i_i2s_set_chan_cfg,
1089 .set_fmt = sun8i_i2s_set_soc_fmt,
1092 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
1094 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
1095 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
1096 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1097 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1098 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1099 .bclk_dividers = sun4i_i2s_bclk_div,
1100 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
1101 .mclk_dividers = sun4i_i2s_mclk_div,
1102 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
1103 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
1104 .get_sr = sun4i_i2s_get_sr,
1105 .get_wss = sun4i_i2s_get_wss,
1106 .set_chan_cfg = sun4i_i2s_set_chan_cfg,
1107 .set_fmt = sun4i_i2s_set_soc_fmt,
1110 static int sun4i_i2s_init_regmap_fields(struct device *dev,
1111 struct sun4i_i2s *i2s)
1113 i2s->field_clkdiv_mclk_en =
1114 devm_regmap_field_alloc(dev, i2s->regmap,
1115 i2s->variant->field_clkdiv_mclk_en);
1116 if (IS_ERR(i2s->field_clkdiv_mclk_en))
1117 return PTR_ERR(i2s->field_clkdiv_mclk_en);
1119 i2s->field_fmt_wss =
1120 devm_regmap_field_alloc(dev, i2s->regmap,
1121 i2s->variant->field_fmt_wss);
1122 if (IS_ERR(i2s->field_fmt_wss))
1123 return PTR_ERR(i2s->field_fmt_wss);
1126 devm_regmap_field_alloc(dev, i2s->regmap,
1127 i2s->variant->field_fmt_sr);
1128 if (IS_ERR(i2s->field_fmt_sr))
1129 return PTR_ERR(i2s->field_fmt_sr);
1134 static int sun4i_i2s_probe(struct platform_device *pdev)
1136 struct sun4i_i2s *i2s;
1137 struct resource *res;
1141 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1144 platform_set_drvdata(pdev, i2s);
1146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1147 regs = devm_ioremap_resource(&pdev->dev, res);
1149 return PTR_ERR(regs);
1151 irq = platform_get_irq(pdev, 0);
1155 i2s->variant = of_device_get_match_data(&pdev->dev);
1156 if (!i2s->variant) {
1157 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1161 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1162 if (IS_ERR(i2s->bus_clk)) {
1163 dev_err(&pdev->dev, "Can't get our bus clock\n");
1164 return PTR_ERR(i2s->bus_clk);
1167 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1168 i2s->variant->sun4i_i2s_regmap);
1169 if (IS_ERR(i2s->regmap)) {
1170 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1171 return PTR_ERR(i2s->regmap);
1174 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1175 if (IS_ERR(i2s->mod_clk)) {
1176 dev_err(&pdev->dev, "Can't get our mod clock\n");
1177 return PTR_ERR(i2s->mod_clk);
1180 if (i2s->variant->has_reset) {
1181 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1182 if (IS_ERR(i2s->rst)) {
1183 dev_err(&pdev->dev, "Failed to get reset control\n");
1184 return PTR_ERR(i2s->rst);
1188 if (!IS_ERR(i2s->rst)) {
1189 ret = reset_control_deassert(i2s->rst);
1192 "Failed to deassert the reset control\n");
1197 i2s->playback_dma_data.addr = res->start +
1198 i2s->variant->reg_offset_txdata;
1199 i2s->playback_dma_data.maxburst = 8;
1201 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1202 i2s->capture_dma_data.maxburst = 8;
1204 pm_runtime_enable(&pdev->dev);
1205 if (!pm_runtime_enabled(&pdev->dev)) {
1206 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1208 goto err_pm_disable;
1211 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1213 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1217 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1219 dev_err(&pdev->dev, "Could not register PCM\n");
1223 ret = devm_snd_soc_register_component(&pdev->dev,
1224 &sun4i_i2s_component,
1227 dev_err(&pdev->dev, "Could not register DAI\n");
1234 if (!pm_runtime_status_suspended(&pdev->dev))
1235 sun4i_i2s_runtime_suspend(&pdev->dev);
1237 pm_runtime_disable(&pdev->dev);
1238 if (!IS_ERR(i2s->rst))
1239 reset_control_assert(i2s->rst);
1244 static int sun4i_i2s_remove(struct platform_device *pdev)
1246 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1248 pm_runtime_disable(&pdev->dev);
1249 if (!pm_runtime_status_suspended(&pdev->dev))
1250 sun4i_i2s_runtime_suspend(&pdev->dev);
1252 if (!IS_ERR(i2s->rst))
1253 reset_control_assert(i2s->rst);
1258 static const struct of_device_id sun4i_i2s_match[] = {
1260 .compatible = "allwinner,sun4i-a10-i2s",
1261 .data = &sun4i_a10_i2s_quirks,
1264 .compatible = "allwinner,sun6i-a31-i2s",
1265 .data = &sun6i_a31_i2s_quirks,
1268 .compatible = "allwinner,sun8i-a83t-i2s",
1269 .data = &sun8i_a83t_i2s_quirks,
1272 .compatible = "allwinner,sun8i-h3-i2s",
1273 .data = &sun8i_a83t_i2s_quirks,
1276 .compatible = "allwinner,sun50i-a64-codec-i2s",
1277 .data = &sun50i_a64_codec_i2s_quirks,
1281 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1283 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1284 .runtime_resume = sun4i_i2s_runtime_resume,
1285 .runtime_suspend = sun4i_i2s_runtime_suspend,
1288 static struct platform_driver sun4i_i2s_driver = {
1289 .probe = sun4i_i2s_probe,
1290 .remove = sun4i_i2s_remove,
1292 .name = "sun4i-i2s",
1293 .of_match_table = sun4i_i2s_match,
1294 .pm = &sun4i_i2s_pm_ops,
1297 module_platform_driver(sun4i_i2s_driver);
1299 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1300 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1301 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1302 MODULE_LICENSE("GPL");