sound/soc/sunxi/sun4i-i2s.c

   1 /*
   2  * Copyright (C) 2015 Andrea Venturi
   3  * Andrea Venturi <be17068@iperbole.bo.it>
   4  *
   5  * Copyright (C) 2016 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 #include <sound/dmaengine_pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27
  28 #define SUN4I_I2S_CTRL_REG              0x00
  29 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  30 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  31 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  32 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  33 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  34 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  35 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  36 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  37
  38 #define SUN4I_I2S_FMT0_REG              0x04
  39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  45 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  46 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  47 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  48 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  49 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  51 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  52 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  55
  56 #define SUN4I_I2S_FMT1_REG              0x08
  57 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  58 #define SUN4I_I2S_FIFO_RX_REG           0x10
  59
  60 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  67
  68 #define SUN4I_I2S_FIFO_STA_REG          0x18
  69
  70 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  73
  74 #define SUN4I_I2S_INT_STA_REG           0x20
  75
  76 #define SUN4I_I2S_CLK_DIV_REG           0x24
  77 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  82
  83 #define SUN4I_I2S_RX_CNT_REG            0x28
  84 #define SUN4I_I2S_TX_CNT_REG            0x2c
  85
  86 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  87 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  88
  89 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  91
  92 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  93 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  94
  95 /* Defines required for sun8i-h3 support */
  96 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  97 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  98
  99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
 101
 102 #define SUN8I_I2S_INT_STA_REG           0x0c
 103 #define SUN8I_I2S_FIFO_TX_REG           0x20
 104
 105 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 110
 111 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 112 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 11)
 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 115 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 117
 118 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 119 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 120
 121 /**
 122  * struct sun4i_i2s_quirks - Differences between SoC variants.
 123  *
 124  * @has_reset: SoC needs reset deasserted.
 125  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 126  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 127  * @has_chcfg: tx and rx slot number need to be set.
 128  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 129  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 130  * @reg_offset_txdata: offset of the tx fifo.
 131  * @sun4i_i2s_regmap: regmap config to use.
 132  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 133  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 134  * @fmt_offset: Value by which wss and sr needs to be adjusted.
 135  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 136  * @field_fmt_wss: regmap field to set word select size.
 137  * @field_fmt_sr: regmap field to set sample resolution.
 138  * @field_fmt_bclk: regmap field to set clk polarity.
 139  * @field_fmt_lrclk: regmap field to set frame polarity.
 140  * @field_fmt_mode: regmap field to set the operational mode.
 141  * @field_txchanmap: location of the tx channel mapping register.
 142  * @field_rxchanmap: location of the rx channel mapping register.
 143  * @field_txchansel: location of the tx channel select bit fields.
 144  * @field_rxchansel: location of the rx channel select bit fields.
 145  */
 146 struct sun4i_i2s_quirks {
 147         bool                            has_reset;
 148         bool                            has_slave_select_bit;
 149         bool                            has_fmt_set_lrck_period;
 150         bool                            has_chcfg;
 151         bool                            has_chsel_tx_chen;
 152         bool                            has_chsel_offset;
 153         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 154         const struct regmap_config      *sun4i_i2s_regmap;
 155         unsigned int                    mclk_offset;
 156         unsigned int                    bclk_offset;
 157         unsigned int                    fmt_offset;
 158
 159         /* Register fields for i2s */
 160         struct reg_field                field_clkdiv_mclk_en;
 161         struct reg_field                field_fmt_wss;
 162         struct reg_field                field_fmt_sr;
 163         struct reg_field                field_fmt_bclk;
 164         struct reg_field                field_fmt_lrclk;
 165         struct reg_field                field_fmt_mode;
 166         struct reg_field                field_txchanmap;
 167         struct reg_field                field_rxchanmap;
 168         struct reg_field                field_txchansel;
 169         struct reg_field                field_rxchansel;
 170 };
 171
 172 struct sun4i_i2s {
 173         struct clk      *bus_clk;
 174         struct clk      *mod_clk;
 175         struct regmap   *regmap;
 176         struct reset_control *rst;
 177
 178         unsigned int    mclk_freq;
 179
 180         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 181         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 182
 183         /* Register fields for i2s */
 184         struct regmap_field     *field_clkdiv_mclk_en;
 185         struct regmap_field     *field_fmt_wss;
 186         struct regmap_field     *field_fmt_sr;
 187         struct regmap_field     *field_fmt_bclk;
 188         struct regmap_field     *field_fmt_lrclk;
 189         struct regmap_field     *field_fmt_mode;
 190         struct regmap_field     *field_txchanmap;
 191         struct regmap_field     *field_rxchanmap;
 192         struct regmap_field     *field_txchansel;
 193         struct regmap_field     *field_rxchansel;
 194
 195         const struct sun4i_i2s_quirks   *variant;
 196 };
 197
 198 struct sun4i_i2s_clk_div {
 199         u8      div;
 200         u8      val;
 201 };
 202
 203 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 204         { .div = 2, .val = 0 },
 205         { .div = 4, .val = 1 },
 206         { .div = 6, .val = 2 },
 207         { .div = 8, .val = 3 },
 208         { .div = 12, .val = 4 },
 209         { .div = 16, .val = 5 },
 210         /* TODO - extend divide ratio supported by newer SoCs */
 211 };
 212
 213 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 214         { .div = 1, .val = 0 },
 215         { .div = 2, .val = 1 },
 216         { .div = 4, .val = 2 },
 217         { .div = 6, .val = 3 },
 218         { .div = 8, .val = 4 },
 219         { .div = 12, .val = 5 },
 220         { .div = 16, .val = 6 },
 221         { .div = 24, .val = 7 },
 222         /* TODO - extend divide ratio supported by newer SoCs */
 223 };
 224
 225 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 226                                   unsigned int oversample_rate,
 227                                   unsigned int word_size)
 228 {
 229         int div = oversample_rate / word_size / 2;
 230         int i;
 231
 232         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 233                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 234
 235                 if (bdiv->div == div)
 236                         return bdiv->val;
 237         }
 238
 239         return -EINVAL;
 240 }
 241
 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 243                                   unsigned int oversample_rate,
 244                                   unsigned int module_rate,
 245                                   unsigned int sampling_rate)
 246 {
 247         int div = module_rate / sampling_rate / oversample_rate;
 248         int i;
 249
 250         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 251                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 252
 253                 if (mdiv->div == div)
 254                         return mdiv->val;
 255         }
 256
 257         return -EINVAL;
 258 }
 259
 260 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 261 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 262 {
 263         int i;
 264
 265         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 266                 if (sun4i_i2s_oversample_rates[i] == oversample)
 267                         return true;
 268
 269         return false;
 270 }
 271
 272 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
 273                                   unsigned int rate,
 274                                   unsigned int word_size)
 275 {
 276         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 277         unsigned int oversample_rate, clk_rate;
 278         int bclk_div, mclk_div;
 279         int ret;
 280
 281         switch (rate) {
 282         case 176400:
 283         case 88200:
 284         case 44100:
 285         case 22050:
 286         case 11025:
 287                 clk_rate = 22579200;
 288                 break;
 289
 290         case 192000:
 291         case 128000:
 292         case 96000:
 293         case 64000:
 294         case 48000:
 295         case 32000:
 296         case 24000:
 297         case 16000:
 298         case 12000:
 299         case 8000:
 300                 clk_rate = 24576000;
 301                 break;
 302
 303         default:
 304                 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
 305                 return -EINVAL;
 306         }
 307
 308         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 309         if (ret)
 310                 return ret;
 311
 312         oversample_rate = i2s->mclk_freq / rate;
 313         if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
 314                 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
 315                         oversample_rate);
 316                 return -EINVAL;
 317         }
 318
 319         bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
 320                                           word_size);
 321         if (bclk_div < 0) {
 322                 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
 323                 return -EINVAL;
 324         }
 325
 326         mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
 327                                           clk_rate, rate);
 328         if (mclk_div < 0) {
 329                 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
 330                 return -EINVAL;
 331         }
 332
 333         /* Adjust the clock division values if needed */
 334         bclk_div += i2s->variant->bclk_offset;
 335         mclk_div += i2s->variant->mclk_offset;
 336
 337         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 338                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 339                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 340
 341         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 342
 343         /* Set sync period */
 344         if (i2s->variant->has_fmt_set_lrck_period)
 345                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 346                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 347                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 348
 349         return 0;
 350 }
 351
 352 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 353                                struct snd_pcm_hw_params *params,
 354                                struct snd_soc_dai *dai)
 355 {
 356         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 357         int sr, wss, channels;
 358         u32 width;
 359
 360         channels = params_channels(params);
 361         if (channels != 2) {
 362                 dev_err(dai->dev, "Unsupported number of channels: %d\n",
 363                         channels);
 364                 return -EINVAL;
 365         }
 366
 367         if (i2s->variant->has_chcfg) {
 368                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 369                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 370                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 371                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 372                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 373                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 374         }
 375
 376         /* Map the channels for playback and capture */
 377         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 378         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 379
 380         /* Configure the channels */
 381         regmap_field_write(i2s->field_txchansel,
 382                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 383
 384         regmap_field_write(i2s->field_rxchansel,
 385                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 386
 387         if (i2s->variant->has_chsel_tx_chen)
 388                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 389                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 390                                    SUN8I_I2S_TX_CHAN_EN(channels));
 391
 392         switch (params_physical_width(params)) {
 393         case 16:
 394                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 395                 break;
 396         default:
 397                 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
 398                         params_physical_width(params));
 399                 return -EINVAL;
 400         }
 401         i2s->playback_dma_data.addr_width = width;
 402
 403         switch (params_width(params)) {
 404         case 16:
 405                 sr = 0;
 406                 wss = 0;
 407                 break;
 408
 409         default:
 410                 dev_err(dai->dev, "Unsupported sample width: %d\n",
 411                         params_width(params));
 412                 return -EINVAL;
 413         }
 414
 415         regmap_field_write(i2s->field_fmt_wss,
 416                            wss + i2s->variant->fmt_offset);
 417         regmap_field_write(i2s->field_fmt_sr,
 418                            sr + i2s->variant->fmt_offset);
 419
 420         return sun4i_i2s_set_clk_rate(dai, params_rate(params),
 421                                       params_width(params));
 422 }
 423
 424 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 425 {
 426         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 427         u32 val;
 428         u32 offset = 0;
 429         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 430         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 431
 432         /* DAI Mode */
 433         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 434         case SND_SOC_DAIFMT_I2S:
 435                 val = SUN4I_I2S_FMT0_FMT_I2S;
 436                 offset = 1;
 437                 break;
 438         case SND_SOC_DAIFMT_LEFT_J:
 439                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 440                 break;
 441         case SND_SOC_DAIFMT_RIGHT_J:
 442                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 443                 break;
 444         default:
 445                 dev_err(dai->dev, "Unsupported format: %d\n",
 446                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 447                 return -EINVAL;
 448         }
 449
 450         if (i2s->variant->has_chsel_offset) {
 451                 /*
 452                  * offset being set indicates that we're connected to an i2s
 453                  * device, however offset is only used on the sun8i block and
 454                  * i2s shares the same setting with the LJ format. Increment
 455                  * val so that the bit to value to write is correct.
 456                  */
 457                 if (offset > 0)
 458                         val++;
 459                 /* blck offset determines whether i2s or LJ */
 460                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 461                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 462                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 463         }
 464
 465         regmap_field_write(i2s->field_fmt_mode, val);
 466
 467         /* DAI clock polarity */
 468         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 469         case SND_SOC_DAIFMT_IB_IF:
 470                 /* Invert both clocks */
 471                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 472                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 473                 break;
 474         case SND_SOC_DAIFMT_IB_NF:
 475                 /* Invert bit clock */
 476                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 477                 break;
 478         case SND_SOC_DAIFMT_NB_IF:
 479                 /* Invert frame clock */
 480                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 481                 break;
 482         case SND_SOC_DAIFMT_NB_NF:
 483                 break;
 484         default:
 485                 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
 486                         fmt & SND_SOC_DAIFMT_INV_MASK);
 487                 return -EINVAL;
 488         }
 489
 490         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 491         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 492
 493         if (i2s->variant->has_slave_select_bit) {
 494                 /* DAI clock master masks */
 495                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 496                 case SND_SOC_DAIFMT_CBS_CFS:
 497                         /* BCLK and LRCLK master */
 498                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 499                         break;
 500                 case SND_SOC_DAIFMT_CBM_CFM:
 501                         /* BCLK and LRCLK slave */
 502                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 503                         break;
 504                 default:
 505                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 506                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 507                         return -EINVAL;
 508                 }
 509                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 510                                    SUN4I_I2S_CTRL_MODE_MASK,
 511                                    val);
 512         } else {
 513                 /*
 514                  * The newer i2s block does not have a slave select bit,
 515                  * instead the clk pins are configured as inputs.
 516                  */
 517                 /* DAI clock master masks */
 518                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 519                 case SND_SOC_DAIFMT_CBS_CFS:
 520                         /* BCLK and LRCLK master */
 521                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 522                                 SUN8I_I2S_CTRL_LRCK_OUT;
 523                         break;
 524                 case SND_SOC_DAIFMT_CBM_CFM:
 525                         /* BCLK and LRCLK slave */
 526                         val = 0;
 527                         break;
 528                 default:
 529                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 530                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 531                         return -EINVAL;
 532                 }
 533                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 534                                    SUN8I_I2S_CTRL_BCLK_OUT |
 535                                    SUN8I_I2S_CTRL_LRCK_OUT,
 536                                    val);
 537         }
 538
 539         /* Set significant bits in our FIFOs */
 540         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 541                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 542                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 543                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 544                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 545         return 0;
 546 }
 547
 548 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 549 {
 550         /* Flush RX FIFO */
 551         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 552                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 553                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 554
 555         /* Clear RX counter */
 556         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 557
 558         /* Enable RX Block */
 559         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 560                            SUN4I_I2S_CTRL_RX_EN,
 561                            SUN4I_I2S_CTRL_RX_EN);
 562
 563         /* Enable RX DRQ */
 564         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 565                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 566                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 567 }
 568
 569 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 570 {
 571         /* Flush TX FIFO */
 572         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 573                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 574                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 575
 576         /* Clear TX counter */
 577         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 578
 579         /* Enable TX Block */
 580         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 581                            SUN4I_I2S_CTRL_TX_EN,
 582                            SUN4I_I2S_CTRL_TX_EN);
 583
 584         /* Enable TX DRQ */
 585         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 586                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 587                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 588 }
 589
 590 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 591 {
 592         /* Disable RX Block */
 593         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 594                            SUN4I_I2S_CTRL_RX_EN,
 595                            0);
 596
 597         /* Disable RX DRQ */
 598         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 599                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 600                            0);
 601 }
 602
 603 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 604 {
 605         /* Disable TX Block */
 606         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 607                            SUN4I_I2S_CTRL_TX_EN,
 608                            0);
 609
 610         /* Disable TX DRQ */
 611         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 612                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 613                            0);
 614 }
 615
 616 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 617                              struct snd_soc_dai *dai)
 618 {
 619         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 620
 621         switch (cmd) {
 622         case SNDRV_PCM_TRIGGER_START:
 623         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 624         case SNDRV_PCM_TRIGGER_RESUME:
 625                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 626                         sun4i_i2s_start_playback(i2s);
 627                 else
 628                         sun4i_i2s_start_capture(i2s);
 629                 break;
 630
 631         case SNDRV_PCM_TRIGGER_STOP:
 632         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 633         case SNDRV_PCM_TRIGGER_SUSPEND:
 634                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 635                         sun4i_i2s_stop_playback(i2s);
 636                 else
 637                         sun4i_i2s_stop_capture(i2s);
 638                 break;
 639
 640         default:
 641                 return -EINVAL;
 642         }
 643
 644         return 0;
 645 }
 646
 647 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 648                                 unsigned int freq, int dir)
 649 {
 650         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 651
 652         if (clk_id != 0)
 653                 return -EINVAL;
 654
 655         i2s->mclk_freq = freq;
 656
 657         return 0;
 658 }
 659
 660 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 661         .hw_params      = sun4i_i2s_hw_params,
 662         .set_fmt        = sun4i_i2s_set_fmt,
 663         .set_sysclk     = sun4i_i2s_set_sysclk,
 664         .trigger        = sun4i_i2s_trigger,
 665 };
 666
 667 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 668 {
 669         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 670
 671         snd_soc_dai_init_dma_data(dai,
 672                                   &i2s->playback_dma_data,
 673                                   &i2s->capture_dma_data);
 674
 675         snd_soc_dai_set_drvdata(dai, i2s);
 676
 677         return 0;
 678 }
 679
 680 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 681         .probe = sun4i_i2s_dai_probe,
 682         .capture = {
 683                 .stream_name = "Capture",
 684                 .channels_min = 2,
 685                 .channels_max = 2,
 686                 .rates = SNDRV_PCM_RATE_8000_192000,
 687                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 688         },
 689         .playback = {
 690                 .stream_name = "Playback",
 691                 .channels_min = 2,
 692                 .channels_max = 2,
 693                 .rates = SNDRV_PCM_RATE_8000_192000,
 694                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 695         },
 696         .ops = &sun4i_i2s_dai_ops,
 697         .symmetric_rates = 1,
 698 };
 699
 700 static const struct snd_soc_component_driver sun4i_i2s_component = {
 701         .name   = "sun4i-dai",
 702 };
 703
 704 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 705 {
 706         switch (reg) {
 707         case SUN4I_I2S_FIFO_TX_REG:
 708                 return false;
 709
 710         default:
 711                 return true;
 712         }
 713 }
 714
 715 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 716 {
 717         switch (reg) {
 718         case SUN4I_I2S_FIFO_RX_REG:
 719         case SUN4I_I2S_FIFO_STA_REG:
 720                 return false;
 721
 722         default:
 723                 return true;
 724         }
 725 }
 726
 727 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 728 {
 729         switch (reg) {
 730         case SUN4I_I2S_FIFO_RX_REG:
 731         case SUN4I_I2S_INT_STA_REG:
 732         case SUN4I_I2S_RX_CNT_REG:
 733         case SUN4I_I2S_TX_CNT_REG:
 734                 return true;
 735
 736         default:
 737                 return false;
 738         }
 739 }
 740
 741 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 742 {
 743         switch (reg) {
 744         case SUN8I_I2S_FIFO_TX_REG:
 745                 return false;
 746
 747         default:
 748                 return true;
 749         }
 750 }
 751
 752 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 753 {
 754         if (reg == SUN8I_I2S_INT_STA_REG)
 755                 return true;
 756         if (reg == SUN8I_I2S_FIFO_TX_REG)
 757                 return false;
 758
 759         return sun4i_i2s_volatile_reg(dev, reg);
 760 }
 761
 762 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 763         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 764         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 765         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 766         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 767         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 768         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 769         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 770         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 771         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 772         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 773 };
 774
 775 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 776         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 777         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 778         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 779         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 780         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 781         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 782         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 783         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 784         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 785         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 786         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 787 };
 788
 789 static const struct regmap_config sun4i_i2s_regmap_config = {
 790         .reg_bits       = 32,
 791         .reg_stride     = 4,
 792         .val_bits       = 32,
 793         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 794
 795         .cache_type     = REGCACHE_FLAT,
 796         .reg_defaults   = sun4i_i2s_reg_defaults,
 797         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 798         .writeable_reg  = sun4i_i2s_wr_reg,
 799         .readable_reg   = sun4i_i2s_rd_reg,
 800         .volatile_reg   = sun4i_i2s_volatile_reg,
 801 };
 802
 803 static const struct regmap_config sun8i_i2s_regmap_config = {
 804         .reg_bits       = 32,
 805         .reg_stride     = 4,
 806         .val_bits       = 32,
 807         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 808         .cache_type     = REGCACHE_FLAT,
 809         .reg_defaults   = sun8i_i2s_reg_defaults,
 810         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 811         .writeable_reg  = sun4i_i2s_wr_reg,
 812         .readable_reg   = sun8i_i2s_rd_reg,
 813         .volatile_reg   = sun8i_i2s_volatile_reg,
 814 };
 815
 816 static int sun4i_i2s_runtime_resume(struct device *dev)
 817 {
 818         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 819         int ret;
 820
 821         ret = clk_prepare_enable(i2s->bus_clk);
 822         if (ret) {
 823                 dev_err(dev, "Failed to enable bus clock\n");
 824                 return ret;
 825         }
 826
 827         regcache_cache_only(i2s->regmap, false);
 828         regcache_mark_dirty(i2s->regmap);
 829
 830         ret = regcache_sync(i2s->regmap);
 831         if (ret) {
 832                 dev_err(dev, "Failed to sync regmap cache\n");
 833                 goto err_disable_clk;
 834         }
 835
 836         /* Enable the whole hardware block */
 837         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 838                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 839
 840         /* Enable the first output line */
 841         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 842                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 843                            SUN4I_I2S_CTRL_SDO_EN(0));
 844
 845         ret = clk_prepare_enable(i2s->mod_clk);
 846         if (ret) {
 847                 dev_err(dev, "Failed to enable module clock\n");
 848                 goto err_disable_clk;
 849         }
 850
 851         return 0;
 852
 853 err_disable_clk:
 854         clk_disable_unprepare(i2s->bus_clk);
 855         return ret;
 856 }
 857
 858 static int sun4i_i2s_runtime_suspend(struct device *dev)
 859 {
 860         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 861
 862         clk_disable_unprepare(i2s->mod_clk);
 863
 864         /* Disable our output lines */
 865         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 866                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 867
 868         /* Disable the whole hardware block */
 869         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 870                            SUN4I_I2S_CTRL_GL_EN, 0);
 871
 872         regcache_cache_only(i2s->regmap, true);
 873
 874         clk_disable_unprepare(i2s->bus_clk);
 875
 876         return 0;
 877 }
 878
 879 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 880         .has_reset              = false,
 881         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 882         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 883         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 884         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 885         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 886         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 887         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 888         .has_slave_select_bit   = true,
 889         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 890         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 891         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 892         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 893         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 894 };
 895
 896 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 897         .has_reset              = true,
 898         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 899         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 900         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 901         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 902         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 903         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 904         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 905         .has_slave_select_bit   = true,
 906         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 907         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 908         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 909         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 910         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 911 };
 912
 913 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
 914         .has_reset              = true,
 915         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 916         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 917         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 918         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 919         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 920         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 921         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 922         .has_slave_select_bit   = true,
 923         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 924         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 925         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 926         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 927         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 928 };
 929
 930 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 931         .has_reset              = true,
 932         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 933         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 934         .mclk_offset            = 1,
 935         .bclk_offset            = 2,
 936         .fmt_offset             = 3,
 937         .has_fmt_set_lrck_period = true,
 938         .has_chcfg              = true,
 939         .has_chsel_tx_chen      = true,
 940         .has_chsel_offset       = true,
 941         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 942         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 943         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 944         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 945         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 946         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 947         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 948         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 949         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 950         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 951 };
 952
 953 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
 954         .has_reset              = true,
 955         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 956         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 957         .has_slave_select_bit   = true,
 958         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 959         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 960         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 961         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 962         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 963         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 964         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 965         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 966         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 967         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 968 };
 969
 970 static int sun4i_i2s_init_regmap_fields(struct device *dev,
 971                                         struct sun4i_i2s *i2s)
 972 {
 973         i2s->field_clkdiv_mclk_en =
 974                 devm_regmap_field_alloc(dev, i2s->regmap,
 975                                         i2s->variant->field_clkdiv_mclk_en);
 976         if (IS_ERR(i2s->field_clkdiv_mclk_en))
 977                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
 978
 979         i2s->field_fmt_wss =
 980                         devm_regmap_field_alloc(dev, i2s->regmap,
 981                                                 i2s->variant->field_fmt_wss);
 982         if (IS_ERR(i2s->field_fmt_wss))
 983                 return PTR_ERR(i2s->field_fmt_wss);
 984
 985         i2s->field_fmt_sr =
 986                         devm_regmap_field_alloc(dev, i2s->regmap,
 987                                                 i2s->variant->field_fmt_sr);
 988         if (IS_ERR(i2s->field_fmt_sr))
 989                 return PTR_ERR(i2s->field_fmt_sr);
 990
 991         i2s->field_fmt_bclk =
 992                         devm_regmap_field_alloc(dev, i2s->regmap,
 993                                                 i2s->variant->field_fmt_bclk);
 994         if (IS_ERR(i2s->field_fmt_bclk))
 995                 return PTR_ERR(i2s->field_fmt_bclk);
 996
 997         i2s->field_fmt_lrclk =
 998                         devm_regmap_field_alloc(dev, i2s->regmap,
 999                                                 i2s->variant->field_fmt_lrclk);
1000         if (IS_ERR(i2s->field_fmt_lrclk))
1001                 return PTR_ERR(i2s->field_fmt_lrclk);
1002
1003         i2s->field_fmt_mode =
1004                         devm_regmap_field_alloc(dev, i2s->regmap,
1005                                                 i2s->variant->field_fmt_mode);
1006         if (IS_ERR(i2s->field_fmt_mode))
1007                 return PTR_ERR(i2s->field_fmt_mode);
1008
1009         i2s->field_txchanmap =
1010                         devm_regmap_field_alloc(dev, i2s->regmap,
1011                                                 i2s->variant->field_txchanmap);
1012         if (IS_ERR(i2s->field_txchanmap))
1013                 return PTR_ERR(i2s->field_txchanmap);
1014
1015         i2s->field_rxchanmap =
1016                         devm_regmap_field_alloc(dev, i2s->regmap,
1017                                                 i2s->variant->field_rxchanmap);
1018         if (IS_ERR(i2s->field_rxchanmap))
1019                 return PTR_ERR(i2s->field_rxchanmap);
1020
1021         i2s->field_txchansel =
1022                         devm_regmap_field_alloc(dev, i2s->regmap,
1023                                                 i2s->variant->field_txchansel);
1024         if (IS_ERR(i2s->field_txchansel))
1025                 return PTR_ERR(i2s->field_txchansel);
1026
1027         i2s->field_rxchansel =
1028                         devm_regmap_field_alloc(dev, i2s->regmap,
1029                                                 i2s->variant->field_rxchansel);
1030         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1031 }
1032
1033 static int sun4i_i2s_probe(struct platform_device *pdev)
1034 {
1035         struct sun4i_i2s *i2s;
1036         struct resource *res;
1037         void __iomem *regs;
1038         int irq, ret;
1039
1040         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1041         if (!i2s)
1042                 return -ENOMEM;
1043         platform_set_drvdata(pdev, i2s);
1044
1045         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046         regs = devm_ioremap_resource(&pdev->dev, res);
1047         if (IS_ERR(regs))
1048                 return PTR_ERR(regs);
1049
1050         irq = platform_get_irq(pdev, 0);
1051         if (irq < 0) {
1052                 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1053                 return irq;
1054         }
1055
1056         i2s->variant = of_device_get_match_data(&pdev->dev);
1057         if (!i2s->variant) {
1058                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1059                 return -ENODEV;
1060         }
1061
1062         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1063         if (IS_ERR(i2s->bus_clk)) {
1064                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1065                 return PTR_ERR(i2s->bus_clk);
1066         }
1067
1068         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1069                                             i2s->variant->sun4i_i2s_regmap);
1070         if (IS_ERR(i2s->regmap)) {
1071                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1072                 return PTR_ERR(i2s->regmap);
1073         }
1074
1075         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1076         if (IS_ERR(i2s->mod_clk)) {
1077                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1078                 return PTR_ERR(i2s->mod_clk);
1079         }
1080
1081         if (i2s->variant->has_reset) {
1082                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1083                 if (IS_ERR(i2s->rst)) {
1084                         dev_err(&pdev->dev, "Failed to get reset control\n");
1085                         return PTR_ERR(i2s->rst);
1086                 }
1087         }
1088
1089         if (!IS_ERR(i2s->rst)) {
1090                 ret = reset_control_deassert(i2s->rst);
1091                 if (ret) {
1092                         dev_err(&pdev->dev,
1093                                 "Failed to deassert the reset control\n");
1094                         return -EINVAL;
1095                 }
1096         }
1097
1098         i2s->playback_dma_data.addr = res->start +
1099                                         i2s->variant->reg_offset_txdata;
1100         i2s->playback_dma_data.maxburst = 8;
1101
1102         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1103         i2s->capture_dma_data.maxburst = 8;
1104
1105         pm_runtime_enable(&pdev->dev);
1106         if (!pm_runtime_enabled(&pdev->dev)) {
1107                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1108                 if (ret)
1109                         goto err_pm_disable;
1110         }
1111
1112         ret = devm_snd_soc_register_component(&pdev->dev,
1113                                               &sun4i_i2s_component,
1114                                               &sun4i_i2s_dai, 1);
1115         if (ret) {
1116                 dev_err(&pdev->dev, "Could not register DAI\n");
1117                 goto err_suspend;
1118         }
1119
1120         ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1121         if (ret) {
1122                 dev_err(&pdev->dev, "Could not register PCM\n");
1123                 goto err_suspend;
1124         }
1125
1126         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1127         if (ret) {
1128                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1129                 goto err_suspend;
1130         }
1131
1132         return 0;
1133
1134 err_suspend:
1135         if (!pm_runtime_status_suspended(&pdev->dev))
1136                 sun4i_i2s_runtime_suspend(&pdev->dev);
1137 err_pm_disable:
1138         pm_runtime_disable(&pdev->dev);
1139         if (!IS_ERR(i2s->rst))
1140                 reset_control_assert(i2s->rst);
1141
1142         return ret;
1143 }
1144
1145 static int sun4i_i2s_remove(struct platform_device *pdev)
1146 {
1147         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1148
1149         snd_dmaengine_pcm_unregister(&pdev->dev);
1150
1151         pm_runtime_disable(&pdev->dev);
1152         if (!pm_runtime_status_suspended(&pdev->dev))
1153                 sun4i_i2s_runtime_suspend(&pdev->dev);
1154
1155         if (!IS_ERR(i2s->rst))
1156                 reset_control_assert(i2s->rst);
1157
1158         return 0;
1159 }
1160
1161 static const struct of_device_id sun4i_i2s_match[] = {
1162         {
1163                 .compatible = "allwinner,sun4i-a10-i2s",
1164                 .data = &sun4i_a10_i2s_quirks,
1165         },
1166         {
1167                 .compatible = "allwinner,sun6i-a31-i2s",
1168                 .data = &sun6i_a31_i2s_quirks,
1169         },
1170         {
1171                 .compatible = "allwinner,sun8i-a83t-i2s",
1172                 .data = &sun8i_a83t_i2s_quirks,
1173         },
1174         {
1175                 .compatible = "allwinner,sun8i-h3-i2s",
1176                 .data = &sun8i_h3_i2s_quirks,
1177         },
1178         {
1179                 .compatible = "allwinner,sun50i-a64-codec-i2s",
1180                 .data = &sun50i_a64_codec_i2s_quirks,
1181         },
1182         {}
1183 };
1184 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1185
1186 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1187         .runtime_resume         = sun4i_i2s_runtime_resume,
1188         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1189 };
1190
1191 static struct platform_driver sun4i_i2s_driver = {
1192         .probe  = sun4i_i2s_probe,
1193         .remove = sun4i_i2s_remove,
1194         .driver = {
1195                 .name           = "sun4i-i2s",
1196                 .of_match_table = sun4i_i2s_match,
1197                 .pm             = &sun4i_i2s_pm_ops,
1198         },
1199 };
1200 module_platform_driver(sun4i_i2s_driver);
1201
1202 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1203 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1204 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1205 MODULE_LICENSE("GPL");