1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
9 #define unlikely(cond) (cond)
14 #include "../../elf.h"
15 #include "../../arch.h"
16 #include "../../warn.h"
18 static unsigned char op_to_cfi_reg[][2] = {
29 static int is_x86_64(struct elf *elf)
31 switch (elf->ehdr.e_machine) {
37 WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
42 bool arch_callee_saved_reg(unsigned char reg)
69 int arch_decode_instruction(struct elf *elf, struct section *sec,
70 unsigned long offset, unsigned int maxlen,
71 unsigned int *len, unsigned char *type,
72 unsigned long *immediate, struct stack_op *op)
76 unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
77 rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
78 modrm_reg = 0, sib = 0;
80 x86_64 = is_x86_64(elf);
84 insn_init(&insn, sec->data->d_buf + offset, maxlen, x86_64);
85 insn_get_length(&insn);
87 if (!insn_complete(&insn)) {
88 WARN_FUNC("can't decode instruction", sec, offset);
95 if (insn.vex_prefix.nbytes)
98 op1 = insn.opcode.bytes[0];
99 op2 = insn.opcode.bytes[1];
101 if (insn.rex_prefix.nbytes) {
102 rex = insn.rex_prefix.bytes[0];
103 rex_w = X86_REX_W(rex) >> 3;
104 rex_r = X86_REX_R(rex) >> 2;
105 rex_x = X86_REX_X(rex) >> 1;
106 rex_b = X86_REX_B(rex);
109 if (insn.modrm.nbytes) {
110 modrm = insn.modrm.bytes[0];
111 modrm_mod = X86_MODRM_MOD(modrm);
112 modrm_reg = X86_MODRM_REG(modrm);
113 modrm_rm = X86_MODRM_RM(modrm);
117 sib = insn.sib.bytes[0];
123 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
125 /* add/sub reg, %rsp */
127 op->src.type = OP_SRC_ADD;
128 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
129 op->dest.type = OP_DEST_REG;
130 op->dest.reg = CFI_SP;
138 op->src.type = OP_SRC_REG;
139 op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
140 op->dest.type = OP_DEST_PUSH;
148 op->src.type = OP_SRC_POP;
149 op->dest.type = OP_DEST_REG;
150 op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
158 op->src.type = OP_SRC_CONST;
159 op->dest.type = OP_DEST_PUSH;
163 *type = INSN_JUMP_CONDITIONAL;
174 op->src.type = OP_SRC_AND;
175 op->src.reg = CFI_SP;
176 op->src.offset = insn.immediate.value;
177 op->dest.type = OP_DEST_REG;
178 op->dest.reg = CFI_SP;
184 else if (modrm == 0xec)
189 /* add/sub imm, %rsp */
191 op->src.type = OP_SRC_ADD;
192 op->src.reg = CFI_SP;
193 op->src.offset = insn.immediate.value * sign;
194 op->dest.type = OP_DEST_REG;
195 op->dest.reg = CFI_SP;
199 if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
203 op->src.type = OP_SRC_REG;
204 op->src.reg = CFI_SP;
205 op->dest.type = OP_DEST_REG;
206 op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
210 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
214 op->src.type = OP_SRC_REG;
215 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
216 op->dest.type = OP_DEST_REG;
217 op->dest.reg = CFI_SP;
224 (modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
226 /* mov reg, disp(%rbp) */
228 op->src.type = OP_SRC_REG;
229 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
230 op->dest.type = OP_DEST_REG_INDIRECT;
231 op->dest.reg = CFI_BP;
232 op->dest.offset = insn.displacement.value;
234 } else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
236 /* mov reg, disp(%rsp) */
238 op->src.type = OP_SRC_REG;
239 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
240 op->dest.type = OP_DEST_REG_INDIRECT;
241 op->dest.reg = CFI_SP;
242 op->dest.offset = insn.displacement.value;
248 if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
250 /* mov disp(%rbp), reg */
252 op->src.type = OP_SRC_REG_INDIRECT;
253 op->src.reg = CFI_BP;
254 op->src.offset = insn.displacement.value;
255 op->dest.type = OP_DEST_REG;
256 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
258 } else if (rex_w && !rex_b && sib == 0x24 &&
259 modrm_mod != 3 && modrm_rm == 4) {
261 /* mov disp(%rsp), reg */
263 op->src.type = OP_SRC_REG_INDIRECT;
264 op->src.reg = CFI_SP;
265 op->src.offset = insn.displacement.value;
266 op->dest.type = OP_DEST_REG;
267 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
273 if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
276 if (!insn.displacement.value) {
277 /* lea (%rsp), reg */
278 op->src.type = OP_SRC_REG;
280 /* lea disp(%rsp), reg */
281 op->src.type = OP_SRC_ADD;
282 op->src.offset = insn.displacement.value;
284 op->src.reg = CFI_SP;
285 op->dest.type = OP_DEST_REG;
286 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
288 } else if (rex == 0x48 && modrm == 0x65) {
290 /* lea disp(%rbp), %rsp */
292 op->src.type = OP_SRC_ADD;
293 op->src.reg = CFI_BP;
294 op->src.offset = insn.displacement.value;
295 op->dest.type = OP_DEST_REG;
296 op->dest.reg = CFI_SP;
298 } else if (rex == 0x49 && modrm == 0x62 &&
299 insn.displacement.value == -8) {
302 * lea -0x8(%r10), %rsp
304 * Restoring rsp back to its original value after a
308 op->src.type = OP_SRC_ADD;
309 op->src.reg = CFI_R10;
311 op->dest.type = OP_DEST_REG;
312 op->dest.reg = CFI_SP;
314 } else if (rex == 0x49 && modrm == 0x65 &&
315 insn.displacement.value == -16) {
318 * lea -0x10(%r13), %rsp
320 * Restoring rsp back to its original value after a
324 op->src.type = OP_SRC_ADD;
325 op->src.reg = CFI_R13;
326 op->src.offset = -16;
327 op->dest.type = OP_DEST_REG;
328 op->dest.reg = CFI_SP;
336 op->src.type = OP_SRC_POP;
337 op->dest.type = OP_DEST_MEM;
347 op->src.type = OP_SRC_CONST;
348 op->dest.type = OP_DEST_PUSHF;
354 op->src.type = OP_SRC_POPF;
355 op->dest.type = OP_DEST_MEM;
364 else if (modrm == 0xcb)
367 } else if (op2 >= 0x80 && op2 <= 0x8f) {
369 *type = INSN_JUMP_CONDITIONAL;
371 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
374 /* sysenter, sysret */
375 *type = INSN_CONTEXT_SWITCH;
377 } else if (op2 == 0x0b || op2 == 0xb9) {
382 } else if (op2 == 0x0d || op2 == 0x1f) {
387 } else if (op2 == 0xa0 || op2 == 0xa8) {
391 op->src.type = OP_SRC_CONST;
392 op->dest.type = OP_DEST_PUSH;
394 } else if (op2 == 0xa1 || op2 == 0xa9) {
398 op->src.type = OP_SRC_POP;
399 op->dest.type = OP_DEST_MEM;
413 op->dest.type = OP_DEST_LEAVE;
419 *type = INSN_JUMP_CONDITIONAL;
424 *type = INSN_JUMP_UNCONDITIONAL;
432 case 0xca: /* retf */
433 case 0xcb: /* retf */
434 case 0xcf: /* iret */
435 *type = INSN_CONTEXT_SWITCH;
451 if (modrm_reg == 2 || modrm_reg == 3)
453 *type = INSN_CALL_DYNAMIC;
455 else if (modrm_reg == 4)
457 *type = INSN_JUMP_DYNAMIC;
459 else if (modrm_reg == 5)
462 *type = INSN_CONTEXT_SWITCH;
464 else if (modrm_reg == 6) {
468 op->src.type = OP_SRC_CONST;
469 op->dest.type = OP_DEST_PUSH;
478 *immediate = insn.immediate.nbytes ? insn.immediate.value : 0;
483 void arch_initial_func_cfi_state(struct cfi_state *state)
487 for (i = 0; i < CFI_NUM_REGS; i++) {
488 state->regs[i].base = CFI_UNDEFINED;
489 state->regs[i].offset = 0;
492 /* initial CFA (call frame address) */
493 state->cfa.base = CFI_SP;
494 state->cfa.offset = 8;
496 /* initial RA (return address) */
497 state->regs[16].base = CFI_CFA;
498 state->regs[16].offset = -8;