1 /* SPDX-License-Identifier: GPL-2.0 */
3 * tools/testing/selftests/kvm/include/x86_64/svm.h
4 * This is a copy of arch/x86/include/asm/svm.h
8 #ifndef SELFTEST_KVM_SVM_H
9 #define SELFTEST_KVM_SVM_H
17 INTERCEPT_SELECTIVE_CR0,
41 INTERCEPT_TASK_SWITCH,
42 INTERCEPT_FERR_FREEZE,
62 struct __attribute__ ((__packed__)) vmcb_control_area {
65 u32 intercept_exceptions;
68 u16 pause_filter_thresh;
69 u16 pause_filter_count;
85 u32 exit_int_info_err;
98 u64 avic_backing_page; /* Offset 0xe0 */
99 u8 reserved_6[8]; /* Offset 0xe8 */
100 u64 avic_logical_id; /* Offset 0xf0 */
101 u64 avic_physical_id; /* Offset 0xf8 */
106 #define TLB_CONTROL_DO_NOTHING 0
107 #define TLB_CONTROL_FLUSH_ALL_ASID 1
108 #define TLB_CONTROL_FLUSH_ASID 3
109 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
111 #define V_TPR_MASK 0x0f
113 #define V_IRQ_SHIFT 8
114 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
116 #define V_GIF_SHIFT 9
117 #define V_GIF_MASK (1 << V_GIF_SHIFT)
119 #define V_INTR_PRIO_SHIFT 16
120 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
122 #define V_IGN_TPR_SHIFT 20
123 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
125 #define V_INTR_MASKING_SHIFT 24
126 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
128 #define V_GIF_ENABLE_SHIFT 25
129 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
131 #define AVIC_ENABLE_SHIFT 31
132 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
134 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
135 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
137 #define SVM_INTERRUPT_SHADOW_MASK 1
139 #define SVM_IOIO_STR_SHIFT 2
140 #define SVM_IOIO_REP_SHIFT 3
141 #define SVM_IOIO_SIZE_SHIFT 4
142 #define SVM_IOIO_ASIZE_SHIFT 7
144 #define SVM_IOIO_TYPE_MASK 1
145 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
146 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
147 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
148 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
150 #define SVM_VM_CR_VALID_MASK 0x001fULL
151 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
152 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
154 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
155 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
157 struct __attribute__ ((__packed__)) vmcb_seg {
164 struct __attribute__ ((__packed__)) vmcb_save_area {
171 struct vmcb_seg gdtr;
172 struct vmcb_seg ldtr;
173 struct vmcb_seg idtr;
209 struct __attribute__ ((__packed__)) vmcb {
210 struct vmcb_control_area control;
211 struct vmcb_save_area save;
214 #define SVM_CPUID_FUNC 0x8000000a
216 #define SVM_VM_CR_SVM_DISABLE 4
218 #define SVM_SELECTOR_S_SHIFT 4
219 #define SVM_SELECTOR_DPL_SHIFT 5
220 #define SVM_SELECTOR_P_SHIFT 7
221 #define SVM_SELECTOR_AVL_SHIFT 8
222 #define SVM_SELECTOR_L_SHIFT 9
223 #define SVM_SELECTOR_DB_SHIFT 10
224 #define SVM_SELECTOR_G_SHIFT 11
226 #define SVM_SELECTOR_TYPE_MASK (0xf)
227 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
228 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
229 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
230 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
231 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
232 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
233 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
235 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
236 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
237 #define SVM_SELECTOR_CODE_MASK (1 << 3)
239 #define INTERCEPT_CR0_READ 0
240 #define INTERCEPT_CR3_READ 3
241 #define INTERCEPT_CR4_READ 4
242 #define INTERCEPT_CR8_READ 8
243 #define INTERCEPT_CR0_WRITE (16 + 0)
244 #define INTERCEPT_CR3_WRITE (16 + 3)
245 #define INTERCEPT_CR4_WRITE (16 + 4)
246 #define INTERCEPT_CR8_WRITE (16 + 8)
248 #define INTERCEPT_DR0_READ 0
249 #define INTERCEPT_DR1_READ 1
250 #define INTERCEPT_DR2_READ 2
251 #define INTERCEPT_DR3_READ 3
252 #define INTERCEPT_DR4_READ 4
253 #define INTERCEPT_DR5_READ 5
254 #define INTERCEPT_DR6_READ 6
255 #define INTERCEPT_DR7_READ 7
256 #define INTERCEPT_DR0_WRITE (16 + 0)
257 #define INTERCEPT_DR1_WRITE (16 + 1)
258 #define INTERCEPT_DR2_WRITE (16 + 2)
259 #define INTERCEPT_DR3_WRITE (16 + 3)
260 #define INTERCEPT_DR4_WRITE (16 + 4)
261 #define INTERCEPT_DR5_WRITE (16 + 5)
262 #define INTERCEPT_DR6_WRITE (16 + 6)
263 #define INTERCEPT_DR7_WRITE (16 + 7)
265 #define SVM_EVTINJ_VEC_MASK 0xff
267 #define SVM_EVTINJ_TYPE_SHIFT 8
268 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
270 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
271 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
272 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
273 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
275 #define SVM_EVTINJ_VALID (1 << 31)
276 #define SVM_EVTINJ_VALID_ERR (1 << 11)
278 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
279 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
281 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
282 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
283 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
284 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
286 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
287 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
289 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
290 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
291 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
293 #define SVM_EXITINFO_REG_MASK 0x0F
295 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
297 #endif /* SELFTEST_KVM_SVM_H */