4 * Copyright (C) 2015,2016 ARM Ltd.
5 * Author: Andre Przywara <andre.przywara@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/cpu.h>
21 #include <linux/kvm.h>
22 #include <linux/kvm_host.h>
23 #include <linux/interrupt.h>
24 #include <linux/list.h>
25 #include <linux/uaccess.h>
27 #include <linux/irqchip/arm-gic-v3.h>
29 #include <asm/kvm_emulate.h>
30 #include <asm/kvm_arm.h>
31 #include <asm/kvm_mmu.h>
34 #include "vgic-mmio.h"
36 static int vgic_its_save_tables_v0(struct vgic_its *its);
37 static int vgic_its_restore_tables_v0(struct vgic_its *its);
38 static int vgic_its_commit_v0(struct vgic_its *its);
41 * Creates a new (reference to a) struct vgic_irq for a given LPI.
42 * If this LPI is already mapped on another ITS, we increase its refcount
43 * and return a pointer to the existing structure.
44 * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
45 * This function returns a pointer to the _unlocked_ structure.
47 static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid)
49 struct vgic_dist *dist = &kvm->arch.vgic;
50 struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
52 /* In this case there is no put, since we keep the reference. */
56 irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL);
58 return ERR_PTR(-ENOMEM);
60 INIT_LIST_HEAD(&irq->lpi_list);
61 INIT_LIST_HEAD(&irq->ap_list);
62 spin_lock_init(&irq->irq_lock);
64 irq->config = VGIC_CONFIG_EDGE;
65 kref_init(&irq->refcount);
68 spin_lock(&dist->lpi_list_lock);
71 * There could be a race with another vgic_add_lpi(), so we need to
72 * check that we don't add a second list entry with the same LPI.
74 list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) {
75 if (oldirq->intid != intid)
78 /* Someone was faster with adding this LPI, lets use that. */
83 * This increases the refcount, the caller is expected to
84 * call vgic_put_irq() on the returned pointer once it's
85 * finished with the IRQ.
87 vgic_get_irq_kref(irq);
92 list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
93 dist->lpi_list_count++;
96 spin_unlock(&dist->lpi_list_lock);
102 struct list_head dev_list;
104 /* the head for the list of ITTEs */
105 struct list_head itt_head;
106 u32 num_eventid_bits;
111 #define COLLECTION_NOT_MAPPED ((u32)~0)
113 struct its_collection {
114 struct list_head coll_list;
120 #define its_is_collection_mapped(coll) ((coll) && \
121 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
124 struct list_head ite_list;
126 struct vgic_irq *irq;
127 struct its_collection *collection;
133 * struct vgic_its_abi - ITS abi ops and settings
134 * @cte_esz: collection table entry size
135 * @dte_esz: device table entry size
136 * @ite_esz: interrupt translation table entry size
137 * @save tables: save the ITS tables into guest RAM
138 * @restore_tables: restore the ITS internal structs from tables
139 * stored in guest RAM
140 * @commit: initialize the registers which expose the ABI settings,
141 * especially the entry sizes
143 struct vgic_its_abi {
147 int (*save_tables)(struct vgic_its *its);
148 int (*restore_tables)(struct vgic_its *its);
149 int (*commit)(struct vgic_its *its);
152 static const struct vgic_its_abi its_table_abi_versions[] = {
153 [0] = {.cte_esz = 8, .dte_esz = 8, .ite_esz = 8,
154 .save_tables = vgic_its_save_tables_v0,
155 .restore_tables = vgic_its_restore_tables_v0,
156 .commit = vgic_its_commit_v0,
160 #define NR_ITS_ABIS ARRAY_SIZE(its_table_abi_versions)
162 inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
164 return &its_table_abi_versions[its->abi_rev];
167 int vgic_its_set_abi(struct vgic_its *its, int rev)
169 const struct vgic_its_abi *abi;
172 abi = vgic_its_get_abi(its);
173 return abi->commit(its);
177 * Find and returns a device in the device table for an ITS.
178 * Must be called with the its_lock mutex held.
180 static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
182 struct its_device *device;
184 list_for_each_entry(device, &its->device_list, dev_list)
185 if (device_id == device->device_id)
192 * Find and returns an interrupt translation table entry (ITTE) for a given
193 * Device ID/Event ID pair on an ITS.
194 * Must be called with the its_lock mutex held.
196 static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
199 struct its_device *device;
202 device = find_its_device(its, device_id);
206 list_for_each_entry(ite, &device->itt_head, ite_list)
207 if (ite->event_id == event_id)
213 /* To be used as an iterator this macro misses the enclosing parentheses */
214 #define for_each_lpi_its(dev, ite, its) \
215 list_for_each_entry(dev, &(its)->device_list, dev_list) \
216 list_for_each_entry(ite, &(dev)->itt_head, ite_list)
219 * We only implement 48 bits of PA at the moment, although the ITS
220 * supports more. Let's be restrictive here.
222 #define BASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16))
223 #define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12))
224 #define PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16))
225 #define PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12))
227 #define GIC_LPI_OFFSET 8192
229 #define VITS_TYPER_IDBITS 16
230 #define VITS_TYPER_DEVBITS 16
233 * Finds and returns a collection in the ITS collection table.
234 * Must be called with the its_lock mutex held.
236 static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
238 struct its_collection *collection;
240 list_for_each_entry(collection, &its->collection_list, coll_list) {
241 if (coll_id == collection->collection_id)
248 #define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED)
249 #define LPI_PROP_PRIORITY(p) ((p) & 0xfc)
252 * Reads the configuration data for a given LPI from guest memory and
253 * updates the fields in struct vgic_irq.
254 * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
255 * VCPU. Unconditionally applies if filter_vcpu is NULL.
257 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
258 struct kvm_vcpu *filter_vcpu)
260 u64 propbase = PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
264 ret = kvm_read_guest(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
270 spin_lock(&irq->irq_lock);
272 if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
273 irq->priority = LPI_PROP_PRIORITY(prop);
274 irq->enabled = LPI_PROP_ENABLE_BIT(prop);
276 vgic_queue_irq_unlock(kvm, irq);
278 spin_unlock(&irq->irq_lock);
285 * Create a snapshot of the current LPI list, so that we can enumerate all
286 * LPIs without holding any lock.
287 * Returns the array length and puts the kmalloc'ed array into intid_ptr.
289 static int vgic_copy_lpi_list(struct kvm *kvm, u32 **intid_ptr)
291 struct vgic_dist *dist = &kvm->arch.vgic;
292 struct vgic_irq *irq;
294 int irq_count = dist->lpi_list_count, i = 0;
297 * We use the current value of the list length, which may change
298 * after the kmalloc. We don't care, because the guest shouldn't
299 * change anything while the command handling is still running,
300 * and in the worst case we would miss a new IRQ, which one wouldn't
301 * expect to be covered by this command anyway.
303 intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
307 spin_lock(&dist->lpi_list_lock);
308 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
309 /* We don't need to "get" the IRQ, as we hold the list lock. */
310 intids[i] = irq->intid;
311 if (++i == irq_count)
314 spin_unlock(&dist->lpi_list_lock);
321 * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
322 * is targeting) to the VGIC's view, which deals with target VCPUs.
323 * Needs to be called whenever either the collection for a LPIs has
324 * changed or the collection itself got retargeted.
326 static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
328 struct kvm_vcpu *vcpu;
330 if (!its_is_collection_mapped(ite->collection))
333 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
335 spin_lock(&ite->irq->irq_lock);
336 ite->irq->target_vcpu = vcpu;
337 spin_unlock(&ite->irq->irq_lock);
341 * Updates the target VCPU for every LPI targeting this collection.
342 * Must be called with the its_lock mutex held.
344 static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
345 struct its_collection *coll)
347 struct its_device *device;
350 for_each_lpi_its(device, ite, its) {
351 if (!ite->collection || coll != ite->collection)
354 update_affinity_ite(kvm, ite);
358 static u32 max_lpis_propbaser(u64 propbaser)
360 int nr_idbits = (propbaser & 0x1f) + 1;
362 return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
366 * Scan the whole LPI pending table and sync the pending bit in there
367 * with our own data structures. This relies on the LPI being
370 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
372 gpa_t pendbase = PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
373 struct vgic_irq *irq;
374 int last_byte_offset = -1;
379 nr_irqs = vgic_copy_lpi_list(vcpu->kvm, &intids);
383 for (i = 0; i < nr_irqs; i++) {
384 int byte_offset, bit_nr;
387 byte_offset = intids[i] / BITS_PER_BYTE;
388 bit_nr = intids[i] % BITS_PER_BYTE;
391 * For contiguously allocated LPIs chances are we just read
392 * this very same byte in the last iteration. Reuse that.
394 if (byte_offset != last_byte_offset) {
395 ret = kvm_read_guest(vcpu->kvm, pendbase + byte_offset,
401 last_byte_offset = byte_offset;
404 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
405 spin_lock(&irq->irq_lock);
406 irq->pending_latch = pendmask & (1U << bit_nr);
407 vgic_queue_irq_unlock(vcpu->kvm, irq);
408 vgic_put_irq(vcpu->kvm, irq);
416 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
417 struct vgic_its *its,
418 gpa_t addr, unsigned int len)
420 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
421 u64 reg = GITS_TYPER_PLPIS;
424 * We use linear CPU numbers for redistributor addressing,
425 * so GITS_TYPER.PTA is 0.
426 * Also we force all PROPBASER registers to be the same, so
427 * CommonLPIAff is 0 as well.
428 * To avoid memory waste in the guest, we keep the number of IDBits and
429 * DevBits low - as least for the time being.
431 reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
432 reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
433 reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
435 return extract_bytes(reg, addr & 7, len);
438 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
439 struct vgic_its *its,
440 gpa_t addr, unsigned int len)
444 val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
445 val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
449 static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
450 struct vgic_its *its,
451 gpa_t addr, unsigned int len,
454 u32 rev = GITS_IIDR_REV(val);
456 if (rev >= NR_ITS_ABIS)
458 return vgic_its_set_abi(its, rev);
461 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
462 struct vgic_its *its,
463 gpa_t addr, unsigned int len)
465 switch (addr & 0xffff) {
467 return 0x92; /* part number, bits[7:0] */
469 return 0xb4; /* part number, bits[11:8] */
471 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
473 return 0x40; /* This is a 64K software visible page */
474 /* The following are the ID registers for (any) GIC. */
489 * Find the target VCPU and the LPI number for a given devid/eventid pair
490 * and make this IRQ pending, possibly injecting it.
491 * Must be called with the its_lock mutex held.
492 * Returns 0 on success, a positive error value for any ITS mapping
493 * related errors and negative error values for generic errors.
495 static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
496 u32 devid, u32 eventid)
498 struct kvm_vcpu *vcpu;
504 ite = find_ite(its, devid, eventid);
505 if (!ite || !its_is_collection_mapped(ite->collection))
506 return E_ITS_INT_UNMAPPED_INTERRUPT;
508 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
510 return E_ITS_INT_UNMAPPED_INTERRUPT;
512 if (!vcpu->arch.vgic_cpu.lpis_enabled)
515 spin_lock(&ite->irq->irq_lock);
516 ite->irq->pending_latch = true;
517 vgic_queue_irq_unlock(kvm, ite->irq);
522 static struct vgic_io_device *vgic_get_its_iodev(struct kvm_io_device *dev)
524 struct vgic_io_device *iodev;
526 if (dev->ops != &kvm_io_gic_ops)
529 iodev = container_of(dev, struct vgic_io_device, dev);
531 if (iodev->iodev_type != IODEV_ITS)
538 * Queries the KVM IO bus framework to get the ITS pointer from the given
540 * We then call vgic_its_trigger_msi() with the decoded data.
541 * According to the KVM_SIGNAL_MSI API description returns 1 on success.
543 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
546 struct kvm_io_device *kvm_io_dev;
547 struct vgic_io_device *iodev;
550 if (!vgic_has_its(kvm))
553 if (!(msi->flags & KVM_MSI_VALID_DEVID))
556 address = (u64)msi->address_hi << 32 | msi->address_lo;
558 kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
562 iodev = vgic_get_its_iodev(kvm_io_dev);
566 mutex_lock(&iodev->its->its_lock);
567 ret = vgic_its_trigger_msi(kvm, iodev->its, msi->devid, msi->data);
568 mutex_unlock(&iodev->its->its_lock);
574 * KVM_SIGNAL_MSI demands a return value > 0 for success and 0
575 * if the guest has blocked the MSI. So we map any LPI mapping
576 * related error to that.
584 /* Requires the its_lock to be held. */
585 static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
587 list_del(&ite->ite_list);
589 /* This put matches the get in vgic_add_lpi. */
591 vgic_put_irq(kvm, ite->irq);
596 static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
598 return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
601 #define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
602 #define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
603 #define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
604 #define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
605 #define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
606 #define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
607 #define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8)
608 #define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
609 #define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
612 * The DISCARD command frees an Interrupt Translation Table Entry (ITTE).
613 * Must be called with the its_lock mutex held.
615 static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
618 u32 device_id = its_cmd_get_deviceid(its_cmd);
619 u32 event_id = its_cmd_get_id(its_cmd);
623 ite = find_ite(its, device_id, event_id);
624 if (ite && ite->collection) {
626 * Though the spec talks about removing the pending state, we
627 * don't bother here since we clear the ITTE anyway and the
628 * pending state is a property of the ITTE struct.
630 its_free_ite(kvm, ite);
634 return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
638 * The MOVI command moves an ITTE to a different collection.
639 * Must be called with the its_lock mutex held.
641 static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
644 u32 device_id = its_cmd_get_deviceid(its_cmd);
645 u32 event_id = its_cmd_get_id(its_cmd);
646 u32 coll_id = its_cmd_get_collection(its_cmd);
647 struct kvm_vcpu *vcpu;
649 struct its_collection *collection;
651 ite = find_ite(its, device_id, event_id);
653 return E_ITS_MOVI_UNMAPPED_INTERRUPT;
655 if (!its_is_collection_mapped(ite->collection))
656 return E_ITS_MOVI_UNMAPPED_COLLECTION;
658 collection = find_collection(its, coll_id);
659 if (!its_is_collection_mapped(collection))
660 return E_ITS_MOVI_UNMAPPED_COLLECTION;
662 ite->collection = collection;
663 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
665 spin_lock(&ite->irq->irq_lock);
666 ite->irq->target_vcpu = vcpu;
667 spin_unlock(&ite->irq->irq_lock);
673 * Check whether an ID can be stored into the corresponding guest table.
674 * For a direct table this is pretty easy, but gets a bit nasty for
675 * indirect tables. We check whether the resulting guest physical address
676 * is actually valid (covered by a memslot and guest accessible).
677 * For this we have to read the respective first level entry.
679 static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id)
681 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
682 u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
683 int esz = GITS_BASER_ENTRY_SIZE(baser);
688 case GITS_BASER_TYPE_DEVICE:
689 if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
692 case GITS_BASER_TYPE_COLLECTION:
693 /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
694 if (id >= BIT_ULL(16))
701 if (!(baser & GITS_BASER_INDIRECT)) {
704 if (id >= (l1_tbl_size / esz))
707 addr = BASER_ADDRESS(baser) + id * esz;
708 gfn = addr >> PAGE_SHIFT;
710 return kvm_is_visible_gfn(its->dev->kvm, gfn);
713 /* calculate and check the index into the 1st level */
714 index = id / (SZ_64K / esz);
715 if (index >= (l1_tbl_size / sizeof(u64)))
718 /* Each 1st level entry is represented by a 64-bit value. */
719 if (kvm_read_guest(its->dev->kvm,
720 BASER_ADDRESS(baser) + index * sizeof(indirect_ptr),
721 &indirect_ptr, sizeof(indirect_ptr)))
724 indirect_ptr = le64_to_cpu(indirect_ptr);
726 /* check the valid bit of the first level entry */
727 if (!(indirect_ptr & BIT_ULL(63)))
731 * Mask the guest physical address and calculate the frame number.
732 * Any address beyond our supported 48 bits of PA will be caught
733 * by the actual check in the final step.
735 indirect_ptr &= GENMASK_ULL(51, 16);
737 /* Find the address of the actual entry */
738 index = id % (SZ_64K / esz);
739 indirect_ptr += index * esz;
740 gfn = indirect_ptr >> PAGE_SHIFT;
742 return kvm_is_visible_gfn(its->dev->kvm, gfn);
745 static int vgic_its_alloc_collection(struct vgic_its *its,
746 struct its_collection **colp,
749 struct its_collection *collection;
751 if (!vgic_its_check_id(its, its->baser_coll_table, coll_id))
752 return E_ITS_MAPC_COLLECTION_OOR;
754 collection = kzalloc(sizeof(*collection), GFP_KERNEL);
756 collection->collection_id = coll_id;
757 collection->target_addr = COLLECTION_NOT_MAPPED;
759 list_add_tail(&collection->coll_list, &its->collection_list);
765 static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
767 struct its_collection *collection;
768 struct its_device *device;
772 * Clearing the mapping for that collection ID removes the
773 * entry from the list. If there wasn't any before, we can
776 collection = find_collection(its, coll_id);
780 for_each_lpi_its(device, ite, its)
781 if (ite->collection &&
782 ite->collection->collection_id == coll_id)
783 ite->collection = NULL;
785 list_del(&collection->coll_list);
790 * The MAPTI and MAPI commands map LPIs to ITTEs.
791 * Must be called with its_lock mutex held.
793 static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
796 u32 device_id = its_cmd_get_deviceid(its_cmd);
797 u32 event_id = its_cmd_get_id(its_cmd);
798 u32 coll_id = its_cmd_get_collection(its_cmd);
800 struct its_device *device;
801 struct its_collection *collection, *new_coll = NULL;
803 struct vgic_irq *irq;
805 device = find_its_device(its, device_id);
807 return E_ITS_MAPTI_UNMAPPED_DEVICE;
809 if (event_id >= BIT_ULL(device->num_eventid_bits))
810 return E_ITS_MAPTI_ID_OOR;
812 if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
813 lpi_nr = its_cmd_get_physical_id(its_cmd);
816 if (lpi_nr < GIC_LPI_OFFSET ||
817 lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser))
818 return E_ITS_MAPTI_PHYSICALID_OOR;
820 /* If there is an existing mapping, behavior is UNPREDICTABLE. */
821 if (find_ite(its, device_id, event_id))
824 collection = find_collection(its, coll_id);
826 int ret = vgic_its_alloc_collection(its, &collection, coll_id);
829 new_coll = collection;
832 ite = kzalloc(sizeof(struct its_ite), GFP_KERNEL);
835 vgic_its_free_collection(its, coll_id);
839 ite->event_id = event_id;
840 list_add_tail(&ite->ite_list, &device->itt_head);
842 ite->collection = collection;
845 irq = vgic_add_lpi(kvm, lpi_nr);
848 vgic_its_free_collection(its, coll_id);
849 its_free_ite(kvm, ite);
854 update_affinity_ite(kvm, ite);
857 * We "cache" the configuration table entries in out struct vgic_irq's.
858 * However we only have those structs for mapped IRQs, so we read in
859 * the respective config data from memory here upon mapping the LPI.
861 update_lpi_config(kvm, ite->irq, NULL);
866 /* Requires the its_lock to be held. */
867 static void vgic_its_unmap_device(struct kvm *kvm, struct its_device *device)
869 struct its_ite *ite, *temp;
872 * The spec says that unmapping a device with still valid
873 * ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
874 * since we cannot leave the memory unreferenced.
876 list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
877 its_free_ite(kvm, ite);
879 list_del(&device->dev_list);
884 * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
885 * Must be called with the its_lock mutex held.
887 static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
890 u32 device_id = its_cmd_get_deviceid(its_cmd);
891 bool valid = its_cmd_get_validbit(its_cmd);
892 u8 num_eventid_bits = its_cmd_get_size(its_cmd);
893 gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
894 struct its_device *device;
896 if (!vgic_its_check_id(its, its->baser_device_table, device_id))
897 return E_ITS_MAPD_DEVICE_OOR;
899 if (valid && num_eventid_bits > VITS_TYPER_IDBITS)
900 return E_ITS_MAPD_ITTSIZE_OOR;
902 device = find_its_device(its, device_id);
905 * The spec says that calling MAPD on an already mapped device
906 * invalidates all cached data for this device. We implement this
907 * by removing the mapping and re-establishing it.
910 vgic_its_unmap_device(kvm, device);
913 * The spec does not say whether unmapping a not-mapped device
914 * is an error, so we are done in any case.
919 device = kzalloc(sizeof(struct its_device), GFP_KERNEL);
923 device->device_id = device_id;
924 device->num_eventid_bits = num_eventid_bits;
925 device->itt_addr = itt_addr;
927 INIT_LIST_HEAD(&device->itt_head);
929 list_add_tail(&device->dev_list, &its->device_list);
935 * The MAPC command maps collection IDs to redistributors.
936 * Must be called with the its_lock mutex held.
938 static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its,
943 struct its_collection *collection;
946 valid = its_cmd_get_validbit(its_cmd);
947 coll_id = its_cmd_get_collection(its_cmd);
948 target_addr = its_cmd_get_target_addr(its_cmd);
950 if (target_addr >= atomic_read(&kvm->online_vcpus))
951 return E_ITS_MAPC_PROCNUM_OOR;
954 vgic_its_free_collection(its, coll_id);
956 collection = find_collection(its, coll_id);
961 ret = vgic_its_alloc_collection(its, &collection,
965 collection->target_addr = target_addr;
967 collection->target_addr = target_addr;
968 update_affinity_collection(kvm, its, collection);
976 * The CLEAR command removes the pending state for a particular LPI.
977 * Must be called with the its_lock mutex held.
979 static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
982 u32 device_id = its_cmd_get_deviceid(its_cmd);
983 u32 event_id = its_cmd_get_id(its_cmd);
987 ite = find_ite(its, device_id, event_id);
989 return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
991 ite->irq->pending_latch = false;
997 * The INV command syncs the configuration bits from the memory table.
998 * Must be called with the its_lock mutex held.
1000 static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
1003 u32 device_id = its_cmd_get_deviceid(its_cmd);
1004 u32 event_id = its_cmd_get_id(its_cmd);
1005 struct its_ite *ite;
1008 ite = find_ite(its, device_id, event_id);
1010 return E_ITS_INV_UNMAPPED_INTERRUPT;
1012 return update_lpi_config(kvm, ite->irq, NULL);
1016 * The INVALL command requests flushing of all IRQ data in this collection.
1017 * Find the VCPU mapped to that collection, then iterate over the VM's list
1018 * of mapped LPIs and update the configuration for each IRQ which targets
1019 * the specified vcpu. The configuration will be read from the in-memory
1020 * configuration table.
1021 * Must be called with the its_lock mutex held.
1023 static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its,
1026 u32 coll_id = its_cmd_get_collection(its_cmd);
1027 struct its_collection *collection;
1028 struct kvm_vcpu *vcpu;
1029 struct vgic_irq *irq;
1033 collection = find_collection(its, coll_id);
1034 if (!its_is_collection_mapped(collection))
1035 return E_ITS_INVALL_UNMAPPED_COLLECTION;
1037 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1039 irq_count = vgic_copy_lpi_list(kvm, &intids);
1043 for (i = 0; i < irq_count; i++) {
1044 irq = vgic_get_irq(kvm, NULL, intids[i]);
1047 update_lpi_config(kvm, irq, vcpu);
1048 vgic_put_irq(kvm, irq);
1057 * The MOVALL command moves the pending state of all IRQs targeting one
1058 * redistributor to another. We don't hold the pending state in the VCPUs,
1059 * but in the IRQs instead, so there is really not much to do for us here.
1060 * However the spec says that no IRQ must target the old redistributor
1061 * afterwards, so we make sure that no LPI is using the associated target_vcpu.
1062 * This command affects all LPIs in the system that target that redistributor.
1064 static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its,
1067 struct vgic_dist *dist = &kvm->arch.vgic;
1068 u32 target1_addr = its_cmd_get_target_addr(its_cmd);
1069 u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
1070 struct kvm_vcpu *vcpu1, *vcpu2;
1071 struct vgic_irq *irq;
1073 if (target1_addr >= atomic_read(&kvm->online_vcpus) ||
1074 target2_addr >= atomic_read(&kvm->online_vcpus))
1075 return E_ITS_MOVALL_PROCNUM_OOR;
1077 if (target1_addr == target2_addr)
1080 vcpu1 = kvm_get_vcpu(kvm, target1_addr);
1081 vcpu2 = kvm_get_vcpu(kvm, target2_addr);
1083 spin_lock(&dist->lpi_list_lock);
1085 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
1086 spin_lock(&irq->irq_lock);
1088 if (irq->target_vcpu == vcpu1)
1089 irq->target_vcpu = vcpu2;
1091 spin_unlock(&irq->irq_lock);
1094 spin_unlock(&dist->lpi_list_lock);
1100 * The INT command injects the LPI associated with that DevID/EvID pair.
1101 * Must be called with the its_lock mutex held.
1103 static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its,
1106 u32 msi_data = its_cmd_get_id(its_cmd);
1107 u64 msi_devid = its_cmd_get_deviceid(its_cmd);
1109 return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data);
1113 * This function is called with the its_cmd lock held, but the ITS data
1114 * structure lock dropped.
1116 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
1121 mutex_lock(&its->its_lock);
1122 switch (its_cmd_get_command(its_cmd)) {
1124 ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd);
1127 ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd);
1130 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1132 case GITS_CMD_MAPTI:
1133 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1136 ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd);
1138 case GITS_CMD_DISCARD:
1139 ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd);
1141 case GITS_CMD_CLEAR:
1142 ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd);
1144 case GITS_CMD_MOVALL:
1145 ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd);
1148 ret = vgic_its_cmd_handle_int(kvm, its, its_cmd);
1151 ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd);
1153 case GITS_CMD_INVALL:
1154 ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd);
1157 /* we ignore this command: we are in sync all of the time */
1161 mutex_unlock(&its->its_lock);
1166 static u64 vgic_sanitise_its_baser(u64 reg)
1168 reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
1169 GITS_BASER_SHAREABILITY_SHIFT,
1170 vgic_sanitise_shareability);
1171 reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
1172 GITS_BASER_INNER_CACHEABILITY_SHIFT,
1173 vgic_sanitise_inner_cacheability);
1174 reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
1175 GITS_BASER_OUTER_CACHEABILITY_SHIFT,
1176 vgic_sanitise_outer_cacheability);
1178 /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
1179 reg &= ~GENMASK_ULL(15, 12);
1181 /* We support only one (ITS) page size: 64K */
1182 reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
1187 static u64 vgic_sanitise_its_cbaser(u64 reg)
1189 reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
1190 GITS_CBASER_SHAREABILITY_SHIFT,
1191 vgic_sanitise_shareability);
1192 reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
1193 GITS_CBASER_INNER_CACHEABILITY_SHIFT,
1194 vgic_sanitise_inner_cacheability);
1195 reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
1196 GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
1197 vgic_sanitise_outer_cacheability);
1200 * Sanitise the physical address to be 64k aligned.
1201 * Also limit the physical addresses to 48 bits.
1203 reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
1208 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
1209 struct vgic_its *its,
1210 gpa_t addr, unsigned int len)
1212 return extract_bytes(its->cbaser, addr & 7, len);
1215 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
1216 gpa_t addr, unsigned int len,
1219 /* When GITS_CTLR.Enable is 1, this register is RO. */
1223 mutex_lock(&its->cmd_lock);
1224 its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
1225 its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
1228 * CWRITER is architecturally UNKNOWN on reset, but we need to reset
1229 * it to CREADR to make sure we start with an empty command buffer.
1231 its->cwriter = its->creadr;
1232 mutex_unlock(&its->cmd_lock);
1235 #define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
1236 #define ITS_CMD_SIZE 32
1237 #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
1239 /* Must be called with the cmd_lock held. */
1240 static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
1245 /* Commands are only processed when the ITS is enabled. */
1249 cbaser = CBASER_ADDRESS(its->cbaser);
1251 while (its->cwriter != its->creadr) {
1252 int ret = kvm_read_guest(kvm, cbaser + its->creadr,
1253 cmd_buf, ITS_CMD_SIZE);
1255 * If kvm_read_guest() fails, this could be due to the guest
1256 * programming a bogus value in CBASER or something else going
1257 * wrong from which we cannot easily recover.
1258 * According to section 6.3.2 in the GICv3 spec we can just
1259 * ignore that command then.
1262 vgic_its_handle_command(kvm, its, cmd_buf);
1264 its->creadr += ITS_CMD_SIZE;
1265 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
1271 * By writing to CWRITER the guest announces new commands to be processed.
1272 * To avoid any races in the first place, we take the its_cmd lock, which
1273 * protects our ring buffer variables, so that there is only one user
1274 * per ITS handling commands at a given time.
1276 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
1277 gpa_t addr, unsigned int len,
1285 mutex_lock(&its->cmd_lock);
1287 reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
1288 reg = ITS_CMD_OFFSET(reg);
1289 if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1290 mutex_unlock(&its->cmd_lock);
1295 vgic_its_process_commands(kvm, its);
1297 mutex_unlock(&its->cmd_lock);
1300 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
1301 struct vgic_its *its,
1302 gpa_t addr, unsigned int len)
1304 return extract_bytes(its->cwriter, addr & 0x7, len);
1307 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
1308 struct vgic_its *its,
1309 gpa_t addr, unsigned int len)
1311 return extract_bytes(its->creadr, addr & 0x7, len);
1314 static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
1315 struct vgic_its *its,
1316 gpa_t addr, unsigned int len,
1322 mutex_lock(&its->cmd_lock);
1329 cmd_offset = ITS_CMD_OFFSET(val);
1330 if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1335 its->creadr = cmd_offset;
1337 mutex_unlock(&its->cmd_lock);
1341 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
1342 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
1343 struct vgic_its *its,
1344 gpa_t addr, unsigned int len)
1348 switch (BASER_INDEX(addr)) {
1350 reg = its->baser_device_table;
1353 reg = its->baser_coll_table;
1360 return extract_bytes(reg, addr & 7, len);
1363 #define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
1364 static void vgic_mmio_write_its_baser(struct kvm *kvm,
1365 struct vgic_its *its,
1366 gpa_t addr, unsigned int len,
1369 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
1370 u64 entry_size, device_type;
1371 u64 reg, *regptr, clearbits = 0;
1373 /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
1377 switch (BASER_INDEX(addr)) {
1379 regptr = &its->baser_device_table;
1380 entry_size = abi->dte_esz;
1381 device_type = GITS_BASER_TYPE_DEVICE;
1384 regptr = &its->baser_coll_table;
1385 entry_size = abi->cte_esz;
1386 device_type = GITS_BASER_TYPE_COLLECTION;
1387 clearbits = GITS_BASER_INDIRECT;
1393 reg = update_64bit_reg(*regptr, addr & 7, len, val);
1394 reg &= ~GITS_BASER_RO_MASK;
1397 reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
1398 reg |= device_type << GITS_BASER_TYPE_SHIFT;
1399 reg = vgic_sanitise_its_baser(reg);
1404 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
1405 struct vgic_its *its,
1406 gpa_t addr, unsigned int len)
1410 mutex_lock(&its->cmd_lock);
1411 if (its->creadr == its->cwriter)
1412 reg |= GITS_CTLR_QUIESCENT;
1414 reg |= GITS_CTLR_ENABLE;
1415 mutex_unlock(&its->cmd_lock);
1420 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
1421 gpa_t addr, unsigned int len,
1424 mutex_lock(&its->cmd_lock);
1426 its->enabled = !!(val & GITS_CTLR_ENABLE);
1429 * Try to process any pending commands. This function bails out early
1430 * if the ITS is disabled or no commands have been queued.
1432 vgic_its_process_commands(kvm, its);
1434 mutex_unlock(&its->cmd_lock);
1437 #define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
1439 .reg_offset = off, \
1441 .access_flags = acc, \
1446 #define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
1448 .reg_offset = off, \
1450 .access_flags = acc, \
1453 .uaccess_its_write = uwr, \
1456 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
1457 gpa_t addr, unsigned int len, unsigned long val)
1462 static struct vgic_register_region its_registers[] = {
1463 REGISTER_ITS_DESC(GITS_CTLR,
1464 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
1466 REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
1467 vgic_mmio_read_its_iidr, its_mmio_write_wi,
1468 vgic_mmio_uaccess_write_its_iidr, 4,
1470 REGISTER_ITS_DESC(GITS_TYPER,
1471 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
1472 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1473 REGISTER_ITS_DESC(GITS_CBASER,
1474 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
1475 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1476 REGISTER_ITS_DESC(GITS_CWRITER,
1477 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
1478 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1479 REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
1480 vgic_mmio_read_its_creadr, its_mmio_write_wi,
1481 vgic_mmio_uaccess_write_its_creadr, 8,
1482 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1483 REGISTER_ITS_DESC(GITS_BASER,
1484 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
1485 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1486 REGISTER_ITS_DESC(GITS_IDREGS_BASE,
1487 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
1491 /* This is called on setting the LPI enable bit in the redistributor. */
1492 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
1494 if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
1495 its_sync_lpi_pending_table(vcpu);
1498 static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its)
1500 struct vgic_io_device *iodev = &its->iodev;
1503 if (!its->initialized)
1506 if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
1509 iodev->regions = its_registers;
1510 iodev->nr_regions = ARRAY_SIZE(its_registers);
1511 kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
1513 iodev->base_addr = its->vgic_its_base;
1514 iodev->iodev_type = IODEV_ITS;
1516 mutex_lock(&kvm->slots_lock);
1517 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
1518 KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
1519 mutex_unlock(&kvm->slots_lock);
1524 #define INITIAL_BASER_VALUE \
1525 (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
1526 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
1527 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
1528 GITS_BASER_PAGE_SIZE_64K)
1530 #define INITIAL_PROPBASER_VALUE \
1531 (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
1532 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
1533 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
1535 static int vgic_its_create(struct kvm_device *dev, u32 type)
1537 struct vgic_its *its;
1539 if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
1542 its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
1546 mutex_init(&its->its_lock);
1547 mutex_init(&its->cmd_lock);
1549 its->vgic_its_base = VGIC_ADDR_UNDEF;
1551 INIT_LIST_HEAD(&its->device_list);
1552 INIT_LIST_HEAD(&its->collection_list);
1554 dev->kvm->arch.vgic.has_its = true;
1555 its->initialized = false;
1556 its->enabled = false;
1559 its->baser_device_table = INITIAL_BASER_VALUE |
1560 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
1561 its->baser_coll_table = INITIAL_BASER_VALUE |
1562 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
1563 dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
1567 return vgic_its_set_abi(its, NR_ITS_ABIS - 1);
1570 static void vgic_its_destroy(struct kvm_device *kvm_dev)
1572 struct kvm *kvm = kvm_dev->kvm;
1573 struct vgic_its *its = kvm_dev->private;
1574 struct its_device *dev;
1575 struct its_ite *ite;
1576 struct list_head *dev_cur, *dev_temp;
1577 struct list_head *cur, *temp;
1580 * We may end up here without the lists ever having been initialized.
1581 * Check this and bail out early to avoid dereferencing a NULL pointer.
1583 if (!its->device_list.next)
1586 mutex_lock(&its->its_lock);
1587 list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
1588 dev = container_of(dev_cur, struct its_device, dev_list);
1589 list_for_each_safe(cur, temp, &dev->itt_head) {
1590 ite = (container_of(cur, struct its_ite, ite_list));
1591 its_free_ite(kvm, ite);
1597 list_for_each_safe(cur, temp, &its->collection_list) {
1599 kfree(container_of(cur, struct its_collection, coll_list));
1601 mutex_unlock(&its->its_lock);
1606 int vgic_its_has_attr_regs(struct kvm_device *dev,
1607 struct kvm_device_attr *attr)
1609 const struct vgic_register_region *region;
1610 gpa_t offset = attr->attr;
1613 align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7;
1618 region = vgic_find_mmio_region(its_registers,
1619 ARRAY_SIZE(its_registers),
1627 int vgic_its_attr_regs_access(struct kvm_device *dev,
1628 struct kvm_device_attr *attr,
1629 u64 *reg, bool is_write)
1631 const struct vgic_register_region *region;
1632 struct vgic_its *its;
1638 offset = attr->attr;
1641 * Although the spec supports upper/lower 32-bit accesses to
1642 * 64-bit ITS registers, the userspace ABI requires 64-bit
1643 * accesses to all 64-bit wide registers. We therefore only
1644 * support 32-bit accesses to GITS_CTLR, GITS_IIDR and GITS ID
1647 if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4))
1655 mutex_lock(&dev->kvm->lock);
1657 if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1662 region = vgic_find_mmio_region(its_registers,
1663 ARRAY_SIZE(its_registers),
1670 if (!lock_all_vcpus(dev->kvm)) {
1675 addr = its->vgic_its_base + offset;
1677 len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
1680 if (region->uaccess_its_write)
1681 ret = region->uaccess_its_write(dev->kvm, its, addr,
1684 region->its_write(dev->kvm, its, addr, len, *reg);
1686 *reg = region->its_read(dev->kvm, its, addr, len);
1688 unlock_all_vcpus(dev->kvm);
1690 mutex_unlock(&dev->kvm->lock);
1695 * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
1696 * according to v0 ABI
1698 static int vgic_its_save_tables_v0(struct vgic_its *its)
1704 * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM
1705 * to internal data structs according to V0 ABI
1708 static int vgic_its_restore_tables_v0(struct vgic_its *its)
1713 static int vgic_its_commit_v0(struct vgic_its *its)
1715 const struct vgic_its_abi *abi;
1717 abi = vgic_its_get_abi(its);
1718 its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
1719 its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
1721 its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
1722 << GITS_BASER_ENTRY_SIZE_SHIFT);
1724 its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
1725 << GITS_BASER_ENTRY_SIZE_SHIFT);
1729 static int vgic_its_has_attr(struct kvm_device *dev,
1730 struct kvm_device_attr *attr)
1732 switch (attr->group) {
1733 case KVM_DEV_ARM_VGIC_GRP_ADDR:
1734 switch (attr->attr) {
1735 case KVM_VGIC_ITS_ADDR_TYPE:
1739 case KVM_DEV_ARM_VGIC_GRP_CTRL:
1740 switch (attr->attr) {
1741 case KVM_DEV_ARM_VGIC_CTRL_INIT:
1745 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
1746 return vgic_its_has_attr_regs(dev, attr);
1751 static int vgic_its_set_attr(struct kvm_device *dev,
1752 struct kvm_device_attr *attr)
1754 struct vgic_its *its = dev->private;
1757 switch (attr->group) {
1758 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1759 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1760 unsigned long type = (unsigned long)attr->attr;
1763 if (type != KVM_VGIC_ITS_ADDR_TYPE)
1766 if (copy_from_user(&addr, uaddr, sizeof(addr)))
1769 ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
1774 its->vgic_its_base = addr;
1778 case KVM_DEV_ARM_VGIC_GRP_CTRL:
1779 switch (attr->attr) {
1780 case KVM_DEV_ARM_VGIC_CTRL_INIT:
1781 its->initialized = true;
1786 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
1787 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1790 if (get_user(reg, uaddr))
1793 return vgic_its_attr_regs_access(dev, attr, ®, true);
1799 static int vgic_its_get_attr(struct kvm_device *dev,
1800 struct kvm_device_attr *attr)
1802 switch (attr->group) {
1803 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1804 struct vgic_its *its = dev->private;
1805 u64 addr = its->vgic_its_base;
1806 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1807 unsigned long type = (unsigned long)attr->attr;
1809 if (type != KVM_VGIC_ITS_ADDR_TYPE)
1812 if (copy_to_user(uaddr, &addr, sizeof(addr)))
1816 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
1817 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1821 ret = vgic_its_attr_regs_access(dev, attr, ®, false);
1824 return put_user(reg, uaddr);
1833 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
1834 .name = "kvm-arm-vgic-its",
1835 .create = vgic_its_create,
1836 .destroy = vgic_its_destroy,
1837 .set_attr = vgic_its_set_attr,
1838 .get_attr = vgic_its_get_attr,
1839 .has_attr = vgic_its_has_attr,
1842 int kvm_vgic_register_its_device(void)
1844 return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
1845 KVM_DEV_TYPE_ARM_VGIC_ITS);
1849 * Registers all ITSes with the kvm_io_bus framework.
1850 * To follow the existing VGIC initialization sequence, this has to be
1851 * done as late as possible, just before the first VCPU runs.
1853 int vgic_register_its_iodevs(struct kvm *kvm)
1855 struct kvm_device *dev;
1858 list_for_each_entry(dev, &kvm->devices, vm_node) {
1859 if (dev->ops != &kvm_arm_vgic_its_ops)
1862 ret = vgic_register_its_iodev(kvm, dev->private);
1866 * We don't need to care about tearing down previously
1867 * registered ITSes, as the kvm_io_bus framework removes
1868 * them for us if the VM gets destroyed.