2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/irqchip/arm-gic.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_host.h>
20 #include <kvm/arm_vgic.h>
21 #include <asm/kvm_mmu.h>
26 * Call this function to convert a u64 value to an unsigned long * bitmask
27 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
29 * Warning: Calling this function may modify *val.
31 static unsigned long *u64_to_bitmask(u64 *val)
33 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
34 *val = (*val >> 32) | (*val << 32);
36 return (unsigned long *)val;
39 void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
41 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
43 if (cpuif->vgic_misr & GICH_MISR_EOI) {
44 u64 eisr = cpuif->vgic_eisr;
45 unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
48 for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
49 u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
51 WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
53 kvm_notify_acked_irq(vcpu->kvm, 0,
54 intid - VGIC_NR_PRIVATE_IRQS);
58 /* check and disable underflow maintenance IRQ */
59 cpuif->vgic_hcr &= ~GICH_HCR_UIE;
62 * In the next iterations of the vcpu loop, if we sync the
63 * vgic state after flushing it, but before entering the guest
64 * (this happens for pending signals and vmid rollovers), then
65 * make sure we don't pick up any old maintenance interrupts
71 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
73 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
75 cpuif->vgic_hcr |= GICH_HCR_UIE;
79 * transfer the content of the LRs back into the corresponding ap_list:
80 * - active bit is transferred as is
82 * - transferred as is in case of edge sensitive IRQs
83 * - set to the line-level (resample time) for level sensitive IRQs
85 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
87 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
90 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
91 u32 val = cpuif->vgic_lr[lr];
92 u32 intid = val & GICH_LR_VIRTUALID;
95 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
97 spin_lock(&irq->irq_lock);
99 /* Always preserve the active bit */
100 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
102 /* Edge is the only case where we preserve the pending bit */
103 if (irq->config == VGIC_CONFIG_EDGE &&
104 (val & GICH_LR_PENDING_BIT)) {
107 if (vgic_irq_is_sgi(intid)) {
108 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
110 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
111 irq->source |= (1 << cpuid);
116 * Clear soft pending state when level irqs have been acked.
117 * Always regenerate the pending state.
119 if (irq->config == VGIC_CONFIG_LEVEL) {
120 if (!(val & GICH_LR_PENDING_BIT))
121 irq->soft_pending = false;
123 irq->pending = irq->line_level || irq->soft_pending;
126 spin_unlock(&irq->irq_lock);
131 * Populates the particular LR with the state of a given IRQ:
132 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
133 * - for a level sensitive IRQ the pending state value is unchanged;
134 * it is dictated directly by the input level
136 * If @irq describes an SGI with multiple sources, we choose the
137 * lowest-numbered source VCPU and clear that bit in the source bitmap.
139 * The irq_lock must be held by the caller.
141 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
143 u32 val = irq->intid;
146 val |= GICH_LR_PENDING_BIT;
148 if (irq->config == VGIC_CONFIG_EDGE)
149 irq->pending = false;
151 if (vgic_irq_is_sgi(irq->intid)) {
152 u32 src = ffs(irq->source);
155 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
156 irq->source &= ~(1 << (src - 1));
163 val |= GICH_LR_ACTIVE_BIT;
167 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
169 if (irq->config == VGIC_CONFIG_LEVEL)
173 /* The GICv2 LR only holds five bits of priority. */
174 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
176 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
179 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
181 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
184 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
188 vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
189 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
190 GICH_VMCR_ALIAS_BINPOINT_MASK;
191 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
192 GICH_VMCR_BINPOINT_MASK;
193 vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
194 GICH_VMCR_PRIMASK_MASK;
196 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
199 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
201 u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
203 vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
204 GICH_VMCR_CTRL_SHIFT;
205 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
206 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
207 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
208 GICH_VMCR_BINPOINT_SHIFT;
209 vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
210 GICH_VMCR_PRIMASK_SHIFT;
213 void vgic_v2_enable(struct kvm_vcpu *vcpu)
216 * By forcing VMCR to zero, the GIC will restore the binary
217 * points to their reset values. Anything else resets to zero
220 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
221 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
223 /* Get the show on the road... */
224 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
227 /* check for overlapping regions and for regions crossing the end of memory */
228 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
230 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
232 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
235 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
237 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
243 int vgic_v2_map_resources(struct kvm *kvm)
245 struct vgic_dist *dist = &kvm->arch.vgic;
251 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
252 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
253 kvm_err("Need to set vgic cpu and dist addresses first\n");
258 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
259 kvm_err("VGIC CPU and dist frames overlap\n");
265 * Initialize the vgic if this hasn't already been done on demand by
266 * accessing the vgic state from userspace.
268 ret = vgic_init(kvm);
270 kvm_err("Unable to initialize VGIC dynamic data structures\n");
274 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
276 kvm_err("Unable to register VGIC MMIO regions\n");
280 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
281 kvm_vgic_global_state.vcpu_base,
282 KVM_VGIC_V2_CPU_SIZE, true);
284 kvm_err("Unable to remap VGIC CPU to VCPU\n");
292 kvm_vgic_destroy(kvm);
297 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
298 * @node: pointer to the DT node
300 * Returns 0 if a GICv2 has been found, returns an error code otherwise
302 int vgic_v2_probe(const struct gic_kvm_info *info)
307 if (!info->vctrl.start) {
308 kvm_err("GICH not present in the firmware table\n");
312 if (!PAGE_ALIGNED(info->vcpu.start)) {
313 kvm_err("GICV physical address 0x%llx not page aligned\n",
314 (unsigned long long)info->vcpu.start);
318 if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
319 kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
320 (unsigned long long)resource_size(&info->vcpu),
325 kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
326 resource_size(&info->vctrl));
327 if (!kvm_vgic_global_state.vctrl_base) {
328 kvm_err("Cannot ioremap GICH\n");
332 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
333 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
335 ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
336 kvm_vgic_global_state.vctrl_base +
337 resource_size(&info->vctrl),
341 kvm_err("Cannot map VCTRL into hyp\n");
342 iounmap(kvm_vgic_global_state.vctrl_base);
346 kvm_vgic_global_state.can_emulate_gicv2 = true;
347 kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
349 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
350 kvm_vgic_global_state.type = VGIC_V2;
351 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
353 kvm_info("vgic-v2@%llx\n", info->vctrl.start);