]> asedeno.scripts.mit.edu Git - linux.git/blobdiff - Documentation/devicetree/bindings/devfreq/exynos-bus.txt
Merge branches 'pm-core', 'pm-qos', 'pm-domains' and 'pm-opp'
[linux.git] / Documentation / devicetree / bindings / devfreq / exynos-bus.txt
index d3ec8e676b6bf306309b42bdd4678403a1682c82..d085ef90d27c1f8b82645177169f71c3eb42d00f 100644 (file)
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
                |--- FSYS
                |--- FSYS2
 
+- In case of Exynos5433, there is VDD_INT power line as following:
+       VDD_INT |--- G2D (parent device)
+               |--- MSCL
+               |--- GSCL
+               |--- JPEG
+               |--- MFC
+               |--- HEVC
+               |--- BUS0
+               |--- BUS1
+               |--- BUS2
+               |--- PERIS (Fixed clock rate)
+               |--- PERIC (Fixed clock rate)
+               |--- FSYS  (Fixed clock rate)
+
 Example1:
        Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
        power line (regulator). The MIF (Memory Interface) AXI bus is used to