ARM: dts: exynos: Add labels to all existing power domains

[linux.git] / arch / arm / boot / dts / exynos5420.dtsi

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0154c2e373f83018265a59e19bf0748c3feb3e1c..7dc9dc82afd87edb22cc3f0411a64a6c9a2d064a 100644 (file)
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -277,6 +277,7 @@ gsc_pd: power-domain@10044000 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10044000 0x20>;
                        #power-domain-cells = <0>;
+                       label = "GSC";
                        clocks = <&clock CLK_FIN_PLL>,
                                 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
                                 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
@@ -287,6 +288,7 @@ isp_pd: power-domain@10044020 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10044020 0x20>;
                        #power-domain-cells = <0>;
+                       label = "ISP";
                };
 
                mfc_pd: power-domain@10044060 {
@@ -297,18 +299,21 @@ mfc_pd: power-domain@10044060 {
                                 <&clock CLK_ACLK333>;
                        clock-names = "oscclk", "clk0","asb0";
                        #power-domain-cells = <0>;
+                       label = "MFC";
                };
 
                msc_pd: power-domain@10044120 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10044120 0x20>;
                        #power-domain-cells = <0>;
+                       label = "MSC";
                };
 
                disp_pd: power-domain@100440C0 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x100440C0 0x20>;
                        #power-domain-cells = <0>;
+                       label = "DISP";
                        clocks = <&clock CLK_FIN_PLL>,
                                 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
                                 <&clock CLK_MOUT_USER_ACLK300_DISP1>,