Merge tag 'imx-dt64-tmu-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawngu...

[linux.git] / arch / arm64 / boot / dts / freescale / imx8mm.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 58b8cd06cae78e7866f8a3a2d4e3ba0617fa0834..10a07108ea649160aaff08ab3a085aa8ea7a381a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -12,7 +12,6 @@
 #include "imx8mm-pinfunc.h"
 
 / {
-       compatible = "fsl,imx8mm";
        interrupt-parent = <&gic>;
        #address-cells = <2>;
        #size-cells = <2>;
@@ -426,7 +425,7 @@ gpr: iomuxc-gpr@30340000 {
                        };
 
                        ocotp: ocotp-ctrl@30350000 {
-                               compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
+                               compatible = "fsl,imx8mm-ocotp", "syscon";
                                reg = <0x30350000 0x10000>;
                                clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
                                /* For nvmem subnodes */
@@ -479,14 +478,18 @@ clk: clock-controller@30380000 {
                                                <&clk IMX8MM_CLK_AUDIO_AHB>,
                                                <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
                                                <&clk IMX8MM_SYS_PLL3>,
-                                               <&clk IMX8MM_VIDEO_PLL1>;
+                                               <&clk IMX8MM_VIDEO_PLL1>,
+                                               <&clk IMX8MM_AUDIO_PLL1>,
+                                               <&clk IMX8MM_AUDIO_PLL2>;
                                assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
                                                         <&clk IMX8MM_SYS_PLL1_800M>;
                                assigned-clock-rates = <0>,
                                                        <400000000>,
                                                        <400000000>,
                                                        <750000000>,
-                                                       <594000000>;
+                                                       <594000000>,
+                                                       <393216000>,
+                                                       <361267200>;
                        };
 
                        src: reset-controller@30390000 {
@@ -698,8 +701,6 @@ usdhc1: mmc@30b40000 {
                                         <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
                                         <&clk IMX8MM_CLK_USDHC1_ROOT>;
                                clock-names = "ipg", "ahb", "per";
-                               assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
-                               assigned-clock-rates = <400000000>;
                                fsl,tuning-start-tap = <20>;
                                fsl,tuning-step= <2>;
                                bus-width = <4>;
@@ -728,8 +729,6 @@ usdhc3: mmc@30b60000 {
                                         <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
                                         <&clk IMX8MM_CLK_USDHC3_ROOT>;
                                clock-names = "ipg", "ahb", "per";
-                               assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
-                               assigned-clock-rates = <400000000>;
                                fsl,tuning-start-tap = <20>;
                                fsl,tuning-step= <2>;
                                bus-width = <4>;