arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file

[linux.git] / arch / arm64 / boot / dts / marvell / armada-cp11x.dtsi

diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 3e77cf34604c4a9800f94780c0cc3ebd4049644d..7d1ab097453d218e2b87e7cd360252cf8714dd15 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -10,7 +10,6 @@
 
 #include "armada-common.dtsi"
 
-#define CP11X_PCIEx_IO_BASE(iface)     (CP11X_PCIE_IO_BASE + (iface *  0x10000))
 #define CP11X_PCIEx_MEM_BASE(iface)    (CP11X_PCIE_MEM_BASE + (iface *  0x1000000))
 #define CP11X_PCIEx_CONF_BASE(iface)   (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
 
@@ -507,11 +506,8 @@ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
                msi-parent = <&gic_v2m0>;
 
                bus-range = <0 0xff>;
-               ranges =
-               /* downstream I/O */
-               <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0  CP11X_PCIEx_IO_BASE(0) 0 0x10000
                /* non-prefetchable memory */
-               0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
                interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
@@ -534,11 +530,8 @@ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
                msi-parent = <&gic_v2m0>;
 
                bus-range = <0 0xff>;
-               ranges =
-               /* downstream I/O */
-               <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0  CP11X_PCIEx_IO_BASE(1) 0 0x10000
                /* non-prefetchable memory */
-               0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
@@ -562,11 +555,8 @@ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
                msi-parent = <&gic_v2m0>;
 
                bus-range = <0 0xff>;
-               ranges =
-               /* downstream I/O */
-               <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0  CP11X_PCIEx_IO_BASE(2) 0 0x10000
                /* non-prefetchable memory */
-               0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
                interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;