Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[linux.git] / arch / arm64 / boot / dts / mediatek / mt8173.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40a02b29213e58a3049b4807161527a9d82f2366..6922252f317bca508d1c8797dfc06941f5543859 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -182,12 +182,12 @@ cooling-maps {
                                map@0 {
                                        trip = <&target>;
                                        cooling-device = <&cpu0 0 0>;
-                                       contribution = <1024>;
+                                       contribution = <3072>;
                                };
                                map@1 {
                                        trip = <&target>;
                                        cooling-device = <&cpu2 0 0>;
-                                       contribution = <2048>;
+                                       contribution = <1024>;
                                };
                        };
                };
@@ -401,6 +401,11 @@ iommu: iommu@10205000 {
                efuse: efuse@10206000 {
                        compatible = "mediatek,mt8173-efuse";
                        reg = <0 0x10206000 0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       thermal_calibration: calib@528 {
+                               reg = <0x528 0xc>;
+                       };
                };
 
                apmixedsys: clock-controller@10209000 {
@@ -574,6 +579,8 @@ thermal: thermal@1100b000 {
                        resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
                        mediatek,auxadc = <&auxadc>;
                        mediatek,apmixedsys = <&apmixedsys>;
+                       nvmem-cells = <&thermal_calibration>;
+                       nvmem-cell-names = "calibration-data";
                };
 
                nor_flash: spi@1100d000 {
@@ -780,6 +787,8 @@ mmsys: clock-controller@14000000 {
                        compatible = "mediatek,mt8173-mmsys", "syscon";
                        reg = <0 0x14000000 0 0x1000>;
                        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+                       assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+                       assigned-clock-rates = <400000000>;
                        #clock-cells = <1>;
                };