arm64/sve: System register and exception syndrome definitions

[linux.git] / arch / arm64 / include / asm / sysreg.h

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 609d59afe3891c20e3f07b3b3e96e063d36bc699..08cc88574659cec177bbeb88b9d3bb953ad01517 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -145,6 +145,7 @@
 
 #define SYS_ID_AA64PFR0_EL1            sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1            sys_reg(3, 0, 0, 4, 1)
+#define SYS_ID_AA64ZFR0_EL1            sys_reg(3, 0, 0, 4, 4)
 
 #define SYS_ID_AA64DFR0_EL1            sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1            sys_reg(3, 0, 0, 5, 1)
@@ -163,6 +164,8 @@
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
 #define SYS_CPACR_EL1                  sys_reg(3, 0, 1, 0, 2)
 
+#define SYS_ZCR_EL1                    sys_reg(3, 0, 1, 2, 0)
+
 #define SYS_TTBR0_EL1                  sys_reg(3, 0, 2, 0, 0)
 #define SYS_TTBR1_EL1                  sys_reg(3, 0, 2, 0, 1)
 #define SYS_TCR_EL1                    sys_reg(3, 0, 2, 0, 2)
@@ -346,6 +349,8 @@
 
 #define SYS_PMCCFILTR_EL0              sys_reg (3, 3, 14, 15, 7)
 
+#define SYS_ZCR_EL2                    sys_reg(3, 4, 1, 2, 0)
+
 #define SYS_DACR32_EL2                 sys_reg(3, 4, 3, 0, 0)
 #define SYS_IFSR32_EL2                 sys_reg(3, 4, 5, 0, 1)
 #define SYS_FPEXC32_EL2                        sys_reg(3, 4, 5, 3, 0)
@@ -432,6 +437,7 @@
 #define ID_AA64ISAR1_DPB_SHIFT         0
 
 /* id_aa64pfr0 */
+#define ID_AA64PFR0_SVE_SHIFT          32
 #define ID_AA64PFR0_GIC_SHIFT          24
 #define ID_AA64PFR0_ASIMD_SHIFT                20
 #define ID_AA64PFR0_FP_SHIFT           16
@@ -440,6 +446,7 @@
 #define ID_AA64PFR0_EL1_SHIFT          4
 #define ID_AA64PFR0_EL0_SHIFT          0
 
+#define ID_AA64PFR0_SVE                        0x1
 #define ID_AA64PFR0_FP_NI              0xf
 #define ID_AA64PFR0_FP_SUPPORTED       0x0
 #define ID_AA64PFR0_ASIMD_NI           0xf
@@ -541,6 +548,20 @@
 #endif
 
 
+/*
+ * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
+ * are reserved by the SVE architecture for future expansion of the LEN
+ * field, with compatible semantics.
+ */
+#define ZCR_ELx_LEN_SHIFT      0
+#define ZCR_ELx_LEN_SIZE       9
+#define ZCR_ELx_LEN_MASK       0x1ff
+
+#define CPACR_EL1_ZEN_EL1EN    (1 << 16) /* enable EL1 access */
+#define CPACR_EL1_ZEN_EL0EN    (1 << 17) /* enable EL0 access, if EL1EN set */
+#define CPACR_EL1_ZEN          (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
+
+
 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
 #define SYS_MPIDR_SAFE_VAL             (1UL << 31)